MOTOROLA MTP9N25

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by MTP9N25E/D
SEMICONDUCTOR TECHNICAL DATA
 
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
9.0 AMPERES
250 VOLTS
RDS(on) = 0.45 OHM
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature

D
G
S
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
250
Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
VDGR
250
Vdc
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
9.0
5.7
32
Adc
Total Power Dissipation
Derate above 25°C
PD
80
0.64
Watts
W/°C
TJ, Tstg
– 55 to 150
Rating
Operating and Storage Temperature Range
Apk
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 3.0 mH, RG = 25 Ω)
EAS
Thermal Resistance — Junction to Case
— Junction to Ambient
RθJC
RθJA
1.56
62.5
°C/W
TL
260
°C
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
mJ
122
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
TMOS
 Motorola
Motorola, Inc.
1995
Power MOSFET Transistor Device Data
1
MTP9N25E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
250
—
—
328
—
—
Vdc
mV/°C
—
—
—
—
10
100
—
—
100
nAdc
2.0
—
3.0
7.0
4.0
—
Vdc
mV/°C
—
0.37
0.45
Ohm
—
—
3.5
—
5.4
4.7
gFS
3.0
5.2
—
mhos
Ciss
—
783
1100
pF
Coss
—
144
200
Crss
—
32
65
td(on)
—
10
20
tr
—
36
70
td(off)
—
27
55
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
µAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 4.5 Adc)
RDS(on)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 9.0 Adc)
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 4.5 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 125 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(See Figure 8)
(VDS = 200 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc)
tf
—
26
50
QT
—
26
40
Q1
—
4.8
—
Q2
—
12.7
—
Q3
—
9.2
—
—
—
0.9
0.81
1.5
—
trr
—
191
—
ta
—
126
—
tb
—
65
—
QRR
—
1.387
—
—
—
3.5
4.5
—
—
—
7.5
—
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 9.0 Adc, VGS = 0 Vdc)
(IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 14)
(IS = 9.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
nH
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP9N25E
TYPICAL ELECTRICAL CHARACTERISTICS
I D , DRAIN CURRENT (AMPS)
18
VGS = 10 V
TJ = 25°C
9V
15
VDS ≥ 10 V
8V
7V
I D , DRAIN CURRENT (AMPS)
18
12
9
6V
6
3
100°C
9
6
0
0
2
4
6
8
10
2
12
3
4
5
6
7
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
1.2
VGS = 10 V
1.0
0.8
TJ = 100°C
0.6
25°C
0.4
0.2
– 55°C
0
0
3
6
9
12
ID, DRAIN CURRENT (AMPS)
15
18
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
25°C
12
3
5V
0
8
0.6
TJ = 25°C
0.5
VGS = 10 V
0.4
15 V
0.3
0
Figure 3. On–Resistance versus Drain Current
and Temperature
3
6
9
12
ID, DRAIN CURRENT (AMPS)
15
18
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1000
2.5
VGS = 0 V
VGS = 10 V
ID = 4.5 A
2.0
TJ = 125°C
100
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
TJ = –55°C
15
1.5
1.0
100°C
10
25°C
1
0.5
0
–50
0.1
–25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. On–Resistance Variation with
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
0
50
150
100
200
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
250
Figure 6. Drain–To–Source Leakage
Current versus Voltage
3
MTP9N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
2000
VDS = 0 V
1600
C, CAPACITANCE (pF)
VGS = 0 V
TJ = 25°C
Ciss
1200
Ciss
Crss
800
Coss
400
0
Crss
10
5
0
VGS
5
10
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
240
12
180
QT
VGS
8
Q1
120
Q2
ID = 9 A
TJ = 25°C
4
60
Q3
0
VDS
0
6
12
18
QG, TOTAL GATE CHARGE (nC)
24
0
30
1000
t, TIME (ns)
16
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTP9N25E
VDD = 250 V
ID = 9 A
VGS = 10 V
TJ = 25°C
100
tr
td(off)
10
1
tf
td(on)
1
10
100
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
I S , SOURCE CURRENT (AMPS)
9.0
VGS = 0 V
TJ = 25°C
7.5
6.0
4.5
3.0
1.5
0
0.5
0.55
0.6
0.7
0.8
0.65
0.75
0.85
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
0.9
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
5
MTP9N25E
SAFE OPERATING AREA
125
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10 µs
10
100 µs
1
1 ms
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
dc
1.0
100
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
ID = 9 A
100
75
50
25
0
1000
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
25
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
0.01
t1
SINGLE PULSE
0.01
0.00001
t2
DUTY CYCLE, D = t1/t2
0.0001
0.001
0.01
0.1
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0
10
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
MTP9N25E
PACKAGE DIMENSIONS
–T–
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
SEATING
PLANE
C
F
T
S
4
A
Q
1 2 3
U
STYLE 5:
PIN 1.
2.
3.
4.
H
K
Z
L
GATE
DRAIN
SOURCE
DRAIN
R
V
J
G
D
N
CASE 221A–06
ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
–––
–––
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
–––
–––
2.04
7
MTP9N25E
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8
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*MTP9N25E/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTP9N25E/D