Order this document by MTW33N10E/D SEMICONDUCTOR TECHNICAL DATA ' !&" $ " ##$!" ' &$ #!$ !% $ Motorola Preferred Device ! N-Channel Enhancement-Mode Silicon Gate TMOS POWER FET 33 AMPERES 100 VOLTS RDS(on) = 0.06 OHM This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Isolated Mounting Hole Reduces Mounting Hardware D N-Channel G CASE 340F, Style 1 TO-247AE S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain-Source Voltage VDSS 100 Vdc Drain-Gate Voltage (RGS = 1.0 MΩ) VDGR 100 Vdc Gate-Source Voltage — Continuous Gate-Source Voltage — Non-Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous @ 25°C — Continuous @ 100°C — Single Pulse (tp ≤ 10 µs) ID ID IDM 33 20 99 Adc Total Power Dissipation @ TC = 25°C Derate above 25°C PD 125 1.0 Watts W/°C TJ, Tstg – 55 to 150 °C EAS 545 mJ RθJC RθJA 1.0 40 °C/W TL 260 °C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 33 Apk, L = 1.000 mH, RG = 25 Ω) Thermal Resistance — Junction to Case — Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds Apk Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E-FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. 3/94 MTW33N10E Motorola, Inc. 1994 MTW33N10E 1 MOTOROLA MOTOROLA 1 1 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 2.0 — — 7.0 4.0 — Vdc mV/°C — 0.04 0.06 Ohm 100 — — 118 — — Vdc mV/°C — — — — 10 100 — — 100 — — 1.6 — 2.4 2.1 gFS 8.0 — — mhos Ciss — 1830 2500 pF Coss — 678 1200 Crss — 559 1100 td(on) — 18 40 tr — 164 330 td(off) — 48 100 tf — 83 170 QT — 52 110 Q1 — 12 — Q2 — 32 — Q3 — 24 — — — 1.0 0.98 2.0 — trr — 144 — ta — 108 — OFF CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 16.5 Adc) RDS(on) Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = – 25°C) IDSS Gate-Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS µAdc nAdc ON CHARACTERISTICS (1) VDS(on) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 33 Adc) (ID = 16.5 Adc, TJ = – 25°C) Forward Transconductance (VDS = 8.0 Vdc, ID = 16.5 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time (VDD = 50 Vdc, ID = 33 Adc, VGS = 10 Vdc, RG = 9.1 Ω) Fall Time Gate Charge (See Figure 8) (VDS = 80 Vdc, ID = 33 Adc, VGS = 10 Vdc) ns nC SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (1) Reverse Recovery Time (See Figure 14) (IS = 33 Adc, VGS = 0 Vdc) (IS = 33 Adc, VGS = 0 Vdc, TJ = 125°C) (IS = 33 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs) VSD Vdc ns tb — 36 — QRR — 0.93 — µC Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD — 4.5 — nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS — 13 — nH Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. MOTOROLA MOTOROLA 2 2 22 MTW33N10E MTW33N10E TYPICAL ELECTRICAL CHARACTERISTICS 90 90 TJ = 25°C VGS = 10 V 9V 70 60 8V 50 40 7V 30 20 6V 10 5V 0 0 1 2 3 5 4 VDS ≥ 10 V 80 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 80 6 7 9 8 70 60 25°C 50 100°C 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) Figure 1. On-Region Characteristics 0.09 VGS = 10 V 0.08 TJ = 100°C 0.07 0.06 0.05 25°C 0.04 – 55°C 0.03 0.02 0 6 12 24 30 36 48 18 42 ID, DRAIN CURRENT (AMPS) 54 60 66 0.053 TJ = 25°C 0.051 0.049 VGS = 10 V 0.047 0.045 0.043 0.041 15 V 0.039 0.037 5 Figure 3. On-Resistance versus Drain Current and Temperature 17 23 29 35 41 47 ID, DRAIN CURRENT (AMPS) 53 59 65 10000 VGS = 10 V ID = 16.5 A VGS = 0 V 1.6 I DSS , LEAKAGE (nA) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 11 Figure 4. On-Resistance versus Drain Current and Gate Voltage 2.0 1.8 TJ = – 55°C 1.4 1.2 1.0 TJ = 125°C 1000 100°C 100 25°C 0.8 0.6 –50 –25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 5. On-Resistance Variation with Temperature MTW33N10E MTW33N10E 3 150 10 20 30 40 60 80 50 70 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 90 Figure 6. Drain-To-Source Leakage Current versus Voltage MOTOROLA MOTOROLA 3 3 100 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 5000 4000 C, CAPACITANCE (pF) VDS = 0 V Ciss 4500 VGS = 0 V TJ = 25°C Crss 3500 3000 2500 Ciss 2000 1500 Coss 1000 500 Crss 0 10 5 0 VGS 5 10 15 20 25 VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation MOTOROLA MOTOROLA 4 4 44 MTW33N10E MTW33N10E 12 VGS QT 10 100 Q2 8 125 80 Q1 6 60 4 40 Q3 2 0 0 10 VDS 20 30 0 60 50 40 20 1000 VDD = 50 V ID = 33 A VGS = 10 V TJ = 25°C t, TIME (ns) ID = 33 A TJ = 25°C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) tr 100 tf td(off) 10 td(on) 1 10 QG, TOTAL GATE CHARGE (nC) 100 RG, GATE RESISTANCE (OHMS) Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN-TO-SOURCE DIODE CHARACTERISTICS 33 30 27 I S , SOURCE CURRENT (AMPS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 140 14 VGS = 0 V TJ = 25°C 24 21 18 15 12 9 6 3 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 1.05 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance-General Data and Its Use.” Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RθJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For MTW33N10E MTW33N10E 5 reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (I DM ), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. MOTOROLA MOTOROLA 5 5 SAFE OPERATING AREA 550 10 µs VGS = 20 V SINGLE PULSE TC = 25°C 100 10 100 µs 0.0 1 ms 1.0 10 ms dc 0.1 0.01 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 0.1 10 500 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 ID = 33 A 450 400 350 300 250 200 150 100 50 0 25 100 50 75 100 125 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 0.01 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t,TIME (ms) 0.1 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RθJC(t) 1.0 10 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform MOTOROLA MOTOROLA 6 6 66 MTW33N10E MTW33N10E PACKAGE DIMENSIONS φ 0.25 (0.010) M T B M -T- -Q- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. 340F-01 AND -02 OBSOLETE, NEW STANDARD 340F-03. E -BC 4 U L A STYLE 1: PIN 1. 2. 3. 4. R 1 2 3 -Y- K P F D 0.25 (0.010) M Y Q S H V G J GATE DRAIN SOURCE DRAIN DIM A B C D E F G H J K L P Q R U V MILLIMETERS MIN MAX 20.40 20.90 15.44 15.95 4.70 5.21 1.09 1.30 1.50 1.63 1.80 2.18 5.45 BSC 2.56 2.87 0.48 0.68 15.57 16.08 7.26 7.50 3.10 3.38 3.50 3.70 3.30 3.80 5.30 BSC 3.05 3.40 INCHES MIN MAX 0.803 0.823 0.608 0.628 0.185 0.205 0.043 0.051 0.059 0.064 0.071 0.086 0.215 BSC 0.101 0.113 0.019 0.027 0.613 0.633 0.286 0.295 0.122 0.133 0.138 0.145 0.130 0.150 0.209 BSC 0.120 0.134 CASE 340F-03 MTW33N10E MTW33N10E 7 MOTOROLA MOTOROLA 7 7 Motorola reserves the right to make changes without further notice to any products herein. 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