Order this document by MTW8N60E/D SEMICONDUCTOR TECHNICAL DATA "'# % #!$$%"# '% $" % "&!%! " N–Channel Enhancement–Mode Silicon Gate This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Robust High Voltage Termination • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Isolated Mounting Hole Reduces Mounting Hardware Motorola Preferred Device TMOS POWER FET 8.0 AMPERES 600 VOLTS RDS(on) = 0.55 OHM D G CASE 340K–01, Style 1 TO–247AE S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–Source Voltage VDSS 600 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 600 Vdc Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGS VGSM ± 20 ± 40 Vdc Vpk Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) ID ID IDM 8.0 6.4 24 Adc Total Power Dissipation Derate above 25°C PD 180 1.43 Watts W/°C TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 24 Apk, L = 3.0 mH, RG = 25 Ω) EAS 864 mJ Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient RθJC RθJA 0.70 40 °C/W TL 260 °C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Apk Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 4 TMOS Motorola Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1 MTW8N60E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 600 — — 695 — — Vdc mV/°C — — — — 10 100 — — 100 nAdc 2.0 — 3.0 7.0 4.0 — Vdc mV/°C — 0.46 0.55 Ohm — — 3.2 — 4.8 4.6 gFS 4.0 8.5 — mhos Ciss — 2480 3470 pF Coss — 247 346 Crss — 56 120 td(on) — 23.6 50 tr — 37.6 70 td(off) — 80 170 OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 600 Vdc, VGS = 0 Vdc) (VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS µAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 4.0 Adc) RDS(on) Drain–Source On–Voltage (VGS = 10 Vdc) (ID = 8.0 Adc) (ID = 4.0 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 4.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, Vdc VGS = 0 Vdc, Vdc f = 1.0 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn–On Delay Time Rise Time Turn–Off Delay Time (VDD = 300 Vdc, 8.0 Adc, Vd ID = 8 0 Ad VGS = 10 Vdc Vdc, RG = 9.1 Ω)) Fall Time Gate Charge (See Figure 8) (VDS = 300 Vdc, Vd ID = 8 8.0 0 Ad Adc, VGS = 10 Vdc) tf — 48 95 QT — 67 100 Q1 — 17 — Q2 — 26 — Q3 — 27 — — — 0.829 0.71 1.1 — trr — 381 — ta — 225 — ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (1) (IS = 8.0 Adc, VGS = 0 Vdc) (IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (See Figure 14) ((IS = 8 8.0 0 Ad Adc,, VGS = 0 Vdc, Vd , dIS/dt = 100 A/µs) VSD Vdc ns tb — 156 — QRR — 4.61 — µC Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) LD — 4.5 — nH Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS — 13 — nH Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data