SN74LS259 8-Bit Addressable Latch The SN74LS259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. The device also incorporates an active LOW common Clear for resetting all latches, as well as, an active LOW Enable. • • • • • • http://onsemi.com LOW POWER SCHOTTKY Serial-to-Parallel Conversion Eight Bits of Storage With Output of Each Bit Available Random (Addressable) Data Entry Active High Demultiplexing or Decoding Capability Easily Expandable Common Clear GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Device Package Shipping SN74LS259N 16 Pin DIP 2000 Units/Box SN74LS259D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS259/D SN74LS259 CONNECTION DIAGRAM DIP (TOP VIEW) VCC C E D Q7 Q6 Q5 Q4 16 15 14 13 12 11 10 9 1 Ao 2 A1 3 A2 4 Q0 5 Q1 6 Q2 7 Q3 8 GND LOADING (Note a) PIN NAMES A0, A1, A2 D E C Q0 – Q7 Address Inputs Data Input Enable (Active LOW) Input Clear (Active LOW) Input Parallel Latch Outputs NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. http://onsemi.com 2 HIGH LOW 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 5 U.L. SN74LS259 LOGIC DIAGRAM E 14 D A0 13 A1 1 A2 2 C 3 15 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 4 6 5 Q0 Q1 7 Q2 9 Q3 10 Q4 11 Q5 12 Q6 Q7 FUNCTIONAL DESCRIPTION other inputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the SN74LS259 as an addressable latch, changing more then one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The truth table below summarizes the operations. The SN74LS259 has four modes of operation as shown in the mode selection table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch.The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state of the D input with all TRUTH TABLE PRESENT OUTPUT STATES MODE SELECTION E C MODE L H L H H L H L Addressable Latch Memory Active HIGH Eight-Channel Demultiplexer Clear X = Don’t Care Condition L = LOW Voltage Level H = HIGH Voltage Level QN–1 = Previous Output State C E D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MODE L L L L L • • • • • L X L L L L L L H L L L L L L H L L L L L L L L L L L L L L L L L L L L L L L L L Clear Demultiplex H L L L L L L L L • • • • • L L L L H QN–1 QN–1 L H QN–1 QN–1 QN–1 QN–1 H L L L L • • • • • L X L H L H • • • • • H X L L H H H X L L L L • • • • • H H H X X X X QN–1 H H H H • • • • • H H L L H H L L L L • • • • • H H L L L L L H I L L L • • • • • L L I H L H • • • • • L H H H H H QN–1 QN–1 Memory QN–1 QN–1 http://onsemi.com 3 QN–1 Addressable Latch • • • • • QN–1 QN–1 L H SN74LS259 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max 2.0 0.8 – 0.65 2.7 – 1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 36 mA VCC = MAX –20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Typ Max Unit tPLH tPHL Symbol Turn-Off Delay, Enable to Output Turn-On Delay, Enable to Output Parameter 22 15 35 24 ns ns tPLH tPHL Turn-Off Delay, Data to Output Turn-On Delay, Data to Output 20 13 32 21 ns ns tPLH tPHL Turn-Off Delay, Address to Output Turn-On Delay, Address to Output 24 18 38 29 ns ns tPHL Turn-On Delay, Clear to Output 17 27 ns Min Test Conditions CL = 15 pF AC SET-UP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit ts Input Setup Time 20 ns tW Pulse Width, Clear or Enable 15 ns th Hold Time, Data 5.0 ns th Hold Time, Address 20 ns http://onsemi.com 4 SN74LS259 AC WAVEFORMS D 1.3 V D tw 1.3 V tw E Q 1.3 V tPHL tPHL tPLH 1.3 V 1.3 V tPLH OTHER CONDITIONS: E = L, C = H, A = STABLE 1.3 V Q Figure 2. Turn-on and Turn-off Delays, Data to Output OTHER CONDITIONS: C = H, A = STABLE Figure 1. Turn-on and Turn-off Delays, Enable To Output and Enable Pulse Width A1 1.3 V 1.3 V 1.3 V A1 D E 1.3 V tPHL Q1 1.3 V Q=D Q th(L) 1.3 V Q=D OTHER CONDITIONS: C = H, A = STABLE OTHER CONDITIONS: E = L, C = L, D = H Figure 4. Setup and Hold Time, Data to Enable Figure 3. Turn-on and Turn-off Delays, Address to Output 1.3 V STABLE ADDRESS A ts tPHL 1.3 V Q ts(L) tPLH 1.3 V C th(H) ts(H) E OTHER CONDITIONS: E = H Figure 5. Turn-on Delay, Clear to Output OTHER CONDITIONS: C = H Figure 6. Setup Time, Address to Enable (See Notes 1 and 2) NOTES: 1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The shaded areas indicate when the inputs are permitted to change for predictable output performance. http://onsemi.com 5 SN74LS259 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 6 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SN74LS259 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS259 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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