K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Document Title
128M x 8 Bit NAND Flash Memory
Revision History
History
Draft Date
0.0
0.1
1. Initial issue
1.[Page 31] device code (76h) --> device code (79h)
Apr. 7th 2001
Jul. 3rd 2001
0.2
1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
Jul. 23th 2001
≈
Revision No
2.5V
Remark
2.5V
High
≈
VCC
WE
1µ
≈
WP
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. [Page28] Only address A 14 to A 25 is valid while A9 to A 13 is ignored
--> Only address A 14 to A 26 is valid while A 9 to A 13 is ignored
0.3
(page 30)
Sep. 13th 2001
A14 and A15 must be the same between source and target page
--> A14 , A15 and A26 must be the same between source and target page
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
128M x 8 Bit NAND Flash Memory
Features
General Description
• Voltage Supply : 2.7V~3.6V
• Organization
- Memory Cell Array : (128M + 4,096K)bit x 8bit
- Data Register : (512 + 16)bit x8bit multipled by eight planes
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
• 528-Byte Page Read Operation
- Random Access : 12µ s(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back Operation
• Package :
- K9K1G08U0M-YCB0, K9K1G08U0M-YIB0 :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
• Simultaneous Four Page/Block Program/Erase
The K9K1G08U0M is a 128M(134,217,728)x8bit NAND Flash
Memory with a spare 4.096K(4,194,304)x8bit. Its NAND cell
provides the most cost-effective solution for the solid state
mass storage market. A program operation can be performed
in typical 200µs on the 528-byte page and an erase operation
can be performed in typical 2ms on a 16K-byte block. Data in
the page can be read out at 50ns cycle time per byte. The I/O
pins serve as the ports for address and data input/output as
well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of
data. Even the write-intensive systems can take advantage of
the K9K1G08U0M’s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. The K9K1G08U0M-YCB0/YIB0 is an
optimum solution for large nonvolatile storage applications such
as solid state file storage and other portable applications requiring non-volatility.
Pin Configuration
N.C
N.C
N.C
N.C
N.C
N.C
R/ B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
Pin Description
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Pin Name
I/O0 ~ I/O 7
Data Input/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
R/B
Ready/Busy output
V CC
Power(+2.7V~3.6V)
V SS
Ground
N.C
No Connection
NOTE : Connect all VCC and V SS pins of each device to common power supply outputs.
Do not leave V CC or VSS disconnected.
2
Pin Function
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Figure 1. Functional Block Diagram
V CC
V SS
A9 - A 26
X-Buffers
Latches
& Decoders
A0 - A7
Y-Buffers
Latches
& Decoders
1,024M + 32M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 262,144
Page Register & S/A
A8
Y-Gating
Command
Command
Register
CE
RE
WE
V CC
V SS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2. Array Organization
1 Block = 32 Pages
(16K + 512) Byte
256K Pages
(=8,192 Blocks)
1st half Page Register
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
1 Page = 528 Bytes
1 Block = 528 B x 32 Pages
= (16K + 512) Bytes
1 Device = 528B x 32Pages x 8,192 Blocks
= 1,056 Mbits
8 bit
512B Bytes
16 Bytes
I/O 0 ~ I/O 7
Page Register
512 Bytes
16 Bytes
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
Column Address
2nd Cycle
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
Row Address
(Page Address)
3rd Cycle
A 17
A 18
A 19
A 20
A 21
A 22
A 23
A 24
4th Cycle
A 25
A 26
*L
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
3
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Product Introduction
The K9K1G08U0M is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 16,384 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 8,192 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9K1G08U0M.
The K9K1G08U0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 128M byte physical space
requires 27 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row
address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In
Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific c ommands into the command register. Table 1 defines the specific commands of the K9K1G08U0M.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block ou t of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burstreading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
Function
1st. Cycle
2nd. Cycle
3rd. Cycle
Read 1
00h/01h (1)
-
-
Read 2
50h
-
-
Read ID
90h
-
-
Reset
FFh
-
-
80h
10h
-
80h
11h
-
00h
8Ah
10h
03h
8Ah
11h
Page Program (True)
(2)
Page Program (Dummy)(2)
Copy-Back Program(True)
(2)
Copy-Back Program(Dummy) (2)
Block Erase
Multi-Plane Block Erase
Read Status
Read Multi-Plane Status
Acceptable Command
during Busy
O
60h
D0h
-
60h----60h
D0h
-
70h
-
-
O
71h (3)
-
-
O
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.
Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation.
3. The 71h command should be used for read status of Multi Plane operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
4
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Memory Map
The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows
it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory
array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohibited.
Figure 3. Memory Array Map
Plane 0
(1024 Block)
Block 0
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 2
Block 1
Plane 3
(1024 Block)
Block 3
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 30
Page 30
Page 30
Page 31
Page 31
Page 31
Page 31
Block 4092
Block 4094
Block 4093
Block 4095
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 30
Page 30
Page 30
Page 31
Page 31
Page 31
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
Plane 5
(1024 Block)
Plane 6
(1024 Block)
Plane 7
(1024 Block)
Plane 4
(1024 Block)
Block 4096
Block 4098
Block 4097
Block 4099
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 30
Page 31
Page 30
Page 30
Page 31
Page 31
Page 31
Block 8188
Block 8190
Block 8189
Block 8191
Page 0
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
528byte Page Registers
528byte Page Registers
528byte Page Registers
528byte Page Registers
5
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Pin Description
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising ed ge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/ B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
6
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
K9K1G08U0M-YCB0
Symbol
Rating
V IN
-0.6 to + 4.6
V CC
-0.6 to + 4.6
V
-10 to +125
TBIAS
K9K1G08U0M-YIB0
Storage Temperature
Unit
°C
-40 to +125
TSTG
°C
-65 to +150
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC, +0.3V which, during transitions, may overshoot to VC C +2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
(Voltage reference to GND, K9K1G08U0M-YCB0 :T A=0 to 70°C, K9K1G08U0M-YIB0 : TA=-40 to 85°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
V CC
2.7
3.3
3.6
V
Supply Voltage
V SS
0
0
0
V
Dc and Operating Characteristics (Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Symbol
Test Conditions
tRC=50ns, CE = VIL , IOUT=0mA
Min
Typ
Max
Sequential Read
ICC1
-
10
30
Program
ICC2
-
-
10
30
Erase
ICC3
-
-
10
30
1
Stand-by Current(TTL)
ISB 1
CE=VIH, WP= 0V/V CC
-
-
Stand-by Current(CMOS)
ISB 2
CE=VCC-0.2, WP = 0V/V CC
-
10
50
ILI
V IN=0 to 3.6V
-
-
±10
Output Leakage Current
ILO
V OUT=0 to 3.6V
Input High Voltage
V IH
Input Leakage Current
-
-
±10
-
2.0
-
V CC+0.3
-
-0.3
-
0.8
2.4
-
-
Input Low Voltage, All inputs
V IL
Output High Voltage Level
V OH
IOH=-400µA
Output Low Voltage Level
V OL
IOL =2.1mA
-
-
0.4
Output Low Current(R/B)
IOL (R/B)
V OL =0.4V
8
10
-
7
Unit
mA
µA
V
mA
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Valid Block
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
8,052
-
8,192
Blocks
NOTE :
1. The K9K1G08U0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits . Do not erase
or program factory-marked bad blocks. Refer to the attached technical notes for an appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correcti on.
AC Test Condition
(K9K1G08U0M-YCB0 :TA=0 to 70°C, K9K1G08U0M-YIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL=100pF
Capacitance( TA=25°C, VCC =3.3V, f=1.0MHz)
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
Item
C I/O
V IL =0V
-
20
pF
Input Capacitance
CIN
V I N=0V
-
20
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
H
L
L
H
H
L
L
L
L
L
L
L
H
L
L
L
H
X
X
X
X
X
X
X
X
RE
WP
L
H
X
L
H
X
L
L
H
H
H
L
H
H
H
H
Data Input
X
Sequential Read & Data Output
H
X
During Read(Busy)
X
X
H
During Program(Busy)
X
X
H
During Erase(Busy)
X
X
X
L
Write Protect
H
X
X
0V/V CC(2)
X
(1)
X
WE
Mode
Read Mode
Command Input
Address Input(4clock)
Write Mode
Command Input
Address Input(4clock)
Stand-by
NOTE : 1. X can be VIL or V IH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG
-
200
500
µs
Dummy Busy Time for Multi Plane Program
tDBSY
1
10
µs
-
-
1
cycle
-
-
2
cycles
-
2
3
ms
Number of Partial Program Cycles
in the Same Page
Block Erase Time
Main Array
Spare Array
Nop
tBERS
8
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE setup Time
tCLS
0
-
ns
CLE Hold Time
tCLH
10
-
ns
CE setup Time
tCS
0
-
ns
CE Hold Time
tCH
10
-
ns
WE Pulse Width
tWP
25 (1)
-
ns
ALE setup Time
tALS
0
-
ns
ALE Hold Time
tALH
10
-
ns
Data setup Time
tDS
20
-
ns
Data Hold Time
tDH
10
-
ns
Write Cycle Time
tWC
50
-
ns
WE High Hold Time
tWH
15
-
ns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
Symbol
Min
Max
Unit
tR
-
12
µs
ALE to RE Delay( ID read )
tAR1
10
-
ns
ALE to RE Delay(Read cycle)
tAR2
50
-
ns
CLE to RE Delay
tCLR
50
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
30
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
RE Access Time
tREA
-
35
ns
RE High to Output Hi-Z
tRHZ
15
30
ns
CE High to Output Hi-Z
tCHZ
-
20
ns
RE High Hold Time
tREH
15
-
ns
tI R
0
-
ns
Last RE High to Busy(at sequential read)
tRB
-
100
ns
CE High to Ready(in case of interception by CE at read)
tCRY
-
50 +tr(R/B) (1)
ns
CE Access Time
tCEA
-
45
ns
CE High Hold Time(at the last serial read) (2)
tCEH
100
-
ns
WE High to RE Low
tWHR
60
-
ns
Device Resetting Time(Read/Program/Erase)
tRST
-
5/10/500 (3)
µs
Data Transfer from Cell to Register
Output Hi-Z to RE Low
NOTE :
1. The time to Ready depends on the value of the pull-up resistor tied R/ B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
9
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The i nformation regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to
be a valid block. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error
Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The i nvalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invali d
block has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based
on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
*
Check "FFh" at the column address 517
of the 1st and 2nd page in the block
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 4. Flow chart to create invalid block table.
10
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the ac tual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00h
Write 80h
Write Address
Write Address
Write Data
Wait for tR Time
Write 10h
Verify Data
Read Status Register
No
*
Program Error
Yes
Program Completed
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
Yes
No
No
*
I/O 0 = 0 ?
Yes
11
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
No
Verify ECC
Yes
Yes
*
No
Erase Error
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
{
nth
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
Buffer memory of the controller.
{
Block B
1
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
12
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Pointer Operation of K9K1G08U0M
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effec tive only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command,
the address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting
from ’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 2. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
256 Byte
256 Byte
"A"
"B"
"C" area
(50h plane)
16 Byte
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 5 Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’,’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’ command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
01h
80h
Address / Data input
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’ area can be programmed.
80h
’50h’ command can be omitted.
13
10h
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
WE
≈
≈
CE
ALE
I/O0~7
80h
Start Add.(4Cycle)
t CS
Data Input
t CH
Data Input
10h
t CEA
CE
CE
tREA
RE
tWP
WE
I/O 0~7
out
Figure 7. Read Operation with CE don’t-care.
CLE
CE don’t-care
Must be held
low during tR.
≈
CE
RE
ALE
tR
R/B
WE
I/O0~7
00h
Data Output(sequential)
Start Add.(4Cycle)
14
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
* Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
t ALH
ALE
t DH
t DS
Command
I/O0 ~7
* Address Latch Cycle
t CLS
CLE
tCS
tWC
t WC
tWC
CE
tWP
tWP
t WP
tWP
WE
tWH
t ALH tALS
t ALS
tWH
tALH t ALS
t WH
tALH t ALS
tALH
ALE
tDS
I/O 0~7
tDH
A0~A7
t DS
tDH
A9 ~A16
15
tDS
t DH
A17~A24
tDS
t DH
A25,,A26
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
* Input Data Latch Cycle
t CLH
CLE
tCH
CE
t ALS
tWC
tWP
≈
ALE
tWP
tWP
WE
I/O 0~7
tWH
t DH
t DS
tDH
DIN 1
DIN 0
t DS
≈ ≈
tDS
tDH
DIN 511
* Serial Access Out Cycle after Read (CLE=L, WE=H, ALE=L)
tRC
≈
CE
tREH
tREA
≈
t REA
t REA
tCHZ*
RE
t RHZ*
I/O0~7
Dout
Dout
≈
tRHZ*
≈
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
16
Dout
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
* Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
t WP
WE
tCEA
tCHZ*
tWHR
RE
tDS
I/O0 ~7
t DH
tREA
tIR
tRHZ*
Status Output
70h
Read1 Operation (Read One Page)
CLE
tCEH
CE
tCHZ
tWC
WE
tWB
t CRY
t AR2
ALE
tR
t RHZ
t RC
≈
RE
I/O0 ~7
00h or 01h A0 ~ A 7
A 9 ~ A1 6
Column
Address
R/B
A1 7 ~ A2 4
A25, A 2 6
Dout N
Page(Row)
Address
Busy
17
Dout N+1 Dout N+2
≈ ≈
tRR
Dout 527
t RB
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Read1 Operation(Intercepted by CE)
CLE
CE
WE
t WB
tCHZ
tAR2
ALE
tR
tRC
RE
t RR
I/O0 ~7
00h or 01h
A0 ~ A 7
A9 ~ A 16
Column
Address
A 17 ~ A 24
A25, A 2 6
Dout N
Dout N+1
Dout N+2
Page(Row)
Address
R/B
Busy
Read2 Operation (Read One Page)
CLE
CE
WE
tR
t WB
t AR2
ALE
≈
t RR
I/O0 ~7
50h
A 0 ~ A7
A 9 ~ A1 6
A17 ~ A24
Dout
511+M
A25, A2 6
R/B
≈
RE
Dout 527
Selected
Row
M Address
A0 ~A 3 : Valid Address
A4 ~A 7 : Don′t care
512
16
Start
address M
18
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Sequential Row Read Operation ( Within a Block )
CLE
CE
WE
≈
≈
ALE
00h
Dout
N
A0 ~ A7 A9 ~ A1 6 A1 7 ~ A2 4 A 25,A2 6
Dout
N+1
Dout
527
Dout
0
≈
Busy
R/B
Dout
1
Dout
527
≈
Ready
≈
I/O0~7
≈
RE
Busy
M
M+1
N
Output
Output
Page Program Operation
CLE
CE
tWC
≈
tWC
tWC
WE
t WB
t PROG
ALE
I/O0 ~7
80h
A0 ~ A7 A 9 ~ A1 6 A17 ~ A2 4
Sequential Data Column
Input Command Address
Page(Row)
Address
A25,A2 6
Din
N
≈ ≈
RE
Din
10h
527
1 up to 528 Byte Data Program
Serial Input
Command
≈
R/B
70h
19
I/O0
Read Status
Command
I/O0 =0 Successful Program
I/O0 =1 Error in Program
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tWB
tBERS
ALE
RE
I/O0~7
60h
A9 ~ A 16 A 1 7 ~ A 24 A 25,A2 6
DOh
70h
I/O 0
Busy
R/B
Auto Block Erase Setup Command
Erase Command
20
≈
Page(Row)
Address
Read Status
Command
I/O 0=0 Successful Erase
I/O0 =1 Error in Erase
21
R/B
I/O 0~7
RE
ALE
WE
Sequential Data
Input Command
80h
tWC
Max. three time s repe ata ble
Page (Ro w)
Add ress
Din
527
tDBSY : typ. 1us
max. 10us
tDBSY
80h
I/O0 ~7
R/B
80h
A 0 ~ A7 & A9 ~ A2 6
528 Byte Data
Address &
Data Input
11h
tDBSY
80h
A0 ~ A7 & A 9 ~ A2 6
528 Byte Data
Address &
Data Input
11h
80h
Din
N
A 0 ~ A7 & A9 ~ A2 6
528 Byte Data
Ad dress &
Data In put
11h
tDBSY
La st P lane In put & Prog ram
A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26
tDBSY
Ex.) Four-Plane Page Program into Plane 0~3 or Plane 4~7
Column
Address
Din
N
≈
≈ ≈
11h
Program
1 up to 528 Byte Data Command
(Dummy)
Serial Input
A0 ~ A7 A9 ~ A16 A17 ~ A24 A25,A26
tWB
≈
CE
≈
≈ ≈
CLE
tPROG
A0 ~ A7 & A9 ~ A 26
5 28 Byte Data
Add ress &
Data Inp ut
10h
Program Confirm
Command
(True)
80h
Din
527
tWB
≈
Multi-Plane Page Program Operation
71h
t PRO G
10h
I/O
7 1h
Read Multi-Plane
Status Command
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7
CLE
CE
tWC
WE
tWB
tBERS
ALE
RE
I/O0~7
60h
A9 ~ A 16 A 1 7 ~ A 24 A25,A2 6
DOh
71h
I/O 0
Busy
R/B
Block Erase Setup Command
≈
Page(Row)
Address
Erase Confirm Command
Read Multi-Plane
StatusCommand
Max. 4 times repeatable
* For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command.
Ex.) Four-Plane Block Erase Operation
R/B
I/O0~7
tBERS
60h
Address
60h
Address
60h
Address
60h
A9 ~ A2 6
22
Address
D0h
71h
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Read ID Operation
CLE
CE
WE
ALE
RE
t REA
I/O 0 ~ 7
90h
Read ID Command
00h
ECh
Address. 1cycle
79h
Maker Code Device Code
ID Defintition Table
90 ID: Access command = 90H
st
1 Byte
2 n d Byte
3 rd Byte
4 th Byte
Value
Description
ECh
79h
A5h
C0h
Maker Code
Device Code
Must be don’t -cared
Supports Multi Plane Operation
23
A5h
C0h
Multi Plane Code
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Copy-Back Program Operation
CLE
CE
tWC
WE
t WB
tWB tPROG
ALE
tR
RE
A0 ~A7 A9 ~A 1 6 A1 7 ~A2 4 A25,A2 6
Column
Address
R/B
8Ah
A0 ~A 7 A9 ~A1 6 A17 ~A 24 A25,A2 6
Column
Address
Page(Row)
Address
10h
70h
Page(Row)
Address
Busy
Busy
Copy-Back Data
Input Command
24
I/O0
Read Status
Command
≈
00h
≈
I/O 0~7
I/O 0=0 Successful Program
I/O 0=1 Error in Program
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 12µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE . High to low transitions of the RE clock output the data stating from the selected column address up to the last column
address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 12µs again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command. Addresses A 0 to A 3 set the starting address of the spare area while
addresses A4 to A 7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row
read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command(00h/01h) is
needed to move the pointer back to the main area. Figures 8 to 11 show typical sequence and timings for each read operation.
Figure 8. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/O 0~7
00h
Start Add.(4Cycle)
Data Output(Sequential)
A0 ~ A 7 & A 9 ~ A2 6
(00h Command)
1st half array
(01h Command)*
2st half array
Data Field
Spare Field
1st half array
2st half array
Data Field
Spare Field
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
25
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Figure 9. Read2 Operation
CLE
CE
WE
ALE
tR
R/B
RE
50h
I/O0~7
Data Output(Sequential)
Start Add.(4Cycle)
A0 ~ A 3 & A9 ~ A 2 6
Spare Field
( A4 ~ A7 :
Don′t Care)
1st half array
2nd half array
Data Field
Spare Field
tR
R/B
I/O 0 ~ 7
00h
Start Add.(4Cycle)
01h
A 0 ~ A7 & A9 ~ A 26
tR
Data Output
1st
( 00h Command)
1st half array
≈
Figure 10. Sequential Row Read1 Operation
tR
Data Output
Data Output
2nd
(528 Byte)
Nth
(528 Byte)
( 01h Command)
2nd half array
1st half array
2nd half array
1st
2nd
Nth
Block
Data Field
1st
2nd
Nth
Spare Field
Data Field
Spare Field
The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto
the next block, read command and address must be given.
26
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
I/O 0~7
tR
tR
R/B
50h
≈
Figure 11. Sequential Row Read2 Operation
Start Add.(4Cycle)
Data Output
1st
A0 ~ A 3 & A 9 ~ A2 6
tR
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A 4 ~ A7 :
Don′t Care)
1st
Block
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done i n
any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command
are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure
12). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains
in Read Status command mode until another valid command is written to the command register.
Figure 12. Program & Read Status Operation
t PROG
R/B
I/O0~7
80h
Address & Data Input
10h
70h
A0 ~ A7 & A 9 ~ A2 6
528 Byte Data
I/O0
Fail
27
Pass
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A 14 to A 26 is valid while A9 to A 13 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
tBERS
R/B
I/O0~7
60h
Address Input(3Cycle)
Pass
I/O0
70h
D0h
Block Add. : A1 4 ~ A2 6
Fail
Multi-Plane Page Program into Plane 0~3 or Plane 4~7
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Sin c e
the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7
enables a simultaneous programming of four pages. Partial activation of four planes is also permitted.
After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming
process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate
71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,
actual True Page Program (10h) instead of dumy Page Program command (11h) must be followed to start the programming process.
The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages into plane 0~3 or plane 4~7
are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The extended
status bits (I/O1 through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when
any of the pages fails.
Multi-Plane page Program with "01h" pointer is not supported, thus prohibited.
Figure 14. Four-Plane Page Program
tDBSY
R/B
I/O0~7
80h
Address &
11h
Data Input
A0 ~ A7 & A9 ~ A 26
528 Byte Data
80h
11h
t DBSY
80h
Address &
11h
Data Input
A0 ~ A7 & A 9 ~ A2 6
528 Byte Data
Address &
11h
Data Input
A0 ~ A7 & A 9 ~ A2 6
528 Byte Data
80h
tDBSY
80h
80h
11h
11h
tPROG
Address &
10h
Data Input
A0 ~ A 7 & A9 ~ A 26
528 Byte Data
80h
80h
10h
Data
input
Plane 0
(1024 Block)
Plane 1
(1024 Block)
Plane 2
(1024 Block)
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 4088
Block 4092
Block 4089
Block 4093
Block 4090
Block 4094
28
Plane 3
(1024 Block)
Block 4091
Block 4095
71h
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Restriction in addressing with Multi Plane Page Program
While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the
selected pages at one operation must be the same. Figure 15 shows an example where 2nd page of each addressed block is
selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure16.
Figure 15. Multi-Plane Program & Read Status Operation
Plane 1
(1024 Block)
Plane 0
(1024 Block)
Block 0
Block 2
Block 1
Page 0
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Block 3
Page 0
Page 0
Page 0
Page 1
Page 1
Page 1
Page 1
Page 30
Page 30
Page 30
Page 30
Page 31
Page 31
Page 31
Page 31
Figure 16. Addressing Multiple Planes
80h
Plane 2
11h
Plane 0
80h
11h
Plane3
80h
11h
80h
Plane 1
10h
Figure 17. Multi-Plane Page Program & Read Status Operation
t PROG
R/B
Last Plane input
I/O0~7
80h
Address & Data Input
10h
I/O
71h
A0 ~ A7 & A 9 ~ A2 6
528 Byte Data
Pass
Fail
Multi-Plane Block Erase into Plane 0~3 or Plane 4~7
Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three
address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane.
The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy
status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1
through I/O 4).
Figure 18. Four Block Erase Operation
R/B
I/O0~7
t BERS
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
60h
Address
(3 Cycle)
D0h
71h
I/O
A0 ~ A7 & A 9 ~ A2 6
Fail
29
Pass
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Copy-Back Program
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within
the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential
execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read opera tion with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. As soon as the
device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be
written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A14 , A15 and A26 must be the same between source and target page.
Figure19 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation,
error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is
not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for
the use of Copy-Back operation."
Figure 19. One Page Copy-Back program Operation
tR
R/B
I/O 0~7
00h
Add.(4Cycles)
A0 ~ A 7 & A 9 ~ A2 6
Source Address
tPROG
8Ah
Add.(4Cycles)
10h
70h
I/O0
A0 ~ A7 & A 9 ~ A2 6
Destination Address
30
Fail
Pass
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Multi-Plane Copy-Back Program
Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is
equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous Multi-Plane CopyBack programming of four pages. Partial activation of four planes is also permitted.
First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal
page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be execute d
with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may
be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of command sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement
address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane
address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may
be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the
last plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is
supported with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial
page programming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished.
Figure 20. Four-Plane Copy-Back Program
Max Three Times Repeatable
Source
Address
Input
00h
Plane 0
(1024 Block)
03h
03h
03h
Plane 3
(1024 Block)
Plane 2
(1024 Block)
Plane 1
(1024 Block)
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 4088
Block 4092
Block 4089
Block 4090
Block 4093
Block 4094
Block 4091
Block 4095
Max Three Times Repeatable
8Ah
11h
8Ah
11h
8Ah
11h
8Ah
10h
Destination
Address
Input
Plane 0
(1024 Block)
Plane 1
(1024 Block)
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 4088
Block 4092
Block 4089
Block 4093
Block 4090
31
Plane 2
(1024 Block)
Block 4094
Plane 3
(1024 Block)
Block 4091
Block 4095
I/O0 ~7
R/B
00h
Add .( 4Cyc.)
tR
A 0 ~ A7 & A9 ~ A2 5
So urce A ddress
0 3h
32
03h
Ad d.( 4Cyc.)
tR
8Ah
Add.(4Cyc.)
tDBS Y
≈
≈
A0 ~ A7 & A 9 ~ A2 5
S ource A ddress
≈
≈
Add .(4 Cyc.)
11h
Max. 4 times (4 Cycle Destination Address Input) repeatable
Add .(4 Cyc.)
tPROG
10h
A0 ~ A7 & A 9 ~ A2 5
Destination Add ress
8A h
tDBS Y
A0 ~ A7 & A 9 ~ A2 5
Destination Add ress
8Ah
tDBSY : Typical 1us, Max 10us
A0 ~ A7 & A 9 ~ A2 5
Destination Add ress
11h
≈
≈
Max. 4 times ( 4 Cycle Source Address Input) repeatable
tR : Normal Read Busy
A 0 ~ A7 & A9 ~ A2 5
So urce A ddress
A dd.( 4Cyc.)
tR
Fig 21. Four-Plane Copy-Back Page Program (Continued)
71h
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether
multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The
pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.
Table4. Read Staus Register Definition
I/O No.
Status
I/O 0
Total Pass/Fail
Definition by 70h Command
Pass : "0"
Definition by 71h Command
Fail : "1"
Pass : "0"(1)
Fail : "1"
I/O 1
Plane 0 Pass/Fail
Must be don’t -cared
Pass : "0"
(2)
I/O 2
Plane 1 Pass/Fail
Must be don’t -cared
Pass : "0"
(2)
Fail : "1"
I/O 3
Plane 2 Pass/Fail
Must be don’t -cared
Pass : "0"(2)
Fail : "1"
I/O 4
Plane 3 Pass/Fail
Must be don’t -cared
Pass : "0"(2)
Fail : "1"
I/O 5
Reserved
Must be don’t -cared
I/O 6
Device Operation
I/O 7
Write Protect
Must be don’t-cared
Busy : "0"
Ready : "1"
Protected : "0"
Fail : "1"
Not Protected : "1"
Busy : "0"
Ready : "1"
Protected : "0"
Not Protected : "1"
NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/
Erase operation, it sets "Fail" flag.
2. The pass/fail status applies only to the corresponding plane.
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacture code(ECh), and the device code (79h), Reserved(A5h), Multi plane operation code(C0h) respectively. A5h must be don’t-cared. C0h means that device supports Multi Plane operation. The command register remains in Read ID mode until further commands are issued to it. Figure 22 shows the operation sequence.
Figure 22. Read ID Operation 1
tCLR
CLE
tCEA
CE
WE
t AR1
ALE
RE
I/O0~7
t WHR
tREA
90h
00h
ECh
Address. 1cycle
Maker code
33
79h
Device code
A5h
C0h
Multi-Plane code
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 23 below.
Figure 23. RESET Operation
tRST
R/B
I/O 0~7
FFh
Table5. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
34
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operatio n. The pin
is an open-drain driver thereby allowing two or more R/ B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 24). Its value can
be determined by the following guidance.
Rp
ibusy
V CC
Ready Vcc
R/B
open drain output
2.0V
0.8V
Busy
tf
tr
GND
Device
Fig 24 Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25 °C
, CL = 100pF
tr ,tf [s]
Ibusy
300n
200n
1.65
290
189
1.1
3m
2m
tr
96
100n
4.2
0.825
tf
1K
4.2
2K
4.2
3K
Rp(ohm)
Rp value guidance
V CC(Max.) - V OL (Max.)
Rp(min) =
IOL + ΣIL
3.2V
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
35
4.2
4K
1m
Ibusy [A]
381
3.3
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Data Protection
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V IL
during power-up and power-down. A recovery time of minimum 10 µs is required before internal circuit gets ready for any command
sequences as shown in Figure 25. The two step command sequence for program/erase provides additional software protection.
≈
Figure 25. AC Waveforms for Power Transition
2.5V
2.5V
High
≈
VCC
≈
WP
10µ s
≈
WE
36
FLASH MEMORY
Package Dimensions
Package Dimensions
48-Pin Lead Plastic Thin Small Out-Line Package Type(I)
48 - TSOP1 - 1220F
0.10
#48
#24
#25
0.50
0 .019 7
12.40
MA X
0.488
( 0.25 )
0.0 10
#1
12.00
0.4 72
+0 .00 3
0.008-0 .0 01
0.2 0 -0 .03
+0.0 7
20.00 ±0.20
0.787± 0.008
0.00 4
MAX
Unit :mm/Inch
1.00± 0.05
0.039 ±0.002
+0 .0 75
0~8 ¡Æ
0.45~0.75
0.018~0.030
+0 .0 03
0 .00 5- 0.0 0 1
18.40± 0.10
0.724± 0.004
0.125 0 .0 35
0.25
0.010 TYP
1.20
0.047 MAX
( 0.50 )
0.020
37
0.05
0.002 MIN
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Datasheets for electronic components.