ST8024T COM/SEG LCD Driver P r e l i m i n a r y Datasheet Version 0.12 2008/01/24 Note: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change. ST8024T 1. FEATURES Number of LCD drive outputs: 240 Supply voltage for LCD drive: +15.0 to +30.0 V Supply voltage for the logic system: +2.5 to +5.5 V Low power consumption Low output impedance (Segment mode) Shift clock frequency 15MHz(MAX.): VDD = +5.0 ± 0.5V 12MHz(MAX.): VDD = +3.0 to + 4.5V 8MHz(MAX.): VDD = +2.5 to + 3.0V Adopts a data bus system 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin Automatic transfer function of an enable signal Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data Line latch circuits are reset when /DISPOFF active 2. (Common mode) Shift clock frequency: 4 MHz (MAX.) Built-in 240-bit bi-directional shift register (divisible into 120 bits x 2) Available in a single mode (240-bit shift register) or in a dual mode (120-bit shift register x 2) Y1->Y240 Single mode Y240->Y1 Single mode Y1->Yl20, Y121->Y240 Dual mode Y240->Y121, Yl20->Y1 Dual mode The above 4 shift directions are pin-selectable Shift register circuits are reset when /DISPOFF active DESCRIPTION The ST8024T is a 240-output segment/common driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/work stations. The ST8024T is good both as a segment driver and a common driver, and it can create a low power consuming, high-resolution LCD. Preliminary Ver 0.12 Page 2/26 2008/01/24 ST8024T 3. BLOCK DIAGRAM V0R FR /DISPOFF V12R V43R VSS Y1 Y2 Y239 Y240 VSS LEVEL SHIFTER 240-BIT 4-LEVEL DRIVER V43L 240 EIO1 EIO2 V12L 240-BIT LEVEL SHIFTER ACTIVE CONTROL V0L 240 240-BIT LINE LATCH/SHIFT REGISTER 16 LP XCK 16 16 8 BIT DATA LATCH CONTROL LOGIC 8 DATA CONTROL L/R MD SP CONVERSION & DATA CONTROL (4 to 8 or 8 to 8) S/C DI0 4. DI1 DI2 DI3 DI4 DI5 DI6 DI7 VDD V SS FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK FUNCTION In case of segment mode, controls the selection or non-selection of the chip. Following an LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. Once data input has been Active Control completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel SP Conversion input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel & Data Control input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time. In case of segment mode, selects the state of the data latch which reads in the data bus Data Latch Control signals. The shift direction is controlled by the control logic. For every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. In case of segment mode, latches the data on the data bus. The latch state of each LCD Data Latch drive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 30 sets of 8 bits. In case of segment mode, all 240 bits which have been read into the data latch are Line Latch/ simultaneously latched at the falling edge of the LP signal, and are output to the level Shift Register shifter block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. Level Shifter The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the driver block. Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4-Level Driver 4 levels (V0, V12, V43 or Vss) based on the S/C, FR and /DISPOFF signals. Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output Control Logic from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip is non-selected. In case of common mode, controls the direction of data shift. Preliminary Ver 0.12 Page 3/26 2008/01/24 ST8024T 5. PIN DESCRIPTION (TCP TYPE) SYMBOL Y1-Y240 V0L, V0R V12L, V12R V43L, V43R L/R VDD S/C I/O O P P P I P I DESCRIPTION LCD drive output Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Display data shift direction selection Power supply for logic system (+2.5 to +5.5 V) Segment mode/common mode selection Input/output for chip selection at segment mode EIO2, EIO1 I/O Shift data input/output for shift register at common mode DI0-DI6 I Display data input at segment mode DI7 I Display data input at segment mode/Dual mode data input at common mode XCK I Clock input for taking display data at segment mode /DISPOFF I Control input for output of non-select level I Latch pulse input for display data at segment mode/ LP Shift clock input for shift register at common mode FR I AC-converting signal input for LCD drive waveform MD I 4 or 8 bits mode selection input VSS P Ground (0 V) TEST1,TEST2 I Connect to GND or floating PS : Detail size see TCP drawing data Preliminary Ver 0.12 Page 4/26 2008/01/24 ST8024T 6. INPUT/OUTPUT CIRCUITS V DD I To Internal Circuit Applicable Pins L/R , S/C , DI6~DI0 , /DISPOFF , LP , FR , MD GND (0V) Figure 1 Input Circuit (1) V DD I To Internal Circuit Applicable Pins DI7 , XCK Control Signal GND (0V) GND (0V) Figure 2 Input Circuit (2) Preliminary Ver 0.12 Page 5/26 2008/01/24 ST8024T V DD To Internal Circuit I/O Control Signal GND (0V) GND (0V) VDD Output Signal Application Pins EIO1 , EIO2 Control Signal GND (0V) Figure 3 Input/Output Circuit V0 V12 V0 Control Signal 1 Control Signal 2 Control Signal 3 Control Signal 4 O GND (0V) V43 GND (0V) Application Pins Y1~Y160 VSS Figure 4 LCD Drive Output Circuit Preliminary Ver 0.12 Page 6/26 2008/01/24 ST8024T 7. FUNCTIONAL DESCRIPTION 7.1 Pin Functions (Segment mode) SYMBOL VDD GND LGND VSS V0L, V0R V12L, V12R V43L, V43R DI7-DI0 XCK LP L/R /DISPOFF FR MD S/C ElO1, EIO2 FUNCTION Logic system power supply pin, Connected to +2.5 to +5.5 V. Ground pin Logic ground pin Do not short LGND with GND and Vss by ITO on LCD panel Connect it to GND on PCB or FPC. Connect to GND by ITO on LCD panel. Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider Ensure that voltages are set such that VSS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin Input pins for display data In 4-bit parallel mode, DI3-DI0 are the display data input pins, and DI7-DI4 must be connected to LGND or VDD. In 8-bit parallel mode, All DI7-Dl0 pins are the display data input pins. Refer to section 7.2.2. Clock input pin for taking display data Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data When set to LGND level "L", data is read sequentially from Y240 to Y1. When set to VDD level "H", data is read sequentially from Y1 to Y240. Refer to section 7.2.2. Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level Vss. When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Mode selection pin When set to LGND level "L", 8-bit parallel input mode is set. When set to VDD level "H", 4-bit parallel input mode is set. Refer to section 7.2.2. Segment mode/common mode selection pin When set to VDD level "H", segment mode is set. Input/output pins for chip selection When L/R input is at LGND level "L", ElO1 is set for output, and EIO2 is set for input. When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output. Preliminary Ver 0.12 Page 7/26 2008/01/24 ST8024T Y1 -Y240 (Common mode) SYMBOL VDD GND LGND VSS V0L, V0R V12L, V12R V43L, V43R ElO1 EIO2 LP L/R /DISPOFF FR MD During output, set to "H" while LP • XCK is "H" and after 240 bits of data have been read, set to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 240 bits of data have been read. LCD drive output pins Corresponding directly to each bit of the data latch, one level (V0, V12, V43, or VSS) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. FUNCTION Logic system power supply pin, connected to +2.5 to +5.5 V. Ground pin Logic ground pin Do not short LGND with GND and Vss by ITO on LCD panel Connect it to GND on PCB or FPC. Connect to GND by ITO on LCD panel. Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that VSS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. Shift data input/output pin for bi-directional shift register Output pin when L/R is at LGND level "L', input pin when L/R is at VDD level "H". When L/R = H, ElO1 is used as input pin, it will be pulled down. When L/R = L, ElO1 is used as output pin, it won't be pulled down. Refer to section 7.2.2. Shift data input/output pin for bi-directional shift register Input pin when L/R is at LGND level "L", output pin when L/R is at VDD level "H". When L/R = L, EIO2 is used as input pin, it will be pulled down. When L/R = H, EIO2 is used as output pin, it won't be pulled down. Refer to section 7.2.2. Shift clock pulse input pin for bi-directional shift register Data is shifted at the falling edge of the clock pulse. Input pin for selecting the shift direction of bi-directional shift register Data is shifted from Y240 to Y1 when set to LGND level "L", and data is shifted from Y1 to Y240 when set to VDD level "H". Refer to section 7.2.2. Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level LGND. When set to "L”, the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Mode selection pin When set to LGND level "L", single mode operation is selected; when set to VDD level Preliminary Ver 0.12 Page 8/26 2008/01/24 ST8024T DI7 S/C DI6-DI0 XCK Y1 -Y240 7.2 7.2.1 "H" dual mode operation is selected. Refer to section 7.2.2. Dual mode data input pin According to the data shift direction of the data shift register, data can be input starting from the 121st bit. When the chip is used in dual mode, DI7 will be pulled down. When the chip is used in single mode, DI7 won't be pulled down. Refer to section 7.2.2. Segment mode/common mode selection pin When set to LGND level "L", common mode is set. Not used Connect DI6-DI0 to LGND or VDD, avoiding floating. Not used XCK is pulled down in common mode, so connect to LGND or open. LCD drive output pins Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Functional Operations Truth table (Segment Mode) FR LATCH DATA L L L H H L H H X X /DISPOFF H H H H L LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240) V43 VSS V12 V0 VSS (Common Mode) LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240) FR LATCH DATA /DISPOFF L L H V43 L H H V0 H L H V12 H H H VSS X X L VSS NOTES: VSS < V43 < V12 < V0 L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage which is assigned by specification for each power pin. Preliminary Ver 0.12 Page 9/26 2008/01/24 ST8024T 7.2.2 Relationship between the display data and LCD drive output Pins (Segment Mode) (a) 4-bit Parallel Input Mode DATA NUMBER OF CLOCKS MD L/R EIO1 EI02 INPUT 60 CLOCK 59 CLOCK 58 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK DI0 Y1 Y5 Y9 … Y229 Y233 Y237 Dl1 Y2 Y6 Y10 … Y230 Y234 Y238 H L Output Input DI2 Y3 Y7 Y11 … Y231 Y235 Y239 DI3 Y4 Y8 Y12 … Y232 Y236 Y240 DI0 Y240 Y236 Y232 … Y12 Y8 Y4 Dl1 Y239 Y235 Y231 … Y11 Y7 Y3 H H Input Output DI2 Y238 Y234 Y230 … Y10 Y6 Y2 DI3 Y237 Y233 Y229 … Y9 Y5 Y1 (b) 8-bit Parallel Input Mode DATA NUMBER OF CLOCKS MD L/R EIO1 EI02 INPUT 30 CLOCK 29 CLOCK 28 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK DI0 Y1 Y9 Y17 … Y217 Y225 Y233 Dl1 Y2 Y10 Y18 … Y218 Y226 Y234 DI2 Y3 Y11 Y19 … Y219 Y227 Y235 DI3 Y4 Y12 Y20 … Y220 Y228 Y236 L L Output Input DI4 Y5 Y13 Y21 Y221 Y229 Y237 DI5 Y6 Y14 Y22 Y222 Y230 Y238 DI6 Y7 Y15 Y23 Y223 Y231 Y239 Y8 Y16 Y24 Y224 Y232 Y240 DI7 DI0 Y240 Y232 Y224 … Y24 Y16 Y8 Dl1 Y239 Y231 Y223 … Y23 Y15 Y7 DI2 Y238 Y230 Y222 … Y22 Y14 Y6 DI3 Y237 Y229 Y221 … Y21 Y13 Y5 L H Input Output DI4 Y236 Y228 Y220 … Y20 Y12 Y4 Dl5 Y235 Y227 Y219 … Y19 Y11 Y3 DI6 Y234 Y226 Y218 … Y18 Y10 Y2 Y233 Y225 Y217 … Y17 Y9 Y1 DI7 (Common Mode) MD L (Single) H (Dual) L/R L H L H DATA TRANSFER DIRECTION Y240 Y1 Y240 Y1 Y240 Y121 Y1 Y120 Y1 Y120 Y240 Y121 EIO1 Output Input EI02 Input Output DI7 X X Output Input Input Input Output Input NOTES: L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. Preliminary Ver 0.12 Page 10/26 2008/01/24 ST8024T 7.2.3 (a) Connection examples of plural segment drivers When L/R = “L” Top data Last data Data flow Y1 Y240 EIO2 Y240 EIO1 Y1 EIO2 EIO1 L/R Y240 Y1 EIO2 EIO1 L/R L/R DI7-DI0 FR MD LP XCK DI7-DI0 FR MD LP XCK DI7-DI0 FR MD LP XCK XCK LP MD FR DI7-DI0 8 LGND (b) When L/R = “H” VDD XCK LP MD FR DI7-DI0 8 DI7-DI0 FR MD LP EIO2 EIO1 EIO2 EIO1 EIO2 Y1 Y240 Y1 Y240 Y1 Y240 L/R XCK DI7-DI0 FR MD XCK LP DI7-DI0 FR MD LP XCK EIO1 L/R LGND L/R Data flow Last data Top data Preliminary Ver 0.12 Page 11/26 2008/01/24 ST8024T 7.2.4 Timing chart of 4-device cascade connection of segment drivers FR LP XCK TOP DATA DI7 - DI 0 n* 1 2 LAST DATA n* device A 1 2 n* device B 1 2 n* device C 1 2 n* 1 2 device D EI (device A) EO (device A) EO (device B) EO (device C) *n = 60 in 4-bit parallel input mode *n = 30 in 8-bit parallel input mode Preliminary Ver 0.12 Page 12/26 2008/01/24 ST8024T 7.2.5 (a) Connection examples for plural common drivers Single Mode (L/R = ”L”) Last First Y240 Y1 Y240 Y1 Y240 Y1 EIO2 EIO1 EIO2 EIO1 EIO2 EIO1 FLM FR L/R /DISPOFF DI7 MD LP FR L/R /DISPOFF DI7 MD LP FR /DISPOFF L/R DI7 MD LP LP LGND(VDD ) LGND /DISPOFF FR (b) Single Mode (L/R = “H”) FR /DISPOFF V DD LGND LGND (V DD) LP LP DI7 L/R Y1 EIO2 Y240 Last First Preliminary Ver 0.12 EIO1 MD Y240 FR EIO2 /DISPOFF DI7 LP Y1 L/R EIO1 MD Y240 FR EIO2 /DISPOFF DI7 LP MD Y1 L/R FR EIO1 /DISPOFF FLM Page 13/26 2008/01/24 ST8024T (c) Dual Mode (L/R = “L”) Last 1 First Y240 Y1 EIO2 EIO1 FLM1 Last 2 First 2 Y240 Y121 Y120 Y1 EIO2 EIO1 Y240 Y1 EIO2 EIO1 FR L/R /DISPOFF MD LP DI7 FR L/R /DISPOFF MD LP DI7 FR L/R /DISPOFF MD LP DI7 LP FLM2 LGND (VDD) VDD LGND /DISPOFF FR (d) Dual mode (L/R = “H”) FR /DISPOFF VDD LGND LGND (VDD) FLM2 LP LP MD Page 14/26 Y1 DI7 Last 1 First 2 EIO1 L/R Y1 Y120 Y121 Y240 FR EIO2 /DISPOFF EIO1 LP MD DI7 L/R Y240 FR EIO2 /DISPOFF Preliminary Ver 0.12 LP First 1 MD Y1 DI7 EIO1 L/R FR /DISPOFF FLM1 EIO2 Y240 Last 2 2008/01/24 ST8024T 8. PRECAUTIONS Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows, When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power It is advisable to connect the serial resistor (50 to 100 ) or fuse to the LCD drive power V0 of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display grade. And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level LGND on /DISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here VDD VDD LGND VDD /DISPOFF LGND V0 V0 GND . Preliminary Ver 0.12 Page 15/26 2008/01/24 ST8024T 9. ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage (1) Supply voltage (2) Input voltage SYMBOL VDD V0 V12 V43 VSS VI APPLICABLE PINS VDD V0L, V0R V12L, V12R V43L, V43R VSS DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, /DISPOFF RATING -0.3 to +7.0 -0.3 to +33.0 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 UNIT V V V V V -0.3 to VDD + 0.3 V NOTE 1,2 Storage temperature TSTG -45 to +125 °C NOTES: 1. TA = +25 °C 2. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V). 10. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE Supply voltage (1) VDD VDD +2.5 +5.5 V 1, 2 Supply voltage (2) V0 V0L, V0R +15.0 +30.0 V °C Operating temperature TOPR -25 +70 NOTES: 1. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V). 2. Ensure that voltages are set such that VSS < V43 < Vl2 < V0. Preliminary Ver 0.12 Page 16/26 2008/01/24 ST8024T 11. ELECTRICAL CHARACTERISTICS 11.1 DC Characteristics (Segment Mode) (LGND=VSS =GND = 0V, VDD = +2.5 ~ +5.5 V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70°C) PARAMETER SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE Input "Low" voltage VIL DI7-DI0, XCK, LP, L/R, 0.2VDD V FR, MD, S/C, EIO1, Input "High" voltage VIH V 0.8VDD EIO2, /DISPOFF Output "Low" voltage VOL IOL = +0.4 mA +0.4 V EIO1, EIO2 Output "High" voltage VOH IOH = -0.4 mA VDD-0.4 V ILIL VI = LGND DI7-DI0, XCK, LP, L/R, -10.0 µA Input leakage current FR, MD, S/C, EIO1, VI = VDD +10.0 µA ILIH EIO2, /DISPOFF | VON| V0=30V 1.5 2.0 Output resistance RON Y1-Y240 k =0.5V V0=20V 2.0 2.5 µA Standby current ISTB LGND+GND+VSS 75.0 1 Supply current (1) VDD 2.0 mA 2 IDD1 (Non-selection) Supply current (2) VDD 12.0 mA 3 IDD2 (Selection) Supply current (3) I0 V0L, V0R 1.5 mA 4 NOTES: 1. VDD = +5.0 V, V0 = +30.0 V, Vi = LGND. 2. VDD = +5.0 V, V0 = +30.0 V, fXCK = 15 MHz, no-load, El = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +5.0 V, V0 = +30.0 V, fXCK = 15 MHz, no-load, El = LGND. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +5.0 V, V0 = +30.0 V, fXCK = 15MHz, fLP = 20.8 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (4-bit parallel input mode). (Common Mode) (LGND=VSS =GND = 0V, VDD = +2.5 ~ +5.5V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70 °C) PARAMETER SYMBOL CONDITIONS APPLICABL E PINS MIN. TYP. MAX. UNIT NOTE Input "Low" voltage VIL DI7-DI0, XCK, LP, L/R 0.2VDD V FR, MD, S/C, EIO1, VIH Input "High" voltage V 0.8VDD EIO2, /DISPOFF Output "Low" voltage VOL IOL = +0.4 mA +0.4 V EIO1, EIO2 Output "High" voltage VOH IOH = -0.4 mA VDD-0.4 V DI7-DI0, XCK, LP, L/R -10.0 µA ILIL VI = LGND FR, MD, S/C, EIO1, Input leakage current EIO2, /DISPOFF DI6-DI0, LP, L/R, FR, ILIH VI = VDD +10.0 µA MD, S/C, /DISPOFF Input pull-down IPD DI7, XCK, EIO1, EIO2 VI = VDD 100.0 µA current | VON| V0=30V 1.5 2.0 Output resistance RON Y1-Y240 k =0.5V V0=20V 2.0 2.5 µA Standby current ISPD LGND+GND+VSS 75.0 1 Supply current (1) IDD VDD 120.0 µA 2 Supply current (2) I0 V0L, V0R 240.0 µA 2 NOTES: 1. VDD = +5.0 V, V0 = +30.0 V, VI = LGND 2. VDD = +5.0 V, V0 = +30.0 V, fLP = 20.8 kHz, fFR = 80 Hz, 1/480 duty operation, no-load. Preliminary Ver 0.12 Page 17/26 2008/01/24 ST8024T 11.2 AC Characteristics (Segment Mode 1) (LGND=VSS = GND = 0 V, VDD = +5.0±0.5 V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70 °C) TYP. MAX. UNIT NOTE PARAMETER SYMBOL CONDITIONS MIN Shift clock period tWCK tR,tF 10ns 66 ns 1 Shift clock "H" pulse width tWCKH 23 ns Shift clock "L" pulse width tWCKL 23 ns Data setup time tDS 15 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 50 ns Latch pulse rise to shift clock rise time tLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 /DISPOFF removal time tSD 100 ns /DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tD CL = 15 pF 41 ns Output delay time (2) tPD1, tPD2 CL = 15 pF 1.2 µs Output delay time (3) tPD3 CL = 15 pF 1.2 µs NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. (Segment Mode 2) (LGND=VSS =GND = 0V, VDD = +3.0 ~ +4.5V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70 °C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Shift clock period tWCK tR,tF 10ns 82 ns 1 Shift clock "H" pulse width tWCKH 28 ns Shift clock "L” pulse width tWCKL 28 ns Data setup time tDS 20 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 65 ns Latch pulse rise to shift clock rise time tLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 /DISPOFF removal time tSD 100 ns /DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tD CL = 15 pF 57 ns Output delay time (2) tPD1, tPD2 CL = 15 pF 1.2 µs Output delay time (3) tPD3 CL = 15 pF 1.2 µs NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. Preliminary Ver 0.12 Page 18/26 2008/01/24 ST8024T (Segment Mode 3) (LGND=VSS =GND = 0V, VDD = +2.5 ~ +3.0V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to+70 °C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Shift clock period tWCK tR,tF 10ns 130 ns 1 Shift clock "H" pulse width tWCKH 35 ns Shift clock "L” pulse width tWCKL 35 ns Data setup time tDS 25 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 80 ns Latch pulse rise to shift clock rise time tLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 /DISPOFF removal time tSD 100 ns /DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tD CL = 15 pF 80 ns Output delay time (2) tPD1, tPD2 CL = 15 pF 1.2 µs Output delay time (3) tPD3 CL = 15 pF 1.2 µs NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. (Common Mode) (LGND=VSS = 0 V, VDD = +2.5 ~ +5.5V, V0 = +15.0 ~ +30.0V, TOPR = -25 to +70° C) TYP. MAX. UNIT PARAMETER SYMBOL CONDITIONS MIN. Shift clock period tWLP tR,tF 20ns 250 ns VDD = +5.0± 0.5V 15 ns Shift clock "H" pulse width tWLPH VDD = +2.5+ 4.5V 30 ns Data setup time tSU 30 ns Data hold time tH 50 ns Input signal rise time tR 50 ns Input signal fall time tF 50 ns /DISPOFF removal time tSD 100 ns /DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tDL CL = 15 pF 200 ns Output delay time (2) tPD1, t PD2 CL = 15 pF 1.2 µs Output delay time (3) t PD3 CL = 15 pF 1.2 µs Preliminary Ver 0.12 Page 19/26 2008/01/24 ST8024T 11.3 Timing Chart of Segment Mode tWLPH LP tLD tSL tLH tLS tWCKH tWCKL XCK tR tF tWCK tDS LAST DATA DI7 - DI0 tWDL tDH TOP DATA tSD /DISPOFF LP XCK 1 n* 2 tS EI tD EO *n = 60 in 4-bit parallel input mode *n = 30 in 8-bit parallel input mode FR tPD1 LP tPD2 /DISPOFF tPD3 Y1 - Y240 Fig. 8 Timing Characteristics (3) Preliminary Ver 0.12 Page 20/26 2008/01/24 ST8024T 11.4 Timing Chart of Common Mode tWLP LP tR tWLPH t SU tF tH EIO2 t DL EIO1 tWDL tSD /DISPOFF FR tPD1 LP tPD2 /DISPOFF tPD3 Y1 - Y240 Preliminary Ver 0.12 Page 21/26 2008/01/24 ST8024T 12. APPLICATION CIRCUIT 12.1 Application Circuit for Module Preliminary Ver 0.12 Page 22/26 2008/01/24 ST8024T 13. PAD DIAGRAM Unit : um Pad# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name V0L V0L V0L V0L V12L V12L V34L V34L VSS VSS GND GND DUMMY LGND LGND VDD VDD S/C EIO2 DUMMY DI0 DI1 DI2 DI3 DI4 DI5 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY X -6437.25 -6437.25 -6437.25 -6437.25 -6437.25 -6437.25 -6437.25 -6437.25 -6437.25 -6437.25 -6268.15 -6136.55 -5978.15 -5680.50 -5573.05 -5452.80 -5345.35 -5208.40 -4786.70 -4412.48 -4005.45 -3621.55 -3317.00 -3005.05 -2840.45 -2679.15 -2515.05 -2350.10 -2185.15 -2020.20 -1855.25 -1690.30 Preliminary Ver 0.12 Y Pad# Name X 266.85 33 DUMMY -1525.35 207.55 34 DUMMY -1360.40 148.25 35 DUMMY -1195.45 88.95 36 DUMMY -874.05 29.65 37 DUMMY -527.80 -29.65 38 DUMMY -161.08 -88.95 39 DUMMY 228.83 -148.25 40 DUMMY 614.43 -207.55 41 DUMMY 878.05 -266.85 42 DUMMY 1297.05 -263.15 43 DUMMY 1474.50 -263.15 44 DUMMY 1651.95 -209.05 45 DUMMY 1829.40 -263.15 46 DUMMY 2006.85 -263.15 47 DUMMY 2184.30 -263.15 48 DUMMY 2361.75 -263.15 49 DUMMY 2539.20 -263.10 50 DI6 2731.90 -263.10 51 DI7 2893.20 -263.10 52 XCK 3214.45 -263.10 53 /DISPOFF 3505.05 -263.10 54 DUMMY 3709.58 -263.10 55 LP 4122.15 -263.10 56 EIO1 4450.75 -263.10 57 FR 4806.65 -263.10 58 L/R 5094.20 -263.10 59 MD 5349.25 -263.10 60 LGND 5573.05 -263.10 61 LGND 5680.50 -263.10 62 DUMMY 5978.15 -263.10 63 GND 6136.55 -263.10 64 GND 6268.15 Page 23/26 Y Pad# -263.10 65 -263.10 66 -263.10 67 -263.10 68 -224.40 69 -227.68 70 -217.73 71 -217.73 72 -220.48 73 -263.10 74 -263.10 75 -263.10 76 -263.10 77 -263.10 78 -263.10 79 -263.10 80 -263.10 81 -263.10 82 -263.10 83 -263.10 84 -263.10 85 -263.10 86 -263.10 87 -263.10 88 -263.10 89 -263.10 90 -263.10 91 -263.15 92 -263.15 93 -209.05 94 -263.15 95 -263.15 96 Name VSS VSS V34R V34R V12R V12R V0R V0R V0R V0R DUMMY Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 X 6437.25 6437.25 6437.25 6437.25 6437.25 6437.25 6437.25 6437.25 6437.25 6437.25 6317.00 6267.00 6215.00 6163.00 6111.00 6059.00 6007.00 5955.00 5903.00 5851.00 5799.00 5747.00 5695.00 5643.00 5591.00 5539.00 5487.00 5435.00 5383.00 5331.00 5279.00 5227.00 Y -266.85 -207.55 -148.25 -88.95 -29.65 29.65 88.95 148.25 207.55 266.85 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 2008/01/24 ST8024T 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 250 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y174 5175.00 5123.00 5071.00 5019.00 4967.00 4915.00 4863.00 4811.00 4759.00 4707.00 4655.00 4603.00 4551.00 4499.00 4447.00 4395.00 4343.00 4291.00 4239.00 4187.00 4135.00 4083.00 4031.00 3979.00 3927.00 3875.00 3823.00 3771.00 3719.00 3667.00 3615.00 3563.00 3511.00 3459.00 3407.00 3355.00 3303.00 3251.00 3199.00 3147.00 3095.00 3043.00 2991.00 2939.00 2887.00 2835.00 2783.00 2731.00 2679.00 2627.00 2575.00 -2835.00 Preliminary Ver 0.12 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 273 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 DUMMY Y121 Y122 Y197 2523.00 2471.00 2419.00 2367.00 2315.00 2263.00 2211.00 2159.00 2107.00 2055.00 2003.00 1951.00 1899.00 1847.00 1795.00 1743.00 1691.00 1639.00 1587.00 1535.00 1483.00 1431.00 1379.00 1327.00 1275.00 1223.00 1171.00 1119.00 1067.00 1015.00 963.00 911.00 859.00 807.00 755.00 703.00 651.00 599.00 547.00 495.00 443.00 391.00 339.00 287.00 235.00 183.00 131.00 79.00 0.00 -79.00 -131.00 -4031.00 Page 24/26 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 296 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 Y161 Y162 Y163 Y164 Y165 Y166 Y167 Y168 Y169 Y170 Y171 Y172 Y173 Y220 -183.00 -235.00 -287.00 -339.00 -391.00 -443.00 -495.00 -547.00 -599.00 -651.00 -703.00 -755.00 -807.00 -859.00 -911.00 -963.00 -1015.00 -1067.00 -1119.00 -1171.00 -1223.00 -1275.00 -1327.00 -1379.00 -1431.00 -1483.00 -1535.00 -1587.00 -1639.00 -1691.00 -1743.00 -1795.00 -1847.00 -1899.00 -1951.00 -2003.00 -2055.00 -2107.00 -2159.00 -2211.00 -2263.00 -2315.00 -2367.00 -2419.00 -2471.00 -2523.00 -2575.00 -2627.00 -2679.00 -2731.00 -2783.00 -5227.00 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 2008/01/24 ST8024T 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 13.1 Y175 Y176 Y177 Y178 Y179 Y180 Y181 Y182 Y183 Y184 Y185 Y186 Y187 Y188 Y189 Y190 Y191 Y192 Y193 Y194 Y195 Y196 -2887.00 -2939.00 -2991.00 -3043.00 -3095.00 -3147.00 -3199.00 -3251.00 -3303.00 -3355.00 -3407.00 -3459.00 -3511.00 -3563.00 -3615.00 -3667.00 -3719.00 -3771.00 -3823.00 -3875.00 -3927.00 -3979.00 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 Y198 Y199 Y200 Y201 Y202 Y203 Y204 Y205 Y206 Y207 Y208 Y209 Y210 Y211 Y212 Y213 Y214 Y215 Y216 Y217 Y218 Y219 -4083.00 -4135.00 -4187.00 -4239.00 -4291.00 -4343.00 -4395.00 -4447.00 -4499.00 -4551.00 -4603.00 -4655.00 -4707.00 -4759.00 -4811.00 -4863.00 -4915.00 -4967.00 -5019.00 -5071.00 -5123.00 -5175.00 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 Y221 Y222 Y223 Y224 Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240 DUMMY -5279.00 -5331.00 -5383.00 -5435.00 -5487.00 -5539.00 -5591.00 -5643.00 -5695.00 -5747.00 -5799.00 -5851.00 -5903.00 -5955.00 -6007.00 -6059.00 -6111.00 -6163.00 -6215.00 -6267.00 -6317.00 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 250.10 Gold Bump Size Pad No. X 1~10, 65~74 87.50 11, 12 , 63, 64 116.60 13, 62 160.20 14~17, 60, 61 92.50 18, 19, 21~26, 50~53, 55~59 131.30 20, 54 152.35 27~36 134.30 37 94.30 38 103.85 39, 40 85.65 41 117.20 42~49 140.80 196 91.00 75, 317 33.00 76~195, 197~316 37.00 Wafer thickness = 480±20um, Bump pad height = 15um, strength=30g Preliminary Ver 0.12 Page 25/26 2 Y 44.30 42.30 33.30 42.30 42.40 42.40 42.40 44.40 37.85 57.75 52.25 42.40 81.00 81.00 81.00 Area (um ) 3876.2500 4932.1800 5334.6600 3912.7500 5567.1200 6459.6400 5694.3200 4186.9200 3930.7225 4946.2875 6123.7000 5969.9200 7371.0000 2673.0000 2997.0000 2008/01/24 ST8024T 14. REVISION REVISION DESCRIPTION PAGE DATE 0.10 First release Change Max. operating voltage to +30V Change Standby Current Application Pin to LGND+GND+VSS Change operating temperature to 70°C 1-26 2006/12/11 1-26 2007/04/20 16-19 2008/01/24 0.11 0.12 The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. Preliminary Ver 0.12 Page 26/26 2008/01/24