SITRONIX ST8024

ST8024
COM/SEG LCD Driver
Datasheet
Version 2.1
2009/08/19
Note: Sitronix Technology Corp. reserves
the right to change the contents in this
document without prior notice. This is not
a final specification. Some parameters
are subject to change.
ST8024
1
FEATURES
Number of LCD drive outputs: 240
Supply voltage for LCD drive: +15.0 to +30.0 V
Supply voltage for the logic system: +2.5 to +5.5 V
Low power consumption
Low output impedance
(Segment mode)
Shift clock frequency
20MHz(MAX.): VDD = +5.0 ± 0.5V
15MHz(MAX.): VDD = +3.0 to + 4.5V
12MHz(MAX.): VDD = +2.5 to + 3.0V
Adopts a data bus system
4-bit/8-bit parallel input modes are
selectable with a mode (MD) pin
Automatic transfer function of an
enable signal
Automatic counting function which, in
the chip selection mode, causes the
internal clock to be stopped by
automatically counting 240 bits of
input data
Line latch circuits are reset when
/DISPOFF active
2
(Common mode)
Shift clock frequency: 4 MHz (MAX.)
Built-in 240-bit bi-directional shift
register (divisible into 120 bits x 2)
Available in a single mode (240-bit
shift register) or in a dual mode
(120-bit shift register x 2)
Y1->Y240 Single mode
Y240->Y1 Single mode
Y1->Yl20, Y121->Y240 Dual mode
Y240->Y121, Yl20->Y1 Dual mode
The above 4 shift directions are
pin-selectable
Shift register circuits are reset when
/DISPOFF active
DESCRIPTION
The ST8024 is a 240-output segment/common driver IC suitable for driving large/medium scale
dot matrix LCD panels, and is used in personal computers/work stations. The ST8024 is good
both as a segment driver and a common driver, and it can create a low power consuming,
high-resolution LCD.
Ver 2.1
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ST8024
3
BLOCK DIAGRAM
V0R
FR
/DISPOFF
V12R
V43R
VSS
Y1
Y2
Y239
Y240
VSS
LEVEL
SHIFTER
240-BIT 4-LEVEL DRIVER
V43L
240
EIO1
EIO2
V12L
240-BIT LEVEL SHIFTER
ACTIVE
CONTROL
V0L
240
240-BIT LINE LATCH/SHIFT REGISTER
16
LP
XCK
16
16
8 BIT
DATA
LATCH
CONTROL
LOGIC
8
DATA CONTROL
L/R
MD
SP CONVERSION & DATA CONTROL
(4 to 8 or 8 to 8)
S/C
DI0
4
DI1
DI2
DI3
DI4
DI5
DI6
DI7
VDD
V SS
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
In case of segment mode, controls the selection or non-selection of the chip. Following
an LP signal input, and after the chip selection signal is input, a selection signal is
generated internally until 240 bits of data have been read in. Once data input has been
Active Control
completed, a selection signal for cascade connection is output, and the chip is
non-selected. In case of common mode, controls the input/output data of bi-directional
pins.
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel
SP Conversion
input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel
& Data Control
input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time.
In case of segment mode, selects the state of the data latch which reads in the data bus
Data Latch Control signals. The shift direction is controlled by the control logic. For every 16 bits of data
read in, the selection signal shifts one bit based on the state of the control circuit.
In case of segment mode, latches the data on the data bus. The latch state of each LCD
Data Latch
drive output pin is controlled by the control logic and the data latch control; 240 bits of
data are read in 30 sets of 8 bits.
In case of segment mode, all 240 bits which have been read into the data latch are
Line Latch/
simultaneously latched at the falling edge of the LP signal, and are output to the level
shifter block. In case of common mode, shifts data from the data input pin at the falling
Shift Register
edge of the LP signal.
Level Shifter
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to
the driver block.
Drives the LCD drive output pins from the line latch/shift register data, and selects one of
4-Level Driver
4 levels (V0, V12, V43 or Vss) based on the S/C, FR and /DISPOFF signals.
Controls the operation of each block. In case of segment mode, when an LP signal has
been input, all blocks are reset and the control logic waits for the selection signal output
Control Logic
from the active control block. Once the selection signal has been output, operation of the
data latch and data transmission is controlled, 240 bits of data are read in, and the chip
is non-selected. In case of common mode, controls the direction of data shift.
Ver 2.1
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ST8024
5
PIN DESCRIPTION (TCP TYPE)
SYMBOL
Y1-Y240
V0L, V0R
V12L, V12R
V43L, V43R
L/R
VDD
S/C
DESCRIPTION
LCD drive output
Power supply for LCD drive
Power supply for LCD drive
Power supply for LCD drive
Display data shift direction selection
Power supply for logic system (+2.5 to +5.5 V)
Segment mode/common mode selection
Input/output for chip selection at segment mode
EIO2, EIO1
I/O
Shift data input/output for shift register at common mode
DI0-DI6
I Display data input at segment mode
DI7
I Display data input at segment mode/Dual mode data input at common mode
XCK
I Clock input for taking display data at segment mode
/DISPOFF
I Control input for output of non-select level
I Latch pulse input for display data at segment mode/
LP
Shift clock input for shift register at common mode
FR
I AC-converting signal input for LCD drive waveform
MD
I 4 or 8 bits mode selection input
VSS
P Ground (0 V)
TEST1
I Connect to GND or floating
PS : Detail size see TCP drawing data
Ver 2.1
I/O
O
P
P
P
I
P
I
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ST8024
6
INPUT/OUTPUT CIRCUITS
V DD
I
To Internal Circuit
Applicable Pins
L/R , S/C , DI6~DI0 ,
/DISPOFF , LP , FR , MD
GND (0V)
Figure 6-1
Input Circuit (1)
V DD
I
To Internal Circuit
Applicable Pins
DI7 , XCK
Control Signal
GND (0V)
GND (0V)
Figure 6-2
Ver 2.1
Input Circuit (2)
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2009/08/19
ST8024
V DD
To Internal
Circuit
I/O
Control Signal
GND (0V)
GND (0V)
VDD
Output Signal
Application Pins
EIO1 , EIO2
Control Signal
GND (0V)
Figure 6-3
Input/Output Circuit
V0
V12
V0
Control Signal 1
Control Signal 2
Control Signal 3
Control Signal 4
O
GND (0V)
V43
Figure 6-4
Ver 2.1
GND (0V)
Application Pins
Y1~Y160
VSS
LCD Drive Output Circuit
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ST8024
7
FUNCTIONAL DESCRIPTION
7.1
Pin Functions
(Segment mode)
SYMBOL
VDD
VSS
V0L, V0R
V12L, V12R
V43L, V43R
DI7-DI0
XCK
LP
L/R
/DISPOFF
FR
MD
S/C
ElO1, EIO2
Ver 2.1
FUNCTION
Logic system power supply pin,
Connected to +2.5 to +5.5 V.
Ground pin, connected to 0 V.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that VSS < V43 < V12 < V0.
ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin
Input pins for display data
In 4-bit parallel mode, DI3-DI0 are the display data input pins, and DI7-DI4 must be
connected to LGND or VDD.
In 8-bit parallel mode, All DI7-Dl0 pins are the display data input pins.
Refer to section 7.2.2.
Clock input pin for taking display data
Data is read at the falling edge of the clock pulse.
Latch pulse input pin for display data
Data is latched at the falling edge of the clock pulse.
Input pin for selecting the reading direction of display data
When set to LGND level "L", data is read sequentially from Y240 to Y1.
When set to VDD level "H", data is read sequentially from Y1 to Y240.
Refer to section 7.2.2.
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level Vss.
When set to "L", the contents of the line latch are reset, but the display data are read in
the data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is
canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of
the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time
does not correspond to what is shown in AC characteristics, it can not output the
reading data correctly.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the line latch output
signal and the FR signal.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
When set to LGND level "L", 8-bit parallel input mode is set.
When set to VDD level "H", 4-bit parallel input mode is set.
Refer to section 7.2.2.
Segment mode/common mode selection pin
When set to VDD level "H", segment mode is set.
Input/output pins for chip selection
When L/R input is at LGND level "L", ElO1 is set for output, and EIO2 is set for input.
When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output.
During output, set to "H" while LP • XCK is "H" and after 240 bits of data have been
read, set to "L” for one cycle (from falling edge to failing edge of XCK), after which it
returns to "H".
During input, the chip is selected while El is set to "L" after the LP signal is input. The
chip is non-selected after 240 bits of data have been read.
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ST8024
Y1 -Y240
(Common mode)
SYMBOL
VDD
VSS
V0L, V0R
V12L, V12R
V43L, V43R
ElO1
EIO2
LP
L/R
/DISPOFF
FR
MD
DI7
S/C
Ver 2.1
LCD drive output pins
Corresponding directly to each bit of the data latch, one level (V0, V12, V43, or VSS) is
selected and output.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
FUNCTION
Logic system power supply pin, connected to +2.5 to +5.5 V.
Ground pin, connected to 0 V.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider.
Ensure that voltages are set such that VSS < V43 < V12 < V0.
ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin.
Shift data input/output pin for bi-directional shift register
Output pin when L/R is at LGND level "L', input pin when L/R is at VDD level "H".
When L/R = H, ElO1 is used as input pin, it will be pulled down.
When L/R = L, ElO1 is used as output pin, it won't be pulled down.
Refer to section 7.2.2.
Shift data input/output pin for bi-directional shift register
Input pin when L/R is at LGND level "L", output pin when L/R is at VDD level "H".
When L/R = L, EIO2 is used as input pin, it will be pulled down.
When L/R = H, EIO2 is used as output pin, it won't be pulled down.
Refer to section 7.2.2.
Shift clock pulse input pin for bi-directional shift register
Data is shifted at the falling edge of the clock pulse.
Input pin for selecting the shift direction of bi-directional shift register
Data is shifted from Y240 to Y1 when set to LGND level "L", and data is shifted from Y1 to
Y240 when set to VDD level "H".
Refer to section 7.2.2.
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level LGND.
When set to "L”, the contents of the shift register are reset to not reading data. When
the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and
the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF
removal time does not correspond to what is shown in AC characteristics, the shift data
is not read correctly.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the shift register
output signal and the FR signal.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
When set to LGND level "L", single mode operation is selected; when set to VDD level
"H" dual mode operation is selected.
Refer to section 7.2.2.
Dual mode data input pin
According to the data shift direction of the data shift register, data can be input starting
from the 121st bit.
When the chip is used in dual mode, DI7 will be pulled down.
When the chip is used in single mode, DI7 won't be pulled down.
Refer to section 7.2.2.
Segment mode/common mode selection pin
When set to LGND level "L", common mode is set.
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ST8024
DI6-DI0
XCK
Y1 -Y240
7.2
7.2.1
Not used
Connect DI6-DI0 to LGND or VDD, avoiding floating.
Not used
XCK is pulled down in common mode, so connect to LGND or open.
LCD drive output pins
Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS) is
selected and output.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Functional Operations
Truth table
(Segment Mode)
FR
LATCH DATA
L
L
L
H
H
L
H
H
X
X
/DISPOFF
H
H
H
H
L
LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240)
V43
VSS
V12
V0
VSS
(Common Mode)
FR
LATCH DATA
/DISPOFF
LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240)
L
L
H
V43
L
H
H
V0
H
L
H
V12
H
H
H
VSS
X
X
L
VSS
NOTES:
VSS < V43 < V12 < V0
L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care
"Don't care" should be fixed to "H" or "L", avoiding floating.
There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver.
Supply regular voltage which is assigned by specification for each power pin.
Ver 2.1
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ST8024
7.2.2
Relationship between the display data and LCD drive output Pins
(Segment Mode)
4-bit Parallel Input Mode
DATA
NUMBER OF CLOCKS
MD L/R EIO1
EI02
INPUT 60 CLOCK 59 CLOCK 58 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK
DI0
Y1
Y5
Y9
…
Y229
Y233
Y237
Dl1
Y2
Y6
Y10
…
Y230
Y234
Y238
H L Output Input
DI2
Y3
Y7
Y11
…
Y231
Y235
Y239
DI3
Y4
Y8
Y12
…
Y232
Y236
Y240
DI0
Y240
Y236
Y232
…
Y12
Y8
Y4
Dl1
Y239
Y235
Y231
…
Y11
Y7
Y3
H H Input Output
DI2
Y238
Y234
Y230
…
Y10
Y6
Y2
DI3
Y237
Y233
Y229
…
Y9
Y5
Y1
8-bit Parallel Input Mode
NUMBER OF CLOCKS
DATA
MD L/R EIO1
EI02
INPUT 30 CLOCK 29 CLOCK 28 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK
DI0
Y1
Y9
Y17
…
Y217
Y225
Y233
Dl1
Y2
Y10
Y18
…
Y218
Y226
Y234
DI2
Y3
Y11
Y19
…
Y219
Y227
Y235
DI3
Y4
Y12
Y20
…
Y220
Y228
Y236
L L Output Input
DI4
Y5
Y13
Y21
Y221
Y229
Y237
DI5
Y6
Y14
Y22
Y222
Y230
Y238
DI6
Y7
Y15
Y23
Y223
Y231
Y239
DI7
Y8
Y16
Y24
Y224
Y232
Y240
DI0
Y240
Y232
Y224
…
Y24
Y16
Y8
Dl1
Y239
Y231
Y223
…
Y23
Y15
Y7
DI2
Y238
Y230
Y222
…
Y22
Y14
Y6
DI3
Y237
Y229
Y221
…
Y21
Y13
Y5
L H Input Output
DI4
Y236
Y228
Y220
…
Y20
Y12
Y4
Dl5
Y235
Y227
Y219
…
Y19
Y11
Y3
DI6
Y234
Y226
Y218
…
Y18
Y10
Y2
DI7
Y233
Y225
Y217
…
Y17
Y9
Y1
(Common Mode)
MD
L
(Single)
H
(Dual)
L/R
L
H
L
H
DATA TRANSFER DIRECTION
Y240
Y1
Y1
Y240
Y240
Y121
Y120
Y1
Y1
Y120
Y240
Y121
EIO1
Output
Input
EI02
Input
Output
DI7
X
X
Output
Input
Input
Input
Output
Input
NOTES:
L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care
"Don't care" should be fixed to "H" or "L", avoiding floating.
Ver 2.1
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ST8024
7.2.3
(a)
Connection examples of plural segment drivers
When L/R = “L”
Top data
Last data
Data flow
Y1
Y240
EIO2
Y240
EIO1
Y1
EIO2
EIO1
L/R
Y240
Y1
EIO2
EIO1
L/R
L/R
DI7-DI0
FR
MD
LP
XCK
DI7-DI0
FR
MD
LP
XCK
DI7-DI0
FR
MD
LP
XCK
XCK
LP
MD
FR
DI7-DI0
8
LGND
(b)
When L/R = “H”
VDD
XCK
LP
MD
FR
DI7-DI0
8
DI7-DI0
FR
MD
LP
L/R
XCK
DI7-DI0
FR
MD
LP
XCK
DI7-DI0
FR
MD
LP
XCK
L/R
LGND
L/R
EIO1
EIO2
EIO1
EIO2
EIO1
EIO2
Y1
Y240
Y1
Y240
Y1
Y240
Data flow
Last data
Top data
Ver 2.1
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ST8024
7.2.4
Timing chart of 4-device cascade connection of segment drivers
FR
LP
XCK
TOP DATA
DI7 - DI 0
n*
1
2
LAST DATA
n*
device A
1
2
n*
device B
1
2
n*
device C
1
2
n*
1
2
device D
EI
(device A)
EO
(device A)
EO
(device B)
EO
(device C)
*n = 60 in 4-bit parallel input mode
*n = 30 in 8-bit parallel input mode
Ver 2.1
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2009/08/19
ST8024
7.2.5
(a)
Connection examples for plural common drivers
Single Mode (L/R = ”L”)
Last
First
FLM
Y240
Y1
Y240
Y1
Y240
Y1
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1
FR
L/R
/DISPOFF
DI7
MD
LP
FR
L/R
/DISPOFF
DI7
MD
LP
FR
/DISPOFF
L/R
DI7
MD
LP
LP
LGND(VDD )
LGND
/DISPOFF
FR
(b)
Single Mode (L/R = “H”)
FR
/DISPOFF
V DD
LGND
LGND (V DD)
LP
LP
DI7
L/R
Y1
EIO2
Y240
Last
First
Ver 2.1
EIO1
MD
Y240
FR
EIO2
/DISPOFF
LP
DI7
Y1
L/R
EIO1
MD
Y240
FR
EIO2
/DISPOFF
LP
DI7
MD
Y1
L/R
FR
EIO1
/DISPOFF
FLM
Page 13/28
2009/08/19
ST8024
(c)
Dual Mode (L/R = “L”)
Last 1
First
Y240
Y1
EIO2
EIO1
FLM1
First 2
Last 2
Y240 Y121 Y120 Y1
EIO2
EIO1
Y240
Y1
EIO2
EIO1
FR
L/R
/DISPOFF
MD
LP
DI7
FR
L/R
/DISPOFF
MD
LP
DI7
FR
L/R
/DISPOFF
MD
LP
DI7
LP
FLM2
LGND (VDD)
VDD
LGND
/DISPOFF
FR
(d)
Dual mode (L/R = “H”)
FR
/DISPOFF
VDD
LGND
LGND (VDD)
FLM2
LP
LP
MD
Page 14/28
Y1
DI7
Last 1 First 2
EIO1
L/R
Y1 Y120 Y121 Y240
FR
EIO2
/DISPOFF
EIO1
LP
MD
DI7
L/R
Y240
FR
EIO2
/DISPOFF
Ver 2.1
LP
First 1
MD
Y1
DI7
EIO1
L/R
FR
/DISPOFF
FLM1
EIO2
Y240
Last 2
2009/08/19
ST8024
8
PRECAUTIONS
Precautions when connecting or disconnecting the power supply
This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which
may flow if voltage is supplied to the LCD drive power supply while the logic system power supply
is floating. The details are as follows,
When connecting the power supply, connect the LCD drive power after connecting the logic
system power. Furthermore, when disconnecting the power, disconnect the logic system power
after disconnecting the LCD drive power
It is advisable to connect the serial resistor (50 to 100 ) or fuse to the LCD drive power V0 of
the system as a current limiter. Set up a suitable value of the resistor in consideration of the
display grade.
And when connecting the logic power supply, the logic condition of this IC inside is insecure.
Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on
/DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply
has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to
level LGND on /DISPOFF function. Then disconnect the logic system power after disconnecting
the LCD drive power.
When connecting the power supply, follow the recommended sequence shown here
VDD
VDD
LGND
VDD
/DISPOFF
LGND
V0
V0
GND
.
Ver 2.1
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ST8024
9
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply voltage (1)
Supply voltage (2)
Input voltage
SYMBOL
VDD
V0
V12
V43
VSS
VI
APPLICABLE PINS
VDD
V0L, V0R
V12L, V12R
V43L, V43R
VSS
DI7-DI0, XCK, LP, L/R, FR,
MD, S/C, EIO1, EIO2,
/DISPOFF
RATING
-0.3 to +7.0
-0.3 to +33.0
-0.3 to V0 + 0.3
-0.3 to V0 + 0.3
-0.3 to V0 + 0.3
UNIT
V
V
V
V
V
-0.3 to VDD + 0.3
V
NOTE
1,2
Storage temperature
TSTG
-45 to +125
°C
NOTES:
1. TA = +25 °C
2. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V).
3. Stress over the “Absolute Max. Ratings” conditions will damaged the device permanently.
10
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
APPLICABLE PINS
MIN.
TYP. MAX. UNIT NOTE
Supply voltage (1)
VDD
VDD
+2.5
+5.5
V
1, 2
Supply voltage (2)
V0
V0L, V0R
+15.0
+30.0
V
Operating temperature
TOPR
-25
+85
°C
NOTES:
1. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V).
2. Ensure that voltages are set such that VSS < V43 < Vl2 < V0.
Ver 2.1
Page 16/28
2009/08/19
ST8024
11
ELECTRICAL CHARACTERISTICS
11.1
DC Characteristics
(Segment Mode)
(LGND=VSS =GND = 0V, VDD = +2.5 ~ +5.5 V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +85°C)
PARAMETER
SYMBOL CONDITIONS APPLICABLE PINS
MIN. TYP. MAX. UNIT NOTE
DI
7
-DI
0
,
XCK,
LP,
L/R,
Input "Low" voltage
VIL
0.2VDD
V
FR, MD, S/C, EIO1,
0.8VDD
Input "High" voltage
VIH
VDD+0.7 V
EIO2, /DISPOFF
Output "Low" voltage
VOL
IOL = +0.4 mA
+0.4
V
EIO1, EIO2
Output "High" voltage
VOH
IOH = -0.4 mA
VDD-0.4
V
DI7-DI0, XCK, LP, L/R,
µA
ILIL
VI = LGND
-10.0
Input leakage current
FR, MD, S/C, EIO1,
µA
+10.0
ILIH
VI = VDD
EIO2, /DISPOFF
| VON| V0=30V
1.5
2.0
Output resistance
RON
Y1-Y240
k
=0.5V V0=20V
2.0
2.5
µA
Standby current
ISTB
LGND
75.0
1
Supply current (1)
VDD
2.0
mA
2
IDD1
(Non-selection)
Supply current (2)
VDD
12.0
mA
3
IDD2
(Selection)
Supply current (3)
I0
V0L, V0R
1.5
mA
4
NOTES:
1. VDD = +5.0 V, V0 = +30.0 V, Vi = LGND.
2. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20 MHz, no-load, El = VDD. The input data is turned over by data taking
clock (4-bit parallel input mode).
3. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20 MHz, no-load, El = LGND. The input data is turned over by data
taking clock (4-bit parallel input mode).
4. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20 MHz, fLP = 41.6 kHz, fFR = 80 Hz, no-load. The input data is turned
over by data taking clock (4-bit parallel input mode).
(Common Mode)
(LGND=VSS =GND = 0V, VDD = +2.5 ~ +5.5V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +85 °C)
PARAMETER
SYMBOL CONDITIONS APPLICABL E PINS MIN. TYP. MAX. UNIT NOTE
DI7-DI0, XCK, LP, L/R
Input "Low" voltage
VIL
0.2VDD
V
FR, MD, S/C, EIO1,
V
IH
0.8VDD
Input "High" voltage
VDD+0.7 V
EIO2, /DISPOFF
Output "Low" voltage
VOL
IOL = +0.4 mA
+0.4
V
EIO1, EIO2
Output "High" voltage
VOH
IOH = -0.4 mA
VDD-0.4
V
DI7-DI0, XCK, LP, L/R
µA
-10.0
ILIL
VI = LGND
FR, MD, S/C, EIO1,
Input leakage current
EIO2, /DISPOFF
DI6-DI0, LP, L/R, FR,
µA
ILIH
VI = VDD
+10.0
MD, S/C, /DISPOFF
Input pull-down
µA
VI = VDD
DI7, XCK, EIO1, EIO2
100.0
IPD
current
| VON| V0=30V
1.5
2.0
Output resistance
RON
Y1-Y240
k
=0.5V V0=20V
2.0
2.5
µA
Standby current
ISPD
LGND
75.0
1
µA
Supply current (1)
IDD
VDD
120.0
2
µA
Supply current (2)
I0
V0L, V0R
240.0
2
NOTES:
1. VDD = +5.0 V, V0 = +30.0 V, VI = LGND
2. VDD = +5.0 V, V0 = +30.0 V, fLP = 41.6 kHz, fFR = 80 Hz, 1/480 duty operation, no-load.
Ver 2.1
Page 17/28
2009/08/19
ST8024
11.2
AC Characteristics
(Segment Mode 1) (LGND=VSS = GND = 0 V, VDD = +5.0±0.5 V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +85 °C)
PARAMETER
SYMBOL CONDITIONS MIN
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF 10ns
50
ns
1
tWCKH
ns
Shift clock "H" pulse width
15
Shift clock "L" pulse width
tWCKL
15
ns
Data setup time
tDS
10
ns
Data hold time
tDH
12
ns
Latch pulse "H" pulse width
tWLPH
15
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
30
ns
Latch pulse rise to shift clock rise time
tLS
25
ns
Latch pulse fall to shift clock fall time
tLH
25
ns
Enable setup time
tS
10
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
30
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Segment Mode 2) (LGND=VSS =GND = 0V, VDD = +3.0 ~ +4.5V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +85 °C)
PARAMETER
SYMBOL CONDITIONS MIN.
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF 10ns
66
ns
1
Shift clock "H" pulse width
tWCKH
23
ns
Shift clock "L” pulse width
tWCKL
23
ns
Data setup time
tDS
15
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
50
ns
Latch pulse rise to shift clock rise time
tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
41
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
Ver 2.1
Page 18/28
2009/08/19
ST8024
(Segment Mode 3) (LGND=VSS =GND = 0V, VDD = +2.5 ~ +3.0V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to+85 °C)
PARAMETER
SYMBOL CONDITIONS MIN.
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF 10ns
82
ns
1
Shift clock "H" pulse width
tWCKH
28
ns
Shift clock "L” pulse width
tWCKL
28
ns
Data setup time
tDS
20
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
65
ns
Latch pulse rise to shift clock rise time
tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
57
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Common Mode)
(LGND=VSS = 0 V, VDD = +2.5 ~ +5.5V, V0 = +15.0 ~ +30.0V, TOPR = -25 to +85° C)
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PARAMETER
SYMBOL
Shift clock period
tWLP
tR,tF 20ns
250
ns
VDD = +5.0± 0.5V
15
ns
Shift clock "H" pulse width
tWLPH
VDD = +2.5+ 4.5V
30
ns
Data setup time
tSU
30
ns
Data hold time
tH
50
ns
Input signal rise time
tR
50
ns
Input signal fall time
tF
50
ns
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tDL
CL = 15 pF
200
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
µs
Output delay time (3)
t PD3
CL = 15 pF
1.2
µs
Ver 2.1
Page 19/28
2009/08/19
ST8024
11.3
Timing Chart of Segment Mode
tWLPH
LP
tLD
tSL
tLH
tLS
tWCKH
tWCKL
XCK
tR
tF
tWCK
tDS
LAST DATA
DI7 - DI0
tWDL
tDH
TOP DATA
tSD
/DISPOFF
LP
XCK
1
n*
2
tS
EI
tD
EO
*n = 60 in 4-bit parallel input mode
*n = 30 in 8-bit parallel input mode
FR
tPD1
LP
tPD2
/DISPOFF
tPD3
Y1 - Y240
Figure 11-1
Ver 2.1
Timing Characteristics (3)
Page 20/28
2009/08/19
ST8024
11.4
Timing Chart of Common Mode
tWLP
LP
tR
tWLPH
t SU
tF
tH
EIO2
t DL
EIO1
tWDL
tSD
/DISPOFF
FR
tPD1
LP
tPD2
/DISPOFF
tPD3
Y1 - Y240
Ver 2.1
Page 21/28
2009/08/19
ST8024
12
APPLICATION CIRCUIT
12.1
Application Circuit for Module
Ver 2.1
Page 22/28
2009/08/19
ST8024
13
PAD DIAGRAM
Unit : um
Pad#
Name
1
VSS
X
Pad#
Name
-5464.70
Y
-471.00
30
XCK
X
1191.70
Y
-471.00
2
VSS
-5384.70
-471.00
31
DUMMY
1461.10
-471.00
3
GND
-5308.70
-471.00
32
/DISPOFF
1730.50
-471.00
4
GND
-5232.70
-471.00
33
DUMMY
1999.90
-471.00
5
VCC
-5156.70
-471.00
34
LP
2269.30
-471.00
6
VCC
-5080.70
-471.00
35
DUMMY
2538.70
-471.00
7
DUMMY
-5004.50
-471.00
36
EIO1
2808.10
-471.00
8
DBLKB
-4735.10
-471.00
37
DUMMY
3077.50
-471.00
9
DUMMY
-4465.70
-471.00
38
FR
3346.90
-471.00
10
S/C
-4196.30
-471.00
39
DUMMY
3616.30
-471.00
11
DUMMY
-3926.90
-471.00
40
L/R
3885.70
-471.00
12
EIO2
-3657.50
-471.00
41
DUMMY
4155.10
-471.00
13
DUMMY
-3388.10
-471.00
42
MD
4424.50
-471.00
14
DI0
-3118.70
-471.00
43
DUMMY
4693.90
-471.00
15
DUMMY
-2849.30
-471.00
44
TEST1
4963.30
-471.00
16
DI1
-2579.90
-471.00
45
GND
5232.70
-471.00
17
DUMMY
-2310.50
-471.00
46
GND
5308.70
-471.00
18
DI2
-2041.10
-471.00
47
VSS
5384.70
-471.00
19
DUMMY
-1771.70
-471.00
48
VSS
5464.70
-471.00
20
DI3
-1502.30
-471.00
49
DUMMY
5551.50
-471.00
21
DUMMY
-1232.90
-471.00
50
V34R
5557.00
-394.80
22
DI4
-963.50
-471.00
51
V34R
5557.00
-344.80
23
DUMMY
-694.10
-471.00
52
V12R
5557.00
-294.80
24
DI5
-424.70
-471.00
53
V12R
5557.00
-244.80
25
DUMMY
-155.30
-471.00
54
V0R
5557.00
-194.80
26
DI6
114.10
-471.00
55
V0R
5557.00
-144.80
27
DUMMY
383.50
-471.00
56
Y1
5557.00
-94.80
28
DI7
652.90
-471.00
57
Y2
5557.00
-44.80
29
DUMMY
922.30
-471.00
58
Y3
5557.00
5.20
Ver 2.1
Page 23/28
2009/08/19
ST8024
59
Y4
5557.00
55.20
109
Y53
3375.00
467.00
60
Y5
5557.00
105.20
110
Y54
3325.00
467.00
61
Y6
5557.00
155.20
111
Y55
3275.00
467.00
62
Y7
5557.00
205.20
112
Y56
3225.00
467.00
63
Y8
5557.00
255.20
113
Y57
3175.00
467.00
64
Y9
5557.00
305.20
114
Y58
3125.00
467.00
65
Y10
5557.00
355.20
115
Y59
3075.00
467.00
66
Y11
5557.00
405.20
116
Y60
3025.00
467.00
67
DUMMY
5551.50
474.00
117
Y61
2975.00
467.00
68
Y12
5425.00
467.00
118
Y62
2925.00
467.00
69
Y13
5375.00
467.00
119
Y63
2875.00
467.00
70
Y14
5325.00
467.00
120
Y64
2825.00
467.00
71
Y15
5275.00
467.00
121
Y65
2775.00
467.00
72
Y16
5225.00
467.00
122
Y66
2725.00
467.00
73
Y17
5175.00
467.00
123
Y67
2675.00
467.00
74
Y18
5125.00
467.00
124
Y68
2625.00
467.00
75
Y19
5075.00
467.00
125
Y69
2575.00
467.00
76
Y20
5025.00
467.00
126
Y70
2525.00
467.00
77
Y21
4975.00
467.00
127
Y71
2475.00
467.00
78
Y22
4925.00
467.00
128
Y72
2425.00
467.00
79
Y23
4875.00
467.00
129
Y73
2375.00
467.00
80
Y24
4825.00
467.00
130
Y74
2325.00
467.00
81
Y25
4775.00
467.00
131
Y75
2275.00
467.00
82
Y26
4725.00
467.00
132
Y76
2225.00
467.00
83
Y27
4675.00
467.00
133
Y77
2175.00
467.00
84
Y28
4625.00
467.00
134
Y78
2125.00
467.00
85
Y29
4575.00
467.00
135
Y79
2075.00
467.00
86
Y30
4525.00
467.00
136
Y80
2025.00
467.00
87
Y31
4475.00
467.00
137
Y81
1975.00
467.00
88
Y32
4425.00
467.00
138
Y82
1925.00
467.00
89
Y33
4375.00
467.00
139
Y83
1875.00
467.00
90
Y34
4325.00
467.00
140
Y84
1825.00
467.00
91
Y35
4275.00
467.00
141
Y85
1775.00
467.00
92
Y36
4225.00
467.00
142
Y86
1725.00
467.00
93
Y37
4175.00
467.00
143
Y87
1675.00
467.00
94
Y38
4125.00
467.00
144
Y88
1625.00
467.00
95
Y39
4075.00
467.00
145
Y89
1575.00
467.00
96
Y40
4025.00
467.00
146
Y90
1525.00
467.00
97
Y41
3975.00
467.00
147
Y91
1475.00
467.00
98
Y42
3925.00
467.00
148
Y92
1425.00
467.00
99
Y43
3875.00
467.00
149
Y93
1375.00
467.00
100
Y44
3825.00
467.00
150
Y94
1325.00
467.00
101
Y45
3775.00
467.00
151
Y95
1275.00
467.00
102
Y46
3725.00
467.00
152
Y96
1225.00
467.00
103
Y47
3675.00
467.00
153
Y97
1175.00
467.00
104
Y48
3625.00
467.00
154
Y98
1125.00
467.00
105
Y49
3575.00
467.00
155
Y99
1075.00
467.00
106
Y50
3525.00
467.00
156
Y100
1025.00
467.00
107
Y51
3475.00
467.00
157
Y101
975.00
467.00
108
Y52
3425.00
467.00
158
Y102
925.00
467.00
Ver 2.1
Page 24/28
2009/08/19
ST8024
159
Y103
875.00
467.00
209
Y153
-1625.00
467.00
160
Y104
825.00
467.00
210
Y154
-1675.00
467.00
161
Y105
775.00
467.00
211
Y155
-1725.00
467.00
162
Y106
725.00
467.00
212
Y156
-1775.00
467.00
163
Y107
675.00
467.00
213
Y157
-1825.00
467.00
164
Y108
625.00
467.00
214
Y158
-1875.00
467.00
165
Y109
575.00
467.00
215
Y159
-1925.00
467.00
166
Y110
525.00
467.00
216
Y160
-1975.00
467.00
167
Y111
475.00
467.00
217
Y161
-2025.00
467.00
168
Y112
425.00
467.00
218
Y162
-2075.00
467.00
169
Y113
375.00
467.00
219
Y163
-2125.00
467.00
170
Y114
325.00
467.00
220
Y164
-2175.00
467.00
171
Y115
275.00
467.00
221
Y165
-2225.00
467.00
172
Y116
225.00
467.00
222
Y166
-2275.00
467.00
173
Y117
175.00
467.00
223
Y167
-2325.00
467.00
174
Y118
125.00
467.00
224
Y168
-2375.00
467.00
175
Y119
75.00
467.00
225
Y169
-2425.00
467.00
176
Y120
25.00
467.00
226
Y170
-2475.00
467.00
177
Y121
-25.00
467.00
227
Y171
-2525.00
467.00
178
Y122
-75.00
467.00
228
Y172
-2575.00
467.00
179
Y123
-125.00
467.00
229
Y173
-2625.00
467.00
180
Y124
-175.00
467.00
230
Y174
-2675.00
467.00
181
Y125
-225.00
467.00
231
Y175
-2725.00
467.00
182
Y126
-275.00
467.00
232
Y176
-2775.00
467.00
183
Y127
-325.00
467.00
233
Y177
-2825.00
467.00
184
Y128
-375.00
467.00
234
Y178
-2875.00
467.00
185
Y129
-425.00
467.00
235
Y179
-2925.00
467.00
186
Y130
-475.00
467.00
236
Y180
-2975.00
467.00
187
Y131
-525.00
467.00
237
Y181
-3025.00
467.00
188
Y132
-575.00
467.00
238
Y182
-3075.00
467.00
189
Y133
-625.00
467.00
239
Y183
-3125.00
467.00
190
Y134
-675.00
467.00
240
Y184
-3175.00
467.00
191
Y135
-725.00
467.00
241
Y185
-3225.00
467.00
192
Y136
-775.00
467.00
242
Y186
-3275.00
467.00
193
Y137
-825.00
467.00
243
Y187
-3325.00
467.00
194
Y138
-875.00
467.00
244
Y188
-3375.00
467.00
195
Y139
-925.00
467.00
245
Y189
-3425.00
467.00
196
Y140
-975.00
467.00
246
Y190
-3475.00
467.00
197
Y141
-1025.00
467.00
247
Y191
-3525.00
467.00
198
Y142
-1075.00
467.00
248
Y192
-3575.00
467.00
199
Y143
-1125.00
467.00
249
Y193
-3625.00
467.00
200
Y144
-1175.00
467.00
250
Y194
-3675.00
467.00
201
Y145
-1225.00
467.00
251
Y195
-3725.00
467.00
202
Y146
-1275.00
467.00
252
Y196
-3775.00
467.00
203
Y147
-1325.00
467.00
253
Y197
-3825.00
467.00
204
Y148
-1375.00
467.00
254
Y198
-3875.00
467.00
205
Y149
-1425.00
467.00
255
Y199
-3925.00
467.00
206
Y150
-1475.00
467.00
256
Y200
-3975.00
467.00
207
Y151
-1525.00
467.00
257
Y201
-4025.00
467.00
208
Y152
-1575.00
467.00
258
Y202
-4075.00
467.00
Ver 2.1
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2009/08/19
ST8024
259
Y203
-4125.00
467.00
282
Y226
-5275.00
467.00
260
Y204
-4175.00
467.00
283
Y227
-5325.00
467.00
261
Y205
-4225.00
467.00
284
Y228
-5375.00
467.00
262
Y206
-4275.00
467.00
285
Y229
-5425.00
467.00
263
Y207
-4325.00
467.00
286
DUMMY
-5551.50
474.00
264
Y208
-4375.00
467.00
287
Y230
-5557.00
405.20
265
Y209
-4425.00
467.00
288
Y231
-5557.00
355.20
266
Y210
-4475.00
467.00
289
Y232
-5557.00
305.20
267
Y211
-4525.00
467.00
290
Y233
-5557.00
255.20
268
Y212
-4575.00
467.00
291
Y234
-5557.00
205.20
269
Y213
-4625.00
467.00
292
Y235
-5557.00
155.20
270
Y214
-4675.00
467.00
293
Y236
-5557.00
105.20
271
Y215
-4725.00
467.00
294
Y237
-5557.00
55.20
272
Y216
-4775.00
467.00
295
Y238
-5557.00
5.20
273
Y217
-4825.00
467.00
296
Y239
-5557.00
-44.80
274
Y218
-4875.00
467.00
297
Y240
-5557.00
-94.80
275
Y219
-4925.00
467.00
298
V0L
-5557.00
-144.80
276
Y220
-4975.00
467.00
299
V0L
-5557.00
-194.80
277
Y221
-5025.00
467.00
300
V12L
-5557.00
-244.80
278
Y222
-5075.00
467.00
301
V12L
-5557.00
-294.80
279
Y223
-5125.00
467.00
302
V34L
-5557.00
-344.80
280
Y224
-5175.00
467.00
303
V34L
-5557.00
-394.80
281
Y225
-5225.00
467.00
304
DUMMY
-5551.50
-471.00
13.1
Gold Bump Size
Pad No.
X
Y
1~48(not DUMMY)
58
60
50~66,287~303
74
35
7~43(DUMMY only)
58
60
68~285
35
74
49,67,286,304
85
60
Wafer thickness = 675±20um, Bump pad height = 15um, strength=30g
Ver 2.1
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2
Area (um )
3480
2590
3480
2590
5100
2009/08/19
ST8024
14
APPLITION NOTE ( REFERENCE ONLY )
14.1 PCB and ITO layout notice:
Pin Name
ITO Resistor Values
Less than 75 when VDD ≧ 3.0V, and the smaller the better
LGND, GND, VDD, Vss
V0R, V0L
Less than 150 , and the smaller the better
V12R, V12L, V34R, V12L Less than 250 , and the smaller the better
PS : Above resistor value test on 3” LCD panel.
14.2 We suggest the ITO resistor for LCD panel is less than 15Ω/Square, and the resistor value is as
smaller as better.
14.3 Adjust V1 and V4 voltage to keep the V0-V1 = V4-VSS relation to get better display quality. The
(V0-V1)-(V4-VSS) value had better less than 100mV.
14.4 Add 0.1uF high frequency by-pass capacitor to filter the noise on V0~V4 to VSS.
14.5 When OP follower circuit is used, please be sure the OP power is higher than V0 at least 1.5V.
14.6 EIO1 and EIO2 is enable pin for driver, please pay attention to the distance to avoid noise when
cascade function is used. Two chip connecting distance is as shorter as better.
Ver 2.1
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2009/08/19
ST8024
15
REVISION
REVISION
0.20
0.21
0.24
0.25
0.26
0.27
0.28
0.29
0.30
0.31
1.0
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
DESCRIPTION
Add pad location and gold bump data
Add BLANK contrast control information
Add TCP (F4) information
Remove TCP information to another PDF file
ST8024TCP(F4).PDF
Gold bump strength=30g, update IC diagram
Correct wrong word mistake
Correct parameter name
Correct DI to FLM
Change operating temperature from -20°C~85°C to
-25°C~85°C
Change description of TEST1 pin in PIN DESCRIPTION(TCP)
Add 1 and 48 Gold Bump size
Modify TCP package
Rename V5 to Vss and some pins' description
Modify PAD sequence
Add alignment mark
Add max value for input high voltage
Add wafer thickness information and roughly TCP drawing
information.
Modify chip size and thickness with scribe line and Spec
arrangement
Modify all the data about absolute max voltage and recommend max
voltage
Modify Pad Diagram
Add application note
Modify Pad Location
PAGE
DATE
16
2006/12/11
1-27
2006/12/25
2,16-19
2007/05/25
23
27
24
2008/1/14
2008/05/07
2009/0819
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without
permission from Sitronix.
Ver 2.1
Page 28/28
2009/08/19