SITRONIX ST8024S

ST8024S
COM/SEG LCD Driver
Datasheet
Version 0.39
2008/05/05
Note: Sitronix Technology Corp. reserves
the right to change the contents in this
document without prior notice. This is not
a final specification. Some parameters
are subject to change.
ST8024S
1.
FEATURES
n
n
n
n
n
Number of LCD drive outputs: 240
Supply voltage for LCD drive: +15.0 to +30.0 V
Supply voltage for the logic system: +2.5 to +5.5 V
Low power consumption
Low output impedance
(Segment mode)
n Shift clock frequency
Ø 20MHz(MAX.):VDD = +5.0 ± 0.5 V
Ø 15MHz(MAX.):VDD = +3.0 to + 4.5 V
Ø 12MHz(MAX.):VDD = +2.5 to + 3.0 V
n Adopts a data bus system
n 4-bit/8-bit parallel input modes are
selectable with a mode (MD) pin
n Automatic transfer function of an
enable signal
n Automatic counting function which, in
the chip selection mode, causes the
internal clock to be stopped by
automatically counting 240 bits of
input data
n Line latch circuits are reset when
/DISPOFF active
2.
(Common mode)
n Shift clock frequency: 4 MHz (MAX.)
n Built-in 240-bit bi-directional shift
register (divisible into 120 bits x 2)
n Available in a single mode (240-bit
shift register) or in a dual mode
(120-bit shift register x 2)
Ø Y1->Y240 Single mode
Ø Y240->Y1 Single mode
Ø Y1->Yl20, Y121->Y240 Dual mode
Ø Y240->Y121, Yl20->Y1 Dual mode
The above 4 shift directions are
in-selectable
n Shift register circuits are reset when
/DISPOFF active
DESCRIPTION
The ST8024S is a 240-output segment/common driver IC suitable for driving large/medium scale
dot matrix LCD panels, and is used in personal computers/work stations. The ST8024S is good
both as a segment driver and a common driver, and it can create a low power consuming,
high-resolution LCD.
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ST8024S
3.
BLOCK DIAGRAM
V0R
FR
/DISPOFF
V12R
V43R
VSS
Y1
Y2
Y239
Y240
VSS
LEVEL
SHIFTER
240-BIT 4-LEVEL DRIVER
V43L
240
EIO1
EIO2
V12L
240-BIT LEVEL SHIFTER
ACTIVE
CONTROL
V0L
240
240-BIT LINE LATCH/SHIFT REGISTER
16
LP
XCK
16
16
8 BIT
DATA
LATCH
CONTROL
LOGIC
8
DATA CONTROL
L/R
MD
SP CONVERSION & DATA CONTROL
(4 to 8 or 8 to 8)
S/C
DI0
4.
DI1
DI2
DI3
DI4
DI5
DI6
DI7
VDD
V SS
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
In case of segment mode, controls the selection or non-selection of the chip. Following
an LP signal input, and after the chip selection signal is input, a selection signal is
generated internally until 240 bits of data have been read in. Once data input has been
Active Control
completed, a selection signal for cascade connection is output, and the chip is
non-selected. In case of common mode, controls the input/output data of bi-directional
pins.
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel
SP Conversion
input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel
& Data Control
input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time.
In case of segment mode, selects the state of the data latch which reads in the data bus
Data Latch Control signals. The shift direction is controlled by the control logic. For every 16 bits of data
read in, the selection signal shifts one bit based on the state of the control circuit.
In case of segment mode, latches the data on the data bus. The latch state of each LCD
Data Latch
drive output pin is controlled by the control logic and the data latch control; 240 bits of
data are read in 30 sets of 8 bits.
In case of segment mode, all 240 bits which have been read into the data latch are
simultaneously latched at the falling edge of the LP signal, and are output to the level
Line Latch/
Shift Register
shifter block. In case of common mode, shifts data from the data input pin at the falling
edge of the LP signal.
Level Shifter
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to
the driver block.
Drives the LCD drive output pins from the line latch/shift register data, and selects one of
4-Level Driver
4 levels (V0, V12, V43 or Vss) based on the S/C, FR and /DISPOFF signals.
Controls the operation of each block. In case of segment mode, when an LP signal has
been input, all blocks are reset and the control logic waits for the selection signal output
Control Logic
from the active control block. Once the selection signal has been output, operation of the
data latch and data transmission is controlled, 240 bits of data are read in, and the chip
is non-selected. In case of common mode, controls the direction of data shift.
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ST8024S
5.
INPUT/OUTPUT CIRCUITS
V DD
I
To Internal Circuit
Applicable Pins
L/R , S/C , DI 6~DI0 ,
/DISPOFF , LP , FR , MD
GND (0V)
Figure 1 Input Circuit (1)
V DD
I
To Internal Circuit
Control Signal
GND (0V)
Applicable Pins
DI7 , XCK
GND (0V)
Figure 2 Input Circuit (2)
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ST8024S
V DD
To Internal
Circuit
I/O
Control Signal
GND (0V)
GND (0V)
VDD
Output Signal
Application Pins
EIO1 , EIO2
Control Signal
GND (0V)
Figure 3 Input/Output Circuit
V0
V12
V0
Control Signal 1
Control Signal 2
Control Signal 3
Control Signal 4
O
GND (0V)
V43
GND (0V)
VSS
Application Pins
Y1~Y160
Figure 4 LCD Drive Output Circuit
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ST8024S
6.
FUNCTIONAL DESCRIPTION
6.1
Pin Functions
(Segment mode)
SYMBOL
VDD
GND
LGND
VSS
V0L, V0R
V12L, V12R
V43L, V43R
DI7-DI0
XCK
LP
L/R
/DISPOFF
FR
MD
S/C
ElO1, EIO2
Ver 0.39
FUNCTION
Logic system power supply pin,
Ÿ Connected to +2.5 to +5.5 V.
Ground pin
Logic ground pin
Ÿ Do not short LGND with GND and Vss by ITO on LCD panel
Ÿ Connect it to GND on PCB or FPC.
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Ÿ Normally use the bias voltages set by a resistor divider
Ÿ Ensure that voltages are set such that VSS < V43 < V12 < V0.
Ÿ ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin
Input pins for display data
Ÿ In 4-bit parallel mode, DI3-DI0 are the display data input pins, and DI7-DI4 must be
connected to LGND or VDD.
Ÿ In 8-bit parallel mode, All DI7-Dl0 pins are the display data input pins.
Ÿ Refer to section 6.2.2.
Clock input pin for taking display data
Ÿ Data is read at the falling edge of the clock pulse.
Latch pulse input pin for display data
Ÿ Data is latched at the falling edge of the clock pulse.
Input pin for selecting the reading direction of display data
Ÿ When set to LGND level "L", data is read sequentially from Y240 to Y1.
Ÿ When set to VDD level "H", data is read sequentially from Y1 to Y240.
Refer to section 6.2.2.
Control input pin for output of non-select level
Ÿ The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Ÿ When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level Vss.
Ÿ When set to "L", the contents of the line latch are reset, but the display data are read in
the
data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is
canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of
the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time
does not correspond to what is shown in AC characteristics, it can not output the
reading data correctly.
Ÿ Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
Ÿ The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Ÿ Normally it inputs a frame inversion signal.
Ÿ The LCD drive output pins' output voltage levels can be set using the line latch output
signal and the FR signal.
Ÿ Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
Ÿ When set to LGND level "L", 8-bit parallel input mode is set.
Ÿ When set to VDD level "H", 4-bit parallel input mode is set.
Ÿ Refer to section 6.2.2.
Segment mode/common mode selection pin
Ÿ When set to VDD level "H", segment mode is set.
Input/output pins for chip selection
Ÿ When L/R input is at LGND level "L", ElO1 is set for output, and EIO2 is set for input.
Ÿ When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output.
Ÿ During output, set to "H" while LP • XCK is "H" and after 240 bits of data have been
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ST8024S
Y1 -Y240
(Common mode)
SYMBOL
VDD
GND
LGND
VSS
V0L, V0R
V12L, V12R
V43L, V43R
ElO1
EIO2
LP
L/R
/DISPOFF
FR
MD
Ver 0.39
read, set
to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to
"H".
Ÿ During input, the chip is selected while El is set to "L" after the LP signal is input. The
chip is non-selected after 240 bits of data have been read.
LCD drive output pins
Ÿ Corresponding directly to each bit of the data latch, one level (V0, V12, V43, or VSS) is
selected and output.
Ÿ Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
FUNCTION
Logic system power supply pin, connected to +2.5 to +5.5 V.
Ground pin
Logic ground pin
Ÿ Do not short LGND with GND and Vss by ITO on LCD panel
Ÿ Connect it to GND on PCB or FPC.
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Ÿ Normally use the bias voltages set by a resistor divider.
Ÿ Ensure that voltages are set such that VSS < V43 < V12 < V0.
Ÿ ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin.
Shift data input/output pin for bi-directional shift register
Ÿ Output pin when L/R is at LGND level "L', input pin when L/R is at VDD level "H".
Ÿ When L/R = H, ElO1 is used as input pin, it will be pulled down.
Ÿ When L/R = L, ElO1 is used as output pin, it won't be pulled down.
Ÿ Refer to section 6.2.2.
Shift data input/output pin for bi-directional shift register
Ÿ Input pin when L/R is at LGND level "L", output pin when L/R is at VDD level "H".
Ÿ When L/R = L, EIO2 is used as input pin, it will be pulled down.
Ÿ When L/R = H, EIO2 is used as output pin, it won't be pulled down.
Ÿ Refer to section 6.2.2.
Shift clock pulse input pin for bi-directional shift register
Ÿ Data is shifted at the falling edge of the clock pulse.
Input pin for selecting the shift direction of bi-directional shift register
Ÿ Data is shifted from Y240 to Y1 when set to LGND level "L", and data is shifted from Y1 to
Y240 when set to VDD level "H".
Ÿ Refer to section 6.2.2.
Control input pin for output of non-select level
Ÿ The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Ÿ When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level LGND.
Ÿ When set to "L”, the contents of the shift register are reset to not reading data. When
the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and
the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF
removal time does not correspond to what is shown in AC characteristics, the shift data
is not read correctly.
Ÿ Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
Ÿ The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Ÿ Normally it inputs a frame inversion signal.
Ÿ The LCD drive output pins' output voltage levels can be set using the shift register
output signal and the FR signal.
Ÿ Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
Ÿ When set to LGND level "L", single mode operation is selected; when set to VDD level
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ST8024S
DI7
S/C
DI6-DI0
XCK
Y1 -Y240
6.2
6.2.1
"H" dual mode operation is selected.
Ÿ Refer to section 6.2.2.
Dual mode data input pin
Ÿ According to the data shift direction of the data shift register, data can be input starting
from the 121st bit.
When the chip is used in dual mode, DI7 will be pulled down.
When the chip is used in single mode, DI7 won't be pulled down.
Ÿ Refer to section 6.2.2.
Segment mode/common mode selection pin
Ÿ When set to LGND level "L", common mode is set.
Not used
Ÿ Connect DI6-DI0 to LGND or VDD, avoiding floating.
Not used
Ÿ XCK is pulled down in common mode, so connect to LGND or open.
LCD drive output pins
Ÿ Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS) is
selected and output.
Ÿ Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Functional Operations
Truth table
(Segment Mode)
FR
LATCH DATA
L
L
L
H
H
L
H
H
X
X
/DISPOFF
H
H
H
H
L
LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240)
V43
VSS
V12
V0
VSS
(Common Mode)
FR
LATCH DATA
/DISPOFF
LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240)
L
L
H
V43
L
H
H
V0
H
L
H
V12
H
H
H
VSS
X
X
L
VSS
NOTES:
1. VSS < V43 < V12 < V0
2. L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care
3. "Don't care" should be fixed to "H" or "L", avoiding floating.
There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver.
Supply regular voltage which is assigned by specification for each power pin.
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ST8024S
6.2.2
Relationship between the display data and LCD drive output Pins
(Segment Mode)
(a) 4-bit Parallel Input Mode
NUMBER OF CLOCKS
DATA
MD L/R EIO1
EI02
INPUT 60 CLOCK 59 CLOCK 58 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK
DI0
Y1
Y5
Y9
…
Y229
Y233
Y237
Dl1
Y2
Y6
Y10
…
Y230
Y234
Y238
H L Output Input
DI2
Y3
Y7
Y11
…
Y231
Y235
Y239
DI3
Y4
Y8
Y12
…
Y232
Y236
Y240
DI0
Y240
Y236
Y232
…
Y12
Y8
Y4
Dl1
Y239
Y235
Y231
…
Y11
Y7
Y3
H H Input Output
DI2
Y238
Y234
Y230
…
Y10
Y6
Y2
DI3
Y237
Y233
Y229
…
Y9
Y5
Y1
(b)
8-bit Parallel Input Mode
DATA
NUMBER OF CLOCKS
MD L/R EIO1
EI02
INPUT 30 CLOCK 29 CLOCK 28 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK
DI0
Y1
Y9
Y17
…
Y217
Y225
Y233
Dl1
Y2
Y10
Y18
…
Y218
Y226
Y234
DI2
Y3
Y11
Y19
…
Y219
Y227
Y235
DI3
Y4
Y12
Y20
…
Y220
Y228
Y236
L L Output Input
DI4
Y5
Y13
Y21
Y221
Y229
Y237
DI5
Y6
Y14
Y22
Y222
Y230
Y238
DI6
Y7
Y15
Y23
Y223
Y231
Y239
DI7
Y8
Y16
Y24
Y224
Y232
Y240
DI0
Y240
Y232
Y224
…
Y24
Y16
Y8
Dl1
Y239
Y231
Y223
…
Y23
Y15
Y7
DI2
Y238
Y230
Y222
…
Y22
Y14
Y6
DI3
Y237
Y229
Y221
…
Y21
Y13
Y5
L H Input Output
DI4
Y236
Y228
Y220
…
Y20
Y12
Y4
Dl5
Y235
Y227
Y219
…
Y19
Y11
Y3
DI6
Y234
Y226
Y218
…
Y18
Y10
Y2
DI7
Y233
Y225
Y217
…
Y17
Y9
Y1
(Common Mode)
MD
L
(Single)
H
(Dual)
L/R
L
H
L
H
DATA TRANSFER DIRECTION
Y240 → Y1
Y1 → Y240
Y240 → Y121
Y120 → Y1
Y1 → Y120
Y121 → Y240
EIO1
Output
Input
EI02
Input
Output
DI7
X
X
Output
Input
Input
Input
Output
Input
NOTES:
1. L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care
2. "Don't care" should be fixed to "H" or "L", avoiding floating.
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ST8024S
6.2.3
(a)
Connection examples of plural segment drivers
When L/R = “L”
Top data
Last data
Data flow
Y1
Y240
EIO2
EIO1
Y240
Y1
EIO2
EIO1
L/R
Y240
Y1
EIO2
EIO1
L/R
L/R
DI7-DI0
FR
MD
LP
XCK
DI7-DI0
FR
MD
LP
XCK
DI7-DI0
FR
MD
LP
XCK
XCK
LP
MD
FR
DI7-DI 0
8
LGND
(b)
When L/R = “H”
VDD
XCK
LP
MD
FR
DI7-DI0
8
DI7-DI0
FR
MD
L/R
EIO1
EIO2
EIO1
EIO2
EIO1
EIO2
Y1
Y240
Y1
Y240
Y1
Y240
Data flow
Last data
Top data
Ver 0.39
LP
L/R
XCK
DI7-DI0
FR
MD
LP
XCK
DI7-DI0
FR
MD
LP
XCK
L/R
LGND
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ST8024S
6.2.4
Timing chart of 4-device cascade connection of segment drivers
FR
LP
XCK
TOP DATA
DI7 - DI0
n*
1
2
LAST DATA
n*
device A
1
2
n*
device B
1
2
n*
device C
1
2
n*
1
2
device D
EI
(device A)
EO
(device A)
EO
(device B)
EO
(device C)
*n = 60 in 4-bit parallel input mode
*n = 30 in 8-bit parallel input mode
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ST8024S
6.2.5
(a)
Connection examples for plural common drivers
Single Mode (L/R = ”L”)
Data flow
First
FLM
Last
Y240
Y1
Y240
Y1
Y240
Y1
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1
FR
L/R
/DISPOFF
DI7
MD
LP
FR
L/R
/DISPOFF
DI7
MD
LP
FR
L/R
/DISPOFF
DI7
MD
LP
LP
LGND(VDD )
LGND
/DISPOFF
FR
(b)
Single Mode (L/R = “H”)
FR
/DISPOFF
V DD
LGND
LGND (V DD)
LP
LP
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DI7
Data flow
Y1
L/R
Y240
EIO1
MD
Y1
EIO2
FR
EIO1
/DISPOFF
LP
DI7
MD
L/R
Y240
FR
EIO2
/DISPOFF
LP
Ver 0.39
DI7
First
L/R
Y1
MD
FR
EIO1
/DISPOFF
FLM
EIO2
Y240
Last
2008/05/05
ST8024S
(c)
Dual Mode (L/R = “L”)
Data flow
Last 1
First
FLM1
Y240
Y1
EIO2
EIO1
First 2
Last 2
Y240 Y121 Y120 Y1
EIO2
EIO1
Y240
Y1
EIO2
EIO1
L/R
FR
MD
FR
/DISPOFF
/DISPOFF
DI7
L/R
LP
FR
MD
DI7
L/R
/DISPOFF
MD
FR
/DISPOFF
L/R
LP
DI7
FR
MD
DI7
L/R
/DISPOFF
MD
L/R
/DISPOFF
LP
DI7
LP
FLM2
LGND (VDD)
VDD
LGND
/DISPOFF
FR
(d)
Dual mode (L/R = “H”)
FR
/DISPOFF
VDD
LGND
LGND (V DD)
FLM2
LP
Y1 Y120 Y121 Y240
Last 1 First 2
EIO1
Y1
LP
Ver 0.39
EIO2
MD
First 1
Y240
EIO1
DI7
Y1
EIO2
LP
EIO1
LP
FR
FLM1
EIO2
Y240
Last 2
Data flow
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ST8024S
7.
PRECAUTIONS
Precautions when connecting or disconnecting the power supply
This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which
may flow if voltage is supplied to the LCD drive power supply while the logic system power supply
is floating. The details are as follows,
Ÿ When connecting the power supply, connect the LCD drive power after connecting the logic
system power. Furthermore, when disconnecting the power, disconnect the logic system power
after disconnecting the LCD drive power
Ÿ It is advisable to connect the serial resistor (50 to 100 Ω) or fuse to the LCD drive power V0 of
the system as a current limiter. Set up a suitable value of the resistor in consideration of the
display grade.
And when connecting the logic power supply, the logic condition of this IC inside is insecure.
Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on
/DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply
has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to
level LGND on /DISPOFF function. Then disconnect the logic system power after disconnecting
the LCD drive power.
When connecting the power supply, follow the recommended sequence shown here
VDD
VDD
LGND
VDD
/DISPOFF
LGND
V0
V0
GND
.
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ST8024S
8.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply voltage (1)
Supply voltage (2)
Input voltage
SYMBOL
VDD
V0
V12
V43
VSS
VI
APPLICABLE PINS
VDD
V0L, V0R
V12L, V12R
V43L, V43R
VSS
DI7-DI0, XCK, LP, L/R, FR,
MD, S/C, EIO1, EIO2,
/DISPOFF
RATING
-0.3 to +7.0
-0.3 to +33.0
-0.3 to V0 + 0.3
-0.3 to V0 + 0.3
-0.3 toV0+0.3
UNIT
V
V
V
V
V
-0.3 to VDD + 0.3
V
NOTE
1,2
Storage temperature
TSTG
-45 to +125
°C
NOTES:
1. TA = +25 °C
2. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V).
3. Stress over the “ Absolute Max. Ratings” conditions will damage the device permanently.
9.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL APPLICABLE PINS
MIN.
TYP. MAX. UNIT
Supply voltage (1)
VDD
VDD
+2.5
+5.5
V
Supply voltage (2)
V0
V0L, V0R
+15.0
+30.0
V
°C
Operating temperature
TOPR
-25
+85
NOTES:
1. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V).
2. Ensure that voltages are set such that VSS < V43 < Vl2 < V0.
Ver 0.39
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NOTE
1, 2
2008/05/05
ST8024S
10.
ELECTRICAL CHARACTERISTICS
10.1
DC Characteristics
(Segment Mode) (LGND=VSS = GND = 0V, VDD = +2.5 to +5.5V, V0 = +15.0 to +30.0V, TOPR = -25 to +85°C)
PARAMETER
SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE
DI7-DI0, XCK, LP, L/R
Input "Low" voltage
VIL
0.2VDD
V
FR, MD, S/C, EIO1,
0.8VDD
Input "High" voltage
VIH
VDD+0.8 V
EIO2, /DISPOFF
Output "Low" voltage
VOL
IOL = +0.4 mA
+0.4
V
EIO1, EIO2
Output "High" voltage
VOH
IOH = -0.4 mA
VDD-0.4
V
ILIL
VI = LGND DI7-DI0, XCK, LP, L/R
-10.0
μA
Input leakage current
FR, MD, S/C, EIO1,
ILIH
VI = VDD
+ 10.0 μ A
EIO2, /DISPOFF
Output resistance
RON
|∆ VON| V0=30V
=0.5V V0=20V
Y1-Y240
1.5
2.0
2.0
2.5
75.0
kΩ
Standby current
ISTB
LGND
μA
1
Supply current (1)
2
IDD1
VDD
2.0
mA
(Non-selection)
Supply current (2)
3
IDD2
VDD
12.0
mA
(Selection)
Supply current (3)
I0
V0L, V0R
1.5
mA
4
NOTES:
1. VDD = +5.0 V, V0 = +30.0 V, Vi = LGND.
2. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20 MHz, no-load, El = VDD. The input data is turned over by data taking
clock (4-bit parallel input mode).
3. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20 MHz, no-load, El = LGND. The input data is turned over by data
taking clock (4-bit parallel input mode).
4. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20MHz, fLP = 41.6 kHz, fFR = 80 Hz, no-load. The input data is turned
over by data taking clock (4-bit parallel input mode).
(Common Mode) (LGND=VSS = GND = 0V, VDD = +2.5 to +5.5V, V0 = +15.0 to +30.0V, TOPR = -25 to +85°C)
PARAMETER
SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE
DI7-DI0, XCK, LP, L/R
Input "Low" voltage
VIL
0.2VDD
V
FR, MD, S/C, EIO1,
0.8VDD
Input "High" voltage
VIH
VDD+0.8 V
EIO2, /DISPOFF
Output "Low" voltage
VOL
IOL = +0.4 mA
+0.4
V
EIO1, EIO2
Output "High" voltage
VOH
IOH = -0.4 mA
VDD-0.4
V
DI7-DI0, XCK, LP, L/R
ILIL
VI = LGND FR, MD, S/C, EIO1,
-10.0
μA
EIO2, /DISPOFF
Input leakage current
DI6-DI0, LP, L/R, FR,
ILIH
VI = VDD
MD, S/C, /DISPOFF
+10.0
μA
Input pull-down current
Output resistance
IPD
RON
VI = VDD
DI7, XCK, EIO1, EIO2
|∆ VON| V0=30V
Y1-Y240
=0.5V V0=20V
LGND
VDD
V0L, V0R
1.5
2.0
100.0
2.0
2.5
75.0
120.0
240.0
Standby current
ISPD
Supply current (1)
IDD
Supply current (2)
I0
NOTES:
1. VDD = +5.0 V, V0 = +30.0 V, VI = LGND
2. VDD = +5.0 V, V0 = +30.0 V, fLP = 41.6 kHz, fFR = 80 Hz, 1/480 duty operation, no-load.
Ver 0.39
Page 16/27
μA
kΩ
μA
μA
μA
1
2
2
2008/05/05
ST8024S
10.2
AC Characteristics
(Segment Mode 1) (LGND=VSS = GND = 0V, VDD = +5.0± 0.5V, V0 = +15.0 to +30.0V, TOPR = -25 to +85 °C)
PARAMETER
SYMBOL CONDITIONS MIN
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 10ns
50
ns
1
Shift clock "H" pulse width
tWCKH
15
ns
Shift clock "L" pulse width
tWCKL
15
ns
Data setup time
tDS
10
ns
Data hold time
tDH
12
ns
Latch pulse "H" pulse width
tWLPH
15
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
30
ns
Latch pulse rise to shift clock rise time
tLS
25
ns
Latch pulse fall to shift clock fall time
tLH
25
ns
Enable setup time
tS
10
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
30
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Segment Mode 2) (LGND=VSS = GND = 0V, VDD = +3.0 to +4.5V, V0 = +15.0 to +30.0V, TOPR = -25 to +85°C)
PARAMETER
SYMBOL CONDITIONS MIN.
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 10ns
66
ns
1
Shift clock "H" pulse width
tWCKH
23
ns
Shift clock "L” pulse width
tWCKL
23
ns
Data setup time
tDS
15
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
50
ns
Latch pulse rise to shift clock rise time
tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
41
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
Ver 0.39
Page 17/27
2008/05/05
ST8024S
(Segment Mode 3) (LGND=VSS = GND = 0V, VDD = +2.5 to +3.0V, V0 = +15.0 to +30.0V, TOPR = -25 to +85°C)
PARAMETER
SYMBOL CONDITIONS MIN.
TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 10ns
82
ns
1
Shift clock "H" pulse width
tWCKH
28
ns
Shift clock "L” pulse width
tWCKL
28
ns
Data setup time
tDS
20
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
65
ns
Latch pulse rise to shift clock rise time
tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
57
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Common Mode) (LGND=VSS = 0V, VDD = +2.5 to +5.5V, V0 = +15.0 to +30.0V, TOPR = -25 to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Shift clock period
tWLP
tR,tF ≤ 20ns
250
ns
VDD = +5.0± 0.5V
15
ns
Shift clock "H" pulse width
tWLPH
VDD = +2.5+ 4.5V
30
ns
Data setup time
tSU
30
ns
Data hold time
tH
50
ns
Input signal rise time
tR
50
ns
Input signal fall time
tF
50
ns
/DISPOFF removal time
tSD
100
ns
/DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tDL
CL = 15 pF
200
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
µs
Output delay time (3)
t PD3
CL = 15 pF
1.2
µs
Ver 0.39
Page 18/27
2008/05/05
ST8024S
10.3
Timing Chart of Segment Mode
tWLPH
LP
tLD
tSL
tLH
tLS
tWCKH
tWCKL
XCK
tR
tF
tWCK
tDS
LAST DATA
DI7 - DI0
tWDL
tDH
TOP DATA
tSD
/DISPOFF
LP
XCK
1
n*
2
tS
EI
tD
EO
*n = 60 in 4-bit parallel input mode
*n = 30 in 8-bit parallel input mode
FR
tPD1
LP
tPD2
/DISPOFF
tPD3
Y1 - Y 240
Fig. 8 Timing Characteristics (3)
Ver 0.39
Page 19/27
2008/05/05
ST8024S
10.4
Timing Chart of Common Mode
tWLP
LP
tR
tWLPH
t SU
tF
tH
EIO2
t DL
EIO1
tWDL
tSD
/DISPOFF
FR
tPD1
LP
tPD2
/DISPOFF
tPD3
Y1 - Y240
Ver 0.39
Page 20/27
2008/05/05
ST8024S
DI0~DI7
EIO2
FR
MD
EIO1
CONTROLLER
L/R
LCD Panel Layout Example
S/C
11.2
LP
Application Circuit for Module
/DISPOFF
APPLICATION CIRCUIT
11.1
XCK
11.
Pin Name
ITO Resistor Values
Less than 75Ω when VDD ≧ 3.0V, and the smaller the better
LGND, GND, VDD, Vss
V0R, V0L
Less than 150Ω, and the smaller the better
V12R, V12L, V34R, V12L Less than 250Ω, and the smaller the better
PS : Above resistor value test on 3” LCD panel.
Ver 0.39
Page 21/27
2008/05/05
ST8024S
12.
Notes:
PAD DIAGRAM
Subtract should be connected to GND.
Unit : um
Pad#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Ver 0.39
Name
V0L
V0L
V12L
V34L
VSS
VSS
GND
GND
LGND
VDD
VDD
S/C
EIO2
DUMMY
DI0
DI1
DI2
DI3
DI4
DI5
DUMMY
DUMMY
DUMMY
DUMMY
DI6
DI7
XCK
/DISPOFF
DUMMY
LP
EIO1
FR
L/R
MD
LGND
GND
GND
X
-4180.00
-4180.00
-4180.00
-4180.00
-4180.00
-4192.50
-3995.95
-3815.75
-3714.45
-3611.80
-3426.65
-3178.35
-2930.15
-2657.85
-2249.05
-2009.05
-1756.85
-1516.85
-1264.65
-1024.65
-674.40
-358.68
179.53
514.13
1098.65
1338.65
1590.85
1830.85
2098.15
2534.85
2783.05
3040.25
3280.25
3532.45
3714.45
3815.75
3995.95
Y
Pad#
264.00 38
214.50 39
148.50 40
82.50 41
16.50 42
-355.00 43
-383.10 44
-383.10 45
-383.10 46
-383.35 47
-379.35 48
-383.10 49
-383.10 50
-383.10 51
-383.10 52
-383.10 53
-383.10 54
-383.10 55
-383.10 56
-383.10 57
-344.40 58
-347.68 59
-337.73 60
-337.73 61
-383.10 62
-383.10 63
-383.10 64
-383.10 65
-383.10 66
-383.10 67
-383.10 68
-383.10 69
-383.10 70
-383.10 71
-383.10 72
-383.10 73
-383.10 74
Page 22/27
Name
VSS
VSS
V34R
V12R
V0R
V0R
V0R
DUMMY
DUMMY
DUMMY
DUMMY
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
X
4192.50
4180.00
4180.00
4180.00
4180.00
4180.00
4192.50
4123.70
4090.70
4057.70
4024.70
3991.70
3958.70
3925.70
3892.70
3859.70
3826.70
3793.70
3760.70
3727.70
3694.70
3661.70
3628.70
3595.70
3562.70
3529.70
3496.70
3463.70
3430.70
3397.70
3364.70
3331.70
3298.70
3265.70
3232.70
3199.70
3166.70
Y
-355.00
16.50
82.50
148.50
214.50
264.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
2008/05/05
ST8024S
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
173
Ver 0.39
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y123
3133.70
3100.70
3067.70
3034.70
3001.70
2968.70
2935.70
2902.70
2869.70
2836.70
2803.70
2770.70
2737.70
2704.70
2671.70
2638.70
2605.70
2572.70
2539.70
2506.70
2473.70
2440.70
2407.70
2374.70
2341.70
2308.70
2275.70
2242.70
2209.70
2176.70
2143.70
2110.70
2077.70
2044.70
2011.70
1978.70
1945.70
1912.70
1879.70
1846.70
1813.70
1780.70
1747.70
1714.70
1681.70
1648.70
1615.70
1582.70
1549.70
-130.70
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
222
Page 23/27
Y76
Y77
Y78
Y79
Y80
Y81
Y82
Y83
Y84
Y85
Y86
Y87
Y88
Y89
Y90
Y91
Y92
Y93
Y94
Y95
Y96
Y97
Y98
Y99
Y100
Y101
Y102
Y103
Y104
Y105
Y106
Y107
Y108
Y109
Y110
Y111
Y112
Y113
Y114
Y115
Y116
Y117
Y118
Y119
Y120
DUMMY
DUMMY
Y121
Y122
Y172
1516.70
1483.70
1450.70
1417.70
1384.70
1351.70
1318.70
1285.70
1252.70
1219.70
1186.70
1153.70
1120.70
1087.70
1054.70
1021.70
988.70
955.70
922.70
889.70
856.70
823.70
790.70
757.70
724.70
691.70
658.70
625.70
592.70
559.70
526.70
493.70
460.70
427.70
394.70
361.70
328.70
295.70
262.70
229.70
196.70
163.70
130.70
97.70
64.70
31.70
-31.70
-64.70
-97.70
-1747.70
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
2008/05/05
ST8024S
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
271
272
Ver 0.39
Y124
Y125
Y126
Y127
Y128
Y129
Y130
Y131
Y132
Y133
Y134
Y135
Y136
Y137
Y138
Y139
Y140
Y141
Y142
Y143
Y144
Y145
Y146
Y147
Y148
Y149
Y150
Y151
Y152
Y153
Y154
Y155
Y156
Y157
Y158
Y159
Y160
Y161
Y162
Y163
Y164
Y165
Y166
Y167
Y168
Y169
Y170
Y171
Y221
Y222
-163.70
-196.70
-229.70
-262.70
-295.70
-328.70
-361.70
-394.70
-427.70
-460.70
-493.70
-526.70
-559.70
-592.70
-625.70
-658.70
-691.70
-724.70
-757.70
-790.70
-823.70
-856.70
-889.70
-922.70
-955.70
-988.70
-1021.70
-1054.70
-1087.70
-1120.70
-1153.70
-1186.70
-1219.70
-1252.70
-1285.70
-1318.70
-1351.70
-1384.70
-1417.70
-1450.70
-1483.70
-1516.70
-1549.70
-1582.70
-1615.70
-1648.70
-1681.70
-1714.70
-3364.70
-3397.70
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
284
285
Page 24/27
Y173
Y174
Y175
Y176
Y177
Y178
Y179
Y180
Y181
Y182
Y183
Y184
Y185
Y186
Y187
Y188
Y189
Y190
Y191
Y192
Y193
Y194
Y195
Y196
Y197
Y198
Y199
Y200
Y201
Y202
Y203
Y204
Y205
Y206
Y207
Y208
Y209
Y210
Y211
Y212
Y213
Y214
Y215
Y216
Y217
Y218
Y219
Y220
Y234
Y235
-1780.70
-1813.70
-1846.70
-1879.70
-1912.70
-1945.70
-1978.70
-2011.70
-2044.70
-2077.70
-2110.70
-2143.70
-2176.70
-2209.70
-2242.70
-2275.70
-2308.70
-2341.70
-2374.70
-2407.70
-2440.70
-2473.70
-2506.70
-2539.70
-2572.70
-2605.70
-2638.70
-2671.70
-2704.70
-2737.70
-2770.70
-2803.70
-2836.70
-2869.70
-2902.70
-2935.70
-2968.70
-3001.70
-3034.70
-3067.70
-3100.70
-3133.70
-3166.70
-3199.70
-3232.70
-3265.70
-3298.70
-3331.70
-3793.70
-3826.70
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
2008/05/05
ST8024S
273
274
275
276
277
278
279
280
281
282
283
12.1
Y223
Y224
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y233
-3430.70
-3463.70
-3496.70
-3529.70
-3562.70
-3595.70
-3628.70
-3661.70
-3694.70
-3727.70
-3760.70
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
286
287
288
289
290
291
292
293
294
295
Gold Bump Size
Pad No.
X
1, 43
112.00
2, 3, 4, 5, 39, 40, 41, 42
112.00
44, 295
87.00
6, 38
87.00
7, 37
99.00
8, 9, 35, 36
81.30
10
84.10
11
80.70
12, 13, 15~20, 25~28, 30~34
88.70
14, 29
100.20
21
43.30
22
52.85
23, 24
34.65
45~294
18.00
Wafer thickness = 480±20um, Bump pad height = 15um, strength=30g
Ver 0.39
-3859.70
-3892.70
-3925.70
-3958.70
-3991.70
-4024.70
-4057.70
-4090.70
-4123.70
-4192.50
Y236
Y237
Y238
Y239
Y240
DUMMY
DUMMY
DUMMY
DUMMY
V0L
Page 25/27
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
350.00
2
Y
18.00
51.00
122.00
112.00
42.40
42.40
42.90
42.40
42.40
42.40
44.40
37.85
57.75
122.00
Area (um )
2016.0000
5712.0000
10614.0000
9744.0000
4197.6000
3447.1200
3620.7600
3421.6800
3760.8800
4248.4800
1922.5200
2000.3725
2001.0375
2196.0000
2008/05/05
ST8024S
13.
APPLICATION NOTE(REFERENCE ONLY)
13.1 Adjust V1 and V4 voltage to keep the V0-V1 = V4-VSS relation to get better display quality. The
(V0-V1)-(V4-VSS) value had better less than 100mV.
13.2 Add 0.1uF high frequency by-pass capacitor to filter the noise on V0~V4 to VSS.
13.3 When OP follower circuit is used, please be sure the OP power is higher than V0 at least 1.5V.
13.4 EIO1 and EIO2 is enable pin for driver, please pay attention to the distance to avoid noise when
cascade function is used. Two chip connecting distance is as shorter as better.
Ver 0.39
Page 26/27
2008/05/05
ST8024S
14.
REVISION
REVISION
0.10
0.20
0.30
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
0.39
DESCRIPTION
First release
Add LGND definition, and re-define the pin function
Modify suggestion resistor value for V0.
Add alignment mark data, Add LCD Panel Layout Example
Modify bond pad height to 18um
Modify bump pad height to 15um and add wafer thickness.
Modify all Vss for logic setting pins to LGND
Modify description of LGND
Change Sitronix logo and modify description of LGND for
COM mode
Modify pad define and size for pad No.6 and No.38.
Modify Chip size and thickness with scribe line
Modify “ Output resistance” test condition
Modify V0 Max. voltage in “ RECOMMENDED OPERATING
CONDITIONS” and “ ABSOLUTE MAXIMUM RATINGS”
Modify the Max. V0 voltage to 40V for test condition
Modify V0 Max. voltage in feature
Modify all the data about absolute max voltage and recommend max
voltage
Modify the ITO resistor value suggestion
Add application note
PAGE
1-25
1-25
DATE
2005/9/12
2005/11/22
21
2006/5/22
24
1-25
6-8
2006/6/7
2006/7/21
2006/7/21
1-25
2006/7/21
21-24
2006/7/24
16,22,24
2006/10/26
2,15-18
2007/1/3
2,16-18
2007/5/25
21,26
2008/5/05
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without
permission from Sitronix.
Ver 0.39
Page 27/27
2008/05/05