KT8555 TIME SLOT ASSIGNMENT CIRCUIT INTRODUCTION 20-CERDIP The KT8555 is a per channel Time Slot Assignment Circuit (TSAC) that produces 8-bit receive and transmit time slots for four 1 CHIP CODEC. Each frame synchronization pulse may be independently assigned to a time slot in a frame of up to 84 time slots. FEATURES l l l l l l l l Single, 5V operation Low power consumption: 5mW Controls four 1 CHIP CODEC Independent transmit and receive frame syncs enables channel unidirectional mode Up to 64 time slots per frame Compatible with KT8554/7 CODECs TTL and CMOS compatible ORDERING INFORMATION Device Package Operating Temperature KT8555J 20-CERDIP - 20°C ~ + 125°C PIN CONFIGURATION FSX1 1 20 VCC FSR1 2 19 FSR2 FSX0 3 18 FSX2 FSR0 4 TSX 5 16 FSX3 DC 6 15 CH0 CLKC 7 14 CH1 CS 8 13 RSYC/CH2 MODE 9 12 XSYC KT8555 GND 10 17 FSR3 11 BCLK Fig. 1 KT8555 TIME SLOT ASSIGNMENT CIRCUIT PIN DESCRIPTION Pin No Symbol Description 3 FSX0 A frame sync output which is normally low, and goes active-high for 8 cycles of 1 FSX1 BCLK when a valid transmit time slot assignment is made. 18 FSX2 16 FSX3 4 FSR0 A frame sync output which is normally low, and goes active-high for 8 cycles of 2 FSR1 BCLK when a valid receive time slot assignment is made. 19 FSR2 17 FSR3 5 TSX This pin pulls low during any active transmit time slot. (N-channel open drain) 6 DC The input for an 8 bit serial control word. X is the first bit clocked in. 7 CLKC 8 CS 9 MODE The clock input for the control interface. The active-low chip select for the control interface. Mode 1 = Open or VCC Mode 2 = Gnd 10 GND Ground 11 BCLK The bit clock input (2.048 MHz) 12 XSYC The transmit TSO sync pulse input. Must be synchronous with BCLK. The transmit time slot 0 sync pulse input. Must be synchronous with BCLK. 13 RSYC /CH2 In mode 1 this input is the receive time slot 0 sync pulse, RSYC, which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word. 14 CH1 The input for the NSB (next significant bit) of the channel select word. 15 CH0 The input for the LSB (last significant bit) of the channel select word, which defines the frame sync output affected by the following control word. 20 VCC Power supply pin. 5V ±5% ABSOLUTE MAXIMUM RATINGS Characteristic Positive Supply Voltage (Ta = 25°C) Symbol Value Unit VCC 7.0 V Input Voltage VI VCC + 0.3 ~ - 0.3 V Output Voltage VO VCC + 0.3 ~ - 0.3 V Operating Temperature Range T OPR - 25 ~ 125 °C Storage Temperature Range T STG - 65 ~ 150 °C Lead Temperature (Soldering, 10 secs) T LEAD 300 °C KT8555 TIME SLOT ASSIGNMENT CIRCUIT ELECTRICAL CHARACTERISTICS Characteristic (Unless otherwise noted; VCC = 5.0V ±5%, Ta = 0°C ~70°C) Symbol Operating Current ICC Input Voltage High VIH Input Voltage Low VIL Input Current 1 II1 Input Current 2 All Inputs Except Mode, VIL<VIN<VIH Mode, VIN = 0V Max Unit 1 1.5 mA tR (CK) tF(CK) V -1 0.7 V 1 µA µA -100 FSX and FSR Outputs, IOH = 3mA VOL Rise and Fall Time of Clock Typ 2.0 VOH Output Voltage Low Min BCLK = 2.048MHz, all outputs open II2 Output Voltage High Test Conditions 2.4 V FSX and FSR Outputs, IOL = 3mA 0.4 V TSX output, IOL = 3mA 0.4 V BCLK, CLKC 50 nS Delay to TSX Low tD (TSX L) CL = 50pF 140 nS Delay to TSX High tD (TSX H) RL = 1KΩ 100 nS 30 to VCC Hold Time from BCLK to Frame Sync tH (BFS) 50 nS Set-Up Time from Frame Sync to BLCK tH (FSB) 30 nS Delay Time from BLCK Low to FXX/R 0-3 tD High or Low CL = 50pF 50 nS Hold Time from Channel Select to CLKC tH (CSC) 50 nS Set-Up Time from Channel Select to CLKC tSU (CSC) 30 nS Period of Clock tCK BCLK, CLKC 240 nS tW (CKH) BCLK, CLKC 50 nS Width of Clock Low tW (CLK) BCLK, CLKC 50 nS Set-Up Time from DC to CLKC tSU (Dc C) 30 nS Hold Time from CLKC to DC tH (CDc) 50 nS Set-Up Time from CS to CLKC tSU (CC) 30 nS Hold Time from CLKC to CS tH (CC) 100 nS Width of Clock High TIMING DIAGRAM tHCD tW(CKH) tW(CKL) CONTROL INTERFACE tH(CC) CLK C tR(CK) tH(CC) tSU(CC) tF(CK) CS tSU(CC) tSU(CSC) CH0, CH1 AND CH2 tH(CSC) tSU(DcC) 1 DC 2 3 4 5 tWCH 7 8 OUTPUT tDT(SxL) tSU(FSB) 1 BCLK 2 tFS 3 4 5 6 7 8 tW(CKL) tH(BFS) tRS 6 tF(CK) tR(CK) tD XSYC OR RSY C tD FS X OR FS R tD(TSxH) MIN tD(TSxH) MAX TS X KT8555 TIME SLOT ASSIGNMENT CIRCUIT APPLICATION INFORMATION OPERATING CONTROL MODE 1 The KT8555 is a control interface which requires an 8 bit serial control word. Either one of the frame sync output group, FSX0 to FXX3 or FSR0 to FSR3, affected by the control word is defined by the two bits, X and R. Time slot selected from 0 to 63 is specified. A frame sync output is highly active for one time slot which is equivalent to 8 cycles of BCLK. Up to 64 time slots are allowed to form a frame. There are two operational mode. In mode 1, each channel of transmit and receive direction has different time slot assigned. This mode can be selected by either leaving pin 9 (MODE) opened or connecting it with VCC. In such a case, pin 13 is RSYC input defining the start of each receive frame while four output, FSR0 to FSR3, are assigned with respect to RSYC. On the other hand, start of each transmit frame is defined by XSYC input by which output FSX0 to FSX3, are assigned. XSYC and RSYC can be phase related. Channels from 0-3 are selected by the input CH0 and CH1 (refer to the table 1). X R T5 T4 T3 T2 T1 T0 CH1 0 0 1 1 X is the first bit clocked into DC input CH0 0 1 0 1 Channel Selected Assign to FSX0 and/or FSR0 Assign to FSX1 and/or FSR1 Assign to FSX2 and/or FSR2 Assign to FSX3 and/or FSR3 CONTROL DATA FORMAT T5 0 0 0 T4 0 0 0 T3 0 0 0 T2 0 0 0 T1 0 0 1 T1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 Time Slot 0 1 2 . . . 30 31 32 33 . . . 63 X R 0 0 Assign time slot to both selected FSX and FSR Action 0 1 Assign time slot to selected FSX only 1 0 Assign time slot to selected FSR only 1 1 Disable both selected FSX and FSR TABLE 1. OPERATING CONTROL MODE 1 OPERATING CONTROL MODE 2 In mode 2, all 8 frame sync outputs can be assigned with respect to XSYC input. The mode 2, selected by connecting pin 9 (MODE) to GND, enables the KT8555 TSAC suitable for an 8-channel unidirectional controller and for a system where both transmit and receive direction of each channel have same time slot assigned. For instance, FSX and FSR input of 1 CHIP CODEC are hard wired together. The channel assigned has its channel selected by CH0, CH1 and CH2 (refer to table 2). CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 Channel Selected Assign to FSX0 Assign to FSX1 Assign to FSX2 Assign to FSX3 Assign to FSR0 Assign to FSR1 Assign to FSR2 Assign to FSR3 X R 0 0 Assign time slot to selected output Action 0 1 Assign time slot to selected output 1 0 Assign time slot to selected output 1 1 Disable both selected output TABLE 2. OPERATING CONTROL MODE 2 KT8555 TIME SLOT ASSIGNMENT CIRCUIT APPLICATION CIRCUIT The KT8555 TSAC combined with any kind of 1 CHIP CODEC from KT8554/7 series can obtain data timing as illustrated in Fig. 3. Even though FSX output goes high before BCLK gets high, the DX output of the 1 CHIP CODEC remains in the TRI-STATE mode until both outputs are high. The eight bit period is shortened to avoid PCM data clash at PCM prehighway. Alternatively, full 8 bits can be obtained by inverting the BCLK to the 1 CHIP CODEC devices, thereby rising edges of BCLK and FSX/R are aligned. Fig. 4 is typical timing of the control data interface. Fig. 5 is the typical application circuit at operating control mode 2. 1 BCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 XSYC FS X 1 FS X 2 DX 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 TS X Fig. 3 Transmit Data Timing CLKC CH0, CH1 CS DC X R T5 T4 T3 T2 T1 T0 Fig. 4 Control Data Timing X R T5 T4 TIME SLOT ASSIGNMENT CIRCUIT KT8555 +5V 0.1µF 13 TS X 7 CLKSEL 10 BCLKX 9 MCLKX KT8554/57 FSX1 FSX0 1 3 1 CHIP CODEC #3 1 CHIP CODEC #2 1 CHIP CODEC #1 VFXI+ 16 14 VFXI- 15 GSX 8 8 3 11 PDN VFRO DX FSX 6 DR FSR 15 CH0 FSX2 18 1 CHIP CODEC #4 5 12 CH0 14 CH1 FSX3 16 1 CHIP CODEC #5 1 CHIP CODEC # 0 CH1 13 CH2 4 1 CHIP CODEC #6 T4 T3 0 0 0 . . . . 1 1 T2 0 0 1 . . . . 1 1 T1 0 1 0 . . . . 0 1 T0 VFXI- 15 VFXI+ 16 Fig. 5 Digital interface on a typical subscriber linecard 10 9 GND MODE CH2 8 CS FSR0 2 7 CLKSEL Time Slot 0 0 0 . . . . 1 1 respectively also available. 20 VCC CS 7 CLKC FSR1 KT8555 CLKC FSR2 19 13 TSX 11 PDN Action Timesolt assign 14 5 FSR Time slot assign DX VFRO 3 R 0 Time slot assign GSX 12 FSX 6 DR 0 KT8554/57 11 BCLK LSB T1 T0 12 XSYC T2 BCLK T3 XSYC T4 FSR3 17 T5 6 DC R DC NOTE 1 : Dc Format MSB X 9 MCLK X X 0 1 10 BCLKX 0 Time slot assign disable NOTE 2 : X, R action status 1 1 0 0 0 . . . . 1 1 1 CHIP CODEC #7 NOTE 4 : Time slot assign status 1 Action Normal operation Time slot assign disable NOTE 3 : T5 action status T5 0 1 0 1 2 . . . . 62 63 NOTE 5 : Different time slot assign for RX and TX