TDA9103 DEFLECTION PROCESSOR FOR MULTISYNC MONITOR .. .. .. .. .. .. . . . .. . . . .. HORIZONTAL DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY SELF-ADAPTIVE (EX : 30 TO 85kHz) X-RAY PROTECTION INPUT DC ADJUSTABLE DUTY-CYCLE INTERNAL 1st PLL LOCK/UNLOCK IDENTIFICATION 4 OUTPUTS FOR S-CORRECTION WIDE RANGE DC CONTROLLED H-POSITION T his IC, combined with TDA9205 (RG B preamp), STV9420/21 or 22 (O.S.D. processor), ST7271 (micro controller) and TDA8172 (vertical booster), allows to realize very simple and high quality multimodes or multisync monitors. ON/OFF SWITCH (FOR PWR MANAGEMENT) TWO H-DRIVE POLARITIES VERTICAL VERTICAL RAMP GENERATOR 50 TO 150Hz AGC LOOP DC CONTROLLED V-AMP, V-POS, S-AMP AND SCENTERING ON/OFF SWITCH SHRINK42 (Plastic Package) ORDER CODE : TDA9103 B+ REGULATOR INTERNAL MAXIMUM CURRENT LIMITATION EWPCC VERTICAL PARABOLA GENERATOR WITH DC CONTROLLED KEYSTONE AND AMPLITUDE GENERAL ACCEPT POS. OR NEG. H AND V SYNC POLARITIES SEPARATED H AND V TTL INPUT SAFETY BLANKING OUTPUT DESCRIPTION The TDA9103 is a monolithic integrated circuit assembled in a 42 pins shrunk dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimodes or multisync monitors. As can be seen in the block diagram, the TDA9103 includes the following functions : - Positive or Negative sync polarities, - Auto-sync horizontal processing, - H-PLL lock/unlock identification, - Auto-sync Vertical processing, - East/West signal processing block, - B+ controller, - Safety blanking output. May 1996 PIN CONNECTIONS PLL2C 1 42 ISENSE H-DUTY 2 41 COMP HFLY 3 40 REGIN HGND 4 39 B+-ADJ HREF 5 38 KEYST S4 6 37 E/W-AMP S3 7 36 E/WOUT S2 8 35 PLL1INHIB S1 9 34 VSYNC C0 10 33 V-POS R0 11 32 VDCOUT PLL1F 12 31 V-AMP HLOCK-CAP 13 30 VOUT FH-MIN 14 29 VS-CENT H-POS 15 28 VS-AMP XRAY-IN 16 27 VCAP HSYNC 17 26 VREF VCC 18 25 VAGCCAP GND 19 24 VGND H-OUTEM 20 23 SBLKOUT H-OUTCOL 21 22 B+OUT 9103-01.AI INTERNAL PWM GENERATOR FOR B+ CURRENT MODE STEP-UP CONVERTER DC ADJUSTABLE B+ VOLTAGE OUTPUT PULSES SYNCHRONISED ON HORIZONTAL FREQUENCY 1/27 TDA9103 PIN-OUT DESCRIPTION Pin N° 1 Name PLL2C Function 2 H-DUTY DC Control of Horizontal Drive Output Pulse Duty-cycle. If this pin is grounded, the horizontal and vertical outputs are inhibited. By connecting a capacitor on this pin a soft-start function may be realized on h-drive output. 3 4 5 H-FLY H-GND H-REF Horizontal Flyback Input (positive Polarity) Horizontal Section Ground. Must be connected only to components related to H blocks. Horizontal Section Reference Voltage. Must be filtered by capacitor to Pin 4 6 7 8 S4 S3 S2 Hor S-CAP Switching Hor S-CAP Switching Hor S-CAP Switching 9 10 11 S1 C0 R0 Hor S-CAP Switching Horizontal Oscillator Capacitor. To be connected to Pin 4. Horizontal Oscillator Resistor. To be connected to Pin 4. 12 PLL1F 13 HLOCK-CAP 14 FH-MIN Second PLL Loop Filter First PLL Loop Filter. To be connected to Pin 4. First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the frequency change detected on Pin13. When frequency is changing, a blanking pulse is generated on Pin 23, the duration of this pulse is proportionnal to the capacitor on Pin 13. To be connected to Pin 4. DC Control for Free Running Frequency Setting. Comming from DAC output or DC voltage generated by a resistor bridge connected between Pin 5 and 4. DC Control for Horizontal Centering 15 H-POS 16 XRAY-IN X-RAY Protection Input (with internal latch function) 17 18 19 H-SYNC VCC GND TTL Horizontal Sync Input Supply Voltage (12V Typical) Ground 20 21 22 H-OUTEM H-OUTCOL B+ OUT 23 SBLK OUT 24 25 VGND VAGCCAP 26 27 28 VREF VCAP VS-AMP Vertical Section Reference Voltage Vertical Sawtooth Generator Capacitor DC Control of Vertical S Shape Amplitude 29 30 31 VS-CENT VOUT V-AMP DC Control of Vertical S Centering Vertical Ramp Output (with frequency independant amplitude and S-correction) DC Control of Vertical Amplitude Adjustment 32 VDCOUT 33 34 35 V-POS VSYNC PLL1INHIB DC Control of Vertical Position Adjustment Vertical TTL Sync Input TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input signal) 36 37 38 E/WOUT E/W-AMP KEYST East/West Pincushion Correction Parabola Output DC Control of East/West Pincushion Correction Amplitude DC Control of Keystone Correction 39 40 41 B+ ADJ REGIN COMP 42 ISENSE 2/27 Horizontal Drive Output (emiter of internal transistor). See description on pages 15-16. Horizontal Drive Output (open collector of internal transistor). See description on pages 15-16. B+ PWM Regulator Output Safety Blanking Output. Activated during frequency changes, when X-RAY input is triggered or when VS is too low. Vertical Section Signal Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator DC Control of B+ Adjustment Regulation Input of B+ Control Loop B+ Error Amplifier Output for Frequency Compensation and Gain Setting Sensing of External B+ Switching Transistor Emiter Current 9103-01.TBL Vertical Position Reference Voltage Output Temperature Matched with V-AMP Output TDA9103 HS YNC 17 INPUT INTERFACE PLL1INHIB H-POS PLL1F R0 C0 FH-MIN HLOCK-CAP HFLY PLL2C H-DUTY H-OUTEM H-OUTCOL S4 S3 S2 S1 BLOCK DIAGRAM 35 15 12 11 10 14 13 3 1 2 20 21 6 7 8 9 1s t P HASE COMP 2nd P HASE COMP VCO P ULSE S HAPER OUTP UT BUFFER H FREQUENCY 23 S BLKOUT LOCK DETECT 39 B+-ADJ XRAY-IN 16 HREF VREF 5 42 IS ENSE H-VREF HGND 4 VREF 26 VGND 24 V-VREF VCC R EA SAFETY P ROCES S OR BANDGAP 22 B+OUT S Outputs Inhibition 41 COMP 40 REGIN P ARABOLA GENERATOR 28 33 31 VS-CENT VS-AMP V-POS V-AMP 30 32 38 37 TDA9103 9103-02.EPS 29 E/W-AMP 25 KEYST 27 VOUT 18 VDCOUT 19 VAGCCAP S CORRECTION VCAP VERTICAL OS CILLATOR VCC INPUT INTERFACE GND VSYNC 34 36 E/WOUT 3/27 TDA9103 QUICK REFERENCE DATA Horizontal Frequency Range Autosynch Frequency Range (for Given R0, C0) ± Hor Sync Polarity Input Compatibility with Composite Sync on H-SYNC Input Value Unit 15 to 150 kHz 1 to 3.7 FH YES YES (1) Lock/Unlock Identification on 1st PLL YES DC Control for H-Position YES X-RAY Protection YES Hor DUTY Adjust YES Stand-by Function YES Hor S-CAP Switching Control YES Two Polarities H-Drive Outputs YES Supply Voltage Monitoring YES PLL1 Inhibition Possibility YES Safety Blanking Output YES Vertical Frequency Range 35 to 200 Hz Vertical Autosync Range (for a Given Capacitor Value) 50 to 150 Hz Vertical -S- Correction YES Vertical -C- Correction YES Vertical Amplitude Adjustment YES Vertical Position Adjustment YES Automatic B+ Adjustment Control Loop YES B+ Adjustment YES East/West Parabola Output YES PCC (Pin Cushion Correction) Amplitude Adjustment YES Keystone Adjustment YES Reference Voltage YES (2) Mode Detection NO Dynamic Focus NO Blanking Output NO Notes : 1. See application diagram. 2. One for Horizontal section and one for Vertical section. 4/27 9103-02.TBL Parameter TDA9103 ABSOLUTE MAX RATING Parameter Value Unit VCC Supply Voltage (Pin 18) 13.5 V VIN Max Voltage on 8 1.8 6 8 8 5.5 V 2 300 kV V -40, +150 °C 150 °C 0, +70 °C VESD Tstg Tj Toper Pins 2, 14, 15, 28, 29, 31, 33, 37, 38, 39 Pin 3 Pins 17, 34 Pin 40 Pin 42 Pin 16 ESD Succeptibility Human Body Model, 100pF Discharge through 1.5kΩ EIAJ Norm, 200pF Discharge through 0Ω Storage Temperature Max Operating Junction Temperature Operating Temperature 9103-03.TBL Symbol Symbol Rth (j-a) Parameter Junction-Ambient Thermal Resistance Value Unit 65 °C/W Max. 9103-04.TBL THERMAL DATA HORIZONTAL SECTION Operating conditions Symbol Parameter Test conditions Min. Typ. Max. Unit VCO R0min Oscillator Resistor Min Value Pin 11 6 C0min Oscillator Capacitor Min Value Pin 10 390 Fmax Maximum Oscillator Frequency HsVR Horizontal Sync Input Voltage Range Pin 17 0 0.7 kΩ pF 150 kHz 5.5 V INPUT SECTION MinD Minimum Input Pulses Duration Pin 17 Mduty Maximum Input Signal Duty Cycle Pin 17 µS 25 % 2 mA mA I3m Maximum Input Peak Current on Pin 3 IS1 to IS4 Maximum Current on S1 to S4 Outputs Pins 6 to 9 0.5 VS1 to VS4 Maximum Voltage on S1 to S4 Outputs Pins 6 to 9 VCC V HOI1 Horizontal Drive Output Max Current Pin 20, sourced current 20 mA HOI2 Horizontal Drive Output Max Current Pin 21, sunk current 20 mA 6 V DC CONTROL VOLTAGES DCadj DC Voltage Range on DC Controls VREF-H = 8V, Pins 2-14-15 2 5/27 9103-05.TBL OUTPUT SECTION TDA9103 Electrical Characteristics (VCC = 12V, Tamb = 25°C) Symbol Parameter Test conditions Min. Typ. Max. Unit 10.8 12 13.2 V 40 60 mA 8 8.6 V 5 mA 8.6 V 5 mA 0.8 V V SUPPLY AND REFERENCE VOLTAGES VCC Supply Voltage Pin 18 ICC Supply Current Pin 18, See Figure 1 VREF-H Reference Voltage for Horizontal Section Pin 5, I = 2mA IREF-H Max Sourced Current on VREF-H Pin 5 VREF-V Reference Voltage for Vertical Section Pin 26, I = 2mA IREF-V Max Sourced Current on VREF-V Pin 26 7.4 7.4 8 INPUT SECTION/PLL1 VINTH VVCO VCOG Hph Hor Input Threshold Voltage Pin 17 Low level voltage High level voltage VCO Control Voltage Range VREF-H = 8V, Pin 12 VCO Gain, dF/dV Pin 12 R0 = 6.49kΩ, C0 = 680pF 2 1.6 6.2 15 V kHz/V ±12.5 % ±20 % Horizontal Phase Adj Range (Pin 15) % of Hor period FFadj Free Running Frequency Adj Range (Pin 14) Without H-sync Signal S1th VCO Input Voltage for S1 Switching Pin 12 voltage, V REF-H = 8V 1.85 2 2.25 S2th VCO Input Voltage for S2 Switching Pin 12 voltage, V REF-H = 8V 2.25 2.4 2.65 V S3th VCO Input Voltage for S3 Switching Pin 12 voltage, V REF-H = 8V 2.9 3 3.3 V S4th VCO Input Voltage for S4 Switching Pin 12 voltage, V REF-H = 8V 3.5 3.7 3.9 V Free Running Frequency V14 = VREF/2 R0 = 6.49kΩ C0 = 680pF 23.5 25 27.5 kHz Low Level Output Voltage on S1 to S4 Outputs Pins 6 to 9, I = 0.5mA 0.2 0.4 V PLL1 Capture Range (F0 = 27kHz) Fh Min Fh Max See conditions on Figure 1 F0 VS1D to VS4D CR PLLinh PLL 1 Inhibition (Pin 35) PLL ON PLL OFF V kHz 28 94 V V35 V35 0.8 2 SECOND PLL AND HORIZONTAL OUTPUT SECTION Hjit Flyback Input Threshold Voltage Pin 3 0.65 Horizontal Jitter HDmin HDmin Minimum Hor Drive Output Duty-cycle Maximum Hor Drive Output Duty-cycle Pin 20 or 21, V2 = 2V Pin 20 or 21, V2 = 6V HDvd Horizontal Drive Low Level Output Voltage V21-V20, Iout = 20mA, Pin 20 to GND HDem Horizontal Drive High Level Output Voltage (output on Pin 20) Pin 21 to VCC, IOUT = 20mA XRAYth X-RAY Protection Input Threshold Voltage Pin 16 ISblkO Maximum Output Current on Safety Blanking Output I23 VSblkO 45 9.5 0.75 V 100 ppm 30 50 35 % % 1.1 1.7 V 10 1.6 V 1.8 V 10 mA 0.5 V Low-Level Voltage on Safety Blanking Output V23 with I23 = 10mA 0.25 Vphi2 Internal Clamping Voltage on 2nd PLL Loop Filter Output (Pin 1) Vmin Vmax 1.6 3.2 V V VOFF Pin 2 Threshold Voltage to Stop H-out, V-out B+out and to Activate S-BLK.OFF Mode when V2 < VOFF V2 1 V 6/27 9103-06.TBL FBth TDA9103 Symbol EAOI FeedRes Parameter Test conditions Min. Maximum Error Amplifier Output Current Sourced by Pin 41 Sunk by Pin 41 Minimum Feedback Resistor Resistor between Pins 40 and 41 5 Test conditions Min. Typ. Max. Unit 0.5 2 mA mA kΩ 9103-07.TBL B+ SECTION Operating Conditions Electrical Characteristics (VCC = 12V, Tamb = 25°C) OLG Parameter Typ. Max. Unit Error Amplifier Open Loop Gain At low frequency (see Note 1) 85 dB Unity Gain Bandwidth (see Note 1) 6 MHz Regulation Input Bias Current Current sourced by Pin 40 (PNP base) 0.2 µA EAOI Maximum Guaranted Error Amplifier Output Current Current sourced by Pin 41 Current sunk by Pin 41 CSG Current Sense Input Voltage Gain Pin 42 3 Max Curent Sense Input Threshold Voltage Pin 42 1.2 V Current Sense Input Bias Current Current sunk by Pin 42 (NPN base) 1 µA Tonmax Maximum External Power Transistor on Time % of H-period @ f0 = 27kHz 75 % B+OSV B+ Output Low Level Saturation Voltage V22 with I22 = 10mA 0.25 V Internal Reference Voltage On error amp (+) input for V39 = 4V 4.9 V Internal Reference Voltage Adjustment Range 2V < V39 < 6V ±14 % UGBW IRI MCEth ISI IVREF VREFADJ 0.5 2 mA mA 9103-08.TBL Symbol EAST WEST PARABOLA GENERATOR Electrical Characteristics (VCC = 12V, Tamb = 25°C) Vsym Kadj Paramp Parameter Parabola Symetry Adjustment Capability (for Keystone Adjustment ; with Pin 38) Test conditions Min. Typ. See Figure 2 ; internal voltage V38 = 2V V38 = 4V V38 = 6V 3.2 3.5 3.8 Keystone Adjustment Capability B/A ratio A/B ratio See Figure 2 ; V37 = 4V V38 = 2V V38 = 6V 2.3 2.0 Parabola Amplitude Adjustment Capability Maximum Amplitude on Pin 36 Maximum Ratio between Max and Min V38 = 4.3V, V28 = 2V V37 = 2V 2V < V37 < 6V Max. Unit V V 3.3 2.4 3.8 3 4.3 7/27 9103-09.TBL Symbol TDA9103 Symbol VSVR Parameter Vertical Sync Input Voltage Range Test conditions On Pin 34 Min. 0 Typ. Max. 5.5 Unit V Min. Typ. 2 Max. Unit µA 9103-10.TBL VERTICAL SECTION Operating Conditions Electrical Characteristics (VCC = 12V, Tamb = 25°C) IBIASN VSth VSBI VRB VRT VRTF IR27 VSW VSmDut VSTD VFRF ASFR Parameter Pin 23-28-29 Bias Current (Current Sourced by PNP Base) Pin 31 Bias Current (Current Sunk by NPN Base) Vertical Sync Input Threshold Voltage Vertical Sync Input Bias Current (Current Sourced by PNP Base) Voltage at Ramp Bottom Point Voltage at Ramp Top Point (with Sync) Voltage at Ramp Top Point (without Sync) Output Current Range on Pin 27 during Ramp Charging Time. Current to Charge Capacitor between Pin 27 and Ground Minimum Vertical Sync Pulse Width Vertical Sync Input Maximum Duty-cycle Vertical Sawtooth Discharge Time Duration Vertical Free Running Frequency (V28 = 2V) RATD AUTO-SYNC Frequency Range (see Note 3) Ramp Amplitude Thermal Drift RAFD Ramp Amplitude Drift Versus Frequency Rlin Rload Vpos IVPOS Vor VOUTDC V0I dVS Ccorr Ramp Linearity on Pin 27 ∆I27/I 27 Minimum Load on Pin 25 for less than 1% Vertical Amplitude Drift Vertical Position Adjustment Range Voltage on Pin 32 Max Current on Vertical Position Control Output (Pin 32) Vertical Output Voltage Range (on Pin 30) (Peak to Peak Voltage on Pin 30) DC Voltage on Vertical Output (Pin30) Vertical Output Maximum Output Current Max Vertical S-Correction Amplitude (V28 = 2V Inhibits S-CORR; V28 = 6V gives Maximum S-CORR) (see Figure 3) C-Correction Adjustment Range Voltage on Pin 27 for Maximum Slope on the Ramp (with S-Correction) (see Figure 4) Test conditions For V23-28-29 = 2V For V31 = 6V Pin 34; High-level Low-level V34 = 0.8V On Pin 27 On Pin 27 On Pin 27 V28 = 2V (Note 2), 2V < V27 < 5V Min current Max current Pin 34 Pin 34 On Pin 27, with 150nF cap Measured on Pin 27 Cosc (Pin27) = 150nF With C27 = 150nF ±5% µA 0.5 2 1 V V µA 2/8 5/8 VRT-0.1 VREF-V VREF-V V 0.8 100 5 15 135 20 15 85 100 50 On Pin 30 (see Note 1) (0°C < Tamb < 70°C) V31 = 6V, C27 = 150nF 50Hz < F < 120Hz V28 = 2V, V25 = 4.3V 2.5V < V27 < 4.5V 150 V31 = 2V V31 = 4V V31 = 6V See Note 4 On Pin 30 ∆V/V30pp at T/4 ∆V/V30pp at 3T/4 V29 = 2V V29 = 4V V29 = 6V 3.65 3.75 Hz 100 ppm/°C 200 ppm/Hz 0.5 % 50 V33 = 2V V33 = 4V V33 = 6V µA µA µS % µS Hz MΩ 3.2 3.5 3.8 ±2 3.3 V V V mA 2 3 4 7/16 ±5 -4 +4 2.2 V V V 3 3.5 4 VREF-V mA % % V V V Notes : 1. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization. 2. When 2V are applied on Pin 28 (Vertical S-Correction control), then the S-Correction is inhibited, consequently the sawtooth have a linear shape. 3. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 27 and with a constant ramp amplitude. 4. Typically 3.5V for Vertical reference voltage typical value (8V). 8/27 9103-11.TBL Symbol IBIASP 9103-54.EPS 2.2 µF 2.2 µF 34 24 26 4 5 16 17 18 12V S5 19 INPUT INTERFACE V-VREF H-VREF INPUT INTERFACE 35 15 12 150nF 1% 27 25 VCO 6.49kΩ 10 29 13 28 33 Outputs Inhibition SAFETY PROCESSOR VCC 3 31 2nd PHASE COMP 220nF LOCK DETECT 14 680pF 1% S CORRECTION 11 4.7 F 1.8kΩ 470nF 1% VERTICAL OSCILLATOR BANDGAP 1st PHASE COMP 10nF 30 1 2 32 PULSE SHAPER 22nF 21 4.7kΩ VREF 6 38 37 PARABOLA GENERATOR EA OUTPUT BUFFER 20 S6 12V 8 9 S R 15 kΩ 36 40 41 22 42 39 23 TDA9103 15 kΩ 15 kΩ 15 kΩ H FREQUENCY 7 12V 10k Ω 47kΩ 470pF 3.9k Ω 4.7k Ω 10kΩ 12V 12V TDA9103 Figure 1 : Testing Circuit 9/27 TDA9103 Figure 2 : Keystone Adjustment V36 A V38 = 2V B V38 = 4V V38 = 6V V27 9103-03.AI 3.8 3.5 3.2 Figure 3 : S Amplitude Adjustment V30 ∆V 0 T/4 T/2 3T/4 T ∆V increase when V28 increase. ∆V = 0 when V28 = 0. 9103-04.AI V30pp Figure 4 : C Correction Adjustment V27 4.0V 3.5V 0 10/27 T 9103-05.AI 3.0V TDA9103 OPERATING DESCRIPTION GENERAL CONSIDERATIONS Power Supply The input currents of the DC control inputs are typically very low (about a few µA). Depending on the internal structure of the inputs, the input currents can be positive or negative (sink or source). The typical value of the power supply voltage VCC is 12V. Perfect operation is obtained if VCC is maintained in the limits : 10.8V → 13.2V. In order to avoid erratic operation of the circuit during the transient phase of VCC switching on, or switching off, the value of VCC is monitored and the outputs of the circuit are inhibited if it is too low. In order to have a very good powersupplyrejection, the circuit is internally powered by several internal voltage references (The unique typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and one for the horizontal part. These voltage references can be used for the DC control voltages applied on the concerned pins by the way of potentiometers or digital to analog converters (DAC’s). Furthermore it is possible to filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the ”jitter” on vertical and horizontal output signals. HORIZONTAL PART Input section The horizontal input is designed to be sensitive to TTL signals typically comprised between 0 and 5V. The typical threshold of this input is 1.6V. This input stage uses an NPN differential stage and the input current is very low. Concerning the duty cycle of the input signal, the following signals may be applied to the circuit. Figure 6 Z T DC Control Adjustments The circuit has 10 adjustment capabilities : 3 for the horizontal part, 1 for the SMPS part, 2 for the E/W correction, 4 for the vertical part. The corresponding inputs of the circuit has to be driven with a DC voltage typically comprised between 2 and 6V for a value of the internal voltage reference of 8V. More precisely, the control voltages have to be maintained between VREF/4 and 3/4 ⋅ VREF. The application of control voltages outside this range is not dangerousfor the circuit but the good operation is not guaranted (except for Pin 2 : duty cycle adjusment. See outputs inhibition paragraph). 9103-07.AI Z Using internal integration, both signals are recognized on condition that Z/T ≤ 25%. Synchronisation occurs on the leading edge of the rectified signal. The minimum value of Z is 0.7µs. Figure 7 : Input Structure HSYNC 1.6V 9103-08.AI Example of Practical DC Control Voltage Generation VREF 10kΩ 22kΩ DC Control Voltage 10kΩ 9103-06.AI Figure 5 : PLL1 The PLL1 is composed of a phase comparator, an external filter and a Voltage Controlled Oscillator (VCO). The phase comparatoris a ”phase frequency” type, designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a ”charge pump”, composed of 2 current sources sink and source (I = 1mA typ.) 11/27 TDA9103 Figure 8 : Principle Diagram C Lockdet 13 Eini 35 Filter R0 C0 12 11 10 LOCKDET High E2 PLL INHIBITION CHARGE PUMP COMP1 Low Horizontal Adjust 15 PHASE ADJUST The dynamic behaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A ”CRC” filter is generally used. PLL1 is inhibited by applying a high level on Pin 35 (PLLinhib) which is a TTL compatible input. The inhibition results from the opening of a switch located between the charge pump and the filter (see Figure 8). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportionnal to the current in the resistor. typical thresholds of sawtooth are 1.6V and 6.4V. VCO OSC 3.2V 9103-09.AI INPUT INTERFACE Horizontal 17 Input The control voltage of the VCO is typically comprised between 1.6V and 6V. The theoretical frequency range of this VCO is in the ratio 1 → 3.75, but due to spread and thermal drift of external components and the circuit itself, the effective frequency range has to be smaller (e.g. 30kHz → 82kHz). Inthe absenceof synchronisationsignal the control voltage is equal to 1.6V typ. and the VCO oscillates on its lowest frequency (free frequency). The synchro frequencyhas to be always higher than the free frequency and a margin has to be taken. As an example for a synchro range from 30kHz to 82kHz, the suggested free frequency is 27kHz. To compensate for the spread of external components and of the circuit itself, the free frequency may be adjusted by a DC voltage on Pin 14 (Fmin adjust) (see Figure10 for details). Figure 9 9103-10.AI PLL1F 12 The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage adjustable between 2.4V and 4V (by Pin 15). So a ±45° phase adjustment is possible. Figure 10 : Details of VCO and Fhmin Adjustment FHMINADJ I0 14 a Loop 12 Filter 6.4V 2 RS FLIP FLOP I0 (0.8V < a < 1.2V) 4 I0 1.6V 2 11 10 R0 6.4V C0 1.6V 0 12/27 0.75T T 9103-58.EPS (1.6V < V12 < 6V) TDA9103 Figure 11 : Safety Functions Block Diagram V CC Checking V CC 30 - REF 30 + SMPS Output Inhibition XRAY Protection XRAY 30 S V CCoff 30 R H Output Inhibition Inhibition V Output Inhibition Q PLL-Unloocked 30 - 1V 30 + Flyback 30 - 0.7V 30 + Blanking 9103-21.AI H-duty Cycle 30 Figure 12 : LOCK/UNLOCK Block Diagram A 20kΩ H-Lock CAP 13 6.5V 220nF The TDA9103 also includes a LOCK/UNLOCK identification block which sense in real-time wheather the PLL is locked on the incomming horizontal sync signal or not. The resulting information is available on safety blanking output (Pin 23) where it is mixed with others information (see Figure 11). The block diagram of the LOCK/UNLOCK function is described in Figure 12. The NOR1 gate is receiving the phase comparator output pulses (which also drives the charge pump). When the PLL is locked, on point A there is a very small negative pulse (100ns) at each horizontal cycle, so after R-C filter, there is a high level on Pin 13 which force SBLK to high level (provided other inputs on NOR2 are also at low level). When the PLL is unlocked, the 100ns negative pulse on A becomesmuch larger and consequently the average level on Pin 13 will decrease. When it reaches 6.5V, point B goes to high level forcing NOR2 open collector output to ”0”. The status of Pin 13 is approximately the following : - Near 0V when there is no H-SYNC, - Between 0 and 4V with H-SYNC frequency differ- NOR2 B 23 SBLK OUT 9103-59.EPS NOR1 ent from VCO, - Between 4 and 8V when H-SYNC frequency = VCO frequency but not in phase, - Near to 8V when PLL is locked. It is important to notice that Pin 13 is not an output pin and must only be used for filtering purpose (see Figure 12). Figure 13 : PLL1 Timing Diagram H Osc Sawtooth 0.75T 0.25T 6.4V 2.4V<Vb<4V Vb 1.6V Phase REF1 H Synchro Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.4V and 4V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS. A ± 45° phase adjustment is possible. 13/27 9103-16.AI From Phase Comparator TDA9103 PLL2 Figure 14 : Dual PLL Block Diagram Eini 35 C Lockdet 13 Filter R0 C0 12 11 10 HFREQ LOCKDET High INPUT INTERFACE CHARGE PUMP COMP1 E2 Low Cap Adjust Rapcyc PH12 2 1 PHASE ADJUST High RAP CYC COMP2 14 Freq Adjust OSC 3.2V GENPULSE FLYBACK 3 Flyback E1 LOGI PWM BUFFER 21 SortCOLL 20 SortEM ±0.5mA (typ.) output current. The flyback input is composed of an NPN transistor. This input has to be current driven. The maximum recommanded input current is 2mA (see Figure 16). The PLL2 ensures the coincidence between the leading edge of the shaped flyback signal and a phase reference signal obtained by comparison of the sawtooth of the VCO and a constant DC voltage (3.2V) (see Figure 15). Figure 15 : PLL2 Timing Diagram 0.75T FAJUST VB PWM H Osc Sawtooth VCO E2 CHARGE PUMP Low VA PLL INHIBITION Horizontal Adjust 15 9103-15.AI Horizontal 17 Input Figure 16 : Flyback Input Electrical Diagram 0.25T 400Ω HFLY 3 6.4V Q1 20kΩ 1.6V GND 0V Flyback Shapped Flyback Phase REF2 H Drive Ts The phase comparator of PLL2 is similar to the one of PLL1, it is followed by a charge pump with a 14/27 9103-57.AI Duty Cycle Phase REF2 is obtained by comparison between the sawtooth and a 3.2V (constant). The PLL2 ensures the exact coincidence between the signals phase REF2 and the flyback signal. The duty cycle of H-drive is adjustable between 30% and 50%. Output Section The H-drive signal is transmitted to the output through a shaping block ensuring a duty cycle adjustable from 30% to 50%. In order to ensure a reliable operation of the scanning power part, the output is inhibited in the following circumstances : - VCC too low. - Xray protection activated. - During the flyback. - Output voluntarily inhibited. The output stage is composed of a Darlington NPN bipolar transistor. Both the collector and the emitter are accessible. 9103-11.AI 3.2V TDA9103 Figure 17 : Output stage simplified diagram, showing the two possibilities of connection The reset of this protection is obtained by VCC switch off. S Correction. S Outputs 21 VCC In the case where the ”S correction” of the horizontal scanning is performed using capacitors, it is necessary to switch capacitors when the frequency changes. For this the outputs S1, 2, 3 and 4 (Pins 9, 8, 7 and 16) give an indication about the horizontalfrequency by monitoring thecontrolvoltage of the VCO (Pin 12). H-DRIVE 20 The switching of the S outputs occurs for the following value of the control voltage. V CC 21 VCC 20 The output Darlington is in off-state when the power scanning transistor is also in off-state. The maximum output current is 20mA, and the correspondingvoltage drop of the output darlington is 1.1V typically. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be designed between the circuit and the power transistor which can be of bipolar or MOS type. Outputs inhibition : the application of a voltage lower than 1V (typ.) on Pin 2 (duty cycle adjust) inhibits the horizontal, vertical and SMPS outputs. This is not memorised. X-ray protection : the activation of the X-ray protection is obtained by application of a high level on the X-ray input (>1.6V). Consequences of X-ray protection are : - Inhibition of H drive output. - Inhibition of SPMS output. - Activation of safety blanking output. 9103-12.AI / 9103-13.AI H-DRIVE S1 2V S2 2.4V S3 3V S4 3.7V The use of comparators with hysteresis avoids erratic switching of the Sout outputs if the control voltage of the VCO remains very close to a switching reference level. SMPS This unit generates the supply voltage for the horizontal scanning system. This supply voltage is approximately proportional to the H frequency in order to keep the scanning amplitude constant when the frequency changes. More precisely the amplitude regulation is obtained by detecting and regulating the ”flyback” amplitude or EHT value. The power supply is a step-up converter and it uses the ”current-mode” regulation principle. The power supply works in synchronism with the horizontal scanning. The switching power transistor (external to the TDA9103) is switched on at the beginning of the positive slope of the horizontal sawtooth. It is switched off as required by the integrated regulator. The current in the switching power transistor is monitored and limited, and the ratio Ton/Ton+Toff of the power transistor is limited to 75% typically providing a very good reliability to the power supply. 15/27 TDA9103 Figure 18 : SMPS Block Diagram ISENSE H-FREQ 42 H-amp Reg-in 39 40 EA + RAP CYC + Buffer R - 22 SMPS OUT Clamp 9103-18.AI VREF S Basc 41 Compensation Figure 19 : SMPS Timing Diagram 0.25T 0.75T 6.4V H Osc Sawtooth 1.6V Error Amplifier Output (1.2V Max) SMPS Current 9103-19.AI SMPS Drive Figure 20 : H Scanning Amplitude Regulation Example Step-up Converter U0 H S can ning P art H yoke Usyst TDA9103 Hamp Adjust HDRIVE Usyst is a pproximatively proportiona l to Hfreq 9103-20.EPS SWITCHING REGULATOR VREF 4.8V Flyba ck Pe a k Detection a nd Re gulation The following functions are implemented in the TDA9103 : - A DC controlled variable gain amplifier allowing a variation of ±14% of the voltage reference. This is used to set the horizontal image amplitude. - An erroramplifier, the non inverting input of which is connected to the above mentioned adjustable voltage reference. The inverting input and the output of the error 16/27 amplifier are externally accessible. - A comparator which determines the conduction of the external transistor by comparing the output voltage of the error amplifier and the voltage applied on Pin 42 (ISENSE), which is the image of the current in the power transistor (current mode principle). - A flip-flop which memorizes the on or off state of the power transistor. - An output buffer stage (open collector). TDA9103 PARABOLA GENERATION FOR EAST-WEST CORRECTION (see Figure 21) control voltages V37 and V38 set to 4V, is 2V. It is important to note that the parasitic parabola during the discharge of the vertical oscillator capacitor is suppressed. Starting from the vertical ramp a parabola is generated for E/W correction. The core of the parabola generator is an analog multiplier which generates a current in the form : I = k (VRAMP - VMID)2 Where VRAMP is the vertical ramp, typically comprised between 2 and 5V, VMID is a DC voltage with a nominal value of 3.5V, but adjustable in the range 3.2V → 3.8V in order to generate a dissymmetric parabola if required (keystone adjustment). The current is converted into voltage through a variable gain transresistance amplifier. The gain, controlled by the voltage on Pin 37 (E/W-AMP) can be adjusted in the ratio 3/1. The parabola is available on Pin 36 by the way of an emitter follower which has to be biased by an external resistor (10kΩ). It must be AC coupled with external circuitry. The typical parabola amplitude (AC), with the DC VERTICAL PART (see Figure 22) The vertical part generates a fixed amplitude ramp which can be affected by a S correction shape. Then, the amplitude of this ramp is adjusted to drive an external power stage. The internal reference voltage used for the vertical part is available between Pin 26 and Pin 24. It can be used as voltage reference for any DC adjusment to keep a high accuracy to each adjustment. Its typical value is : V26 = VREF = 8V. The charge of the external capacitor on Pin 27 (VCAP) generates a fixed amplitude ramp between the internal voltages, VL (VL = VREF/4) and VH (VH = 5/8 ⋅ VREF). Figure 21 : Parabola Generation Principle + Analog. Multiplier I 36 or 38 E/W-CENT 37 E/W-AMP 9103-14.AI Vertical Ramp Figure 22 : Vertical Part Block Diagram Charge Current R 19R VREF 27 Disch. SYNCHRO OSCIL 25 Osc Cap Sampling Cap 29 S-CENTER 28 S-AMP S Correction 30 VERT-OUT Parabola Generator 36 EW-OUT 38 KEYST 31 VERT-AMP 9103-17.AI V-SYNC 34 Transconductance Amplifier VREF 37 EW-AMP 17/27 TDA9103 Function When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 180nF, the typical free running frequency is 84Hz. Typical free running frequency can be calculated by : f0 (Hz) = 1.5 ⋅ 10−5 ⋅ 1 COSC (nF) A negative or positive TTL level pulse applied on Pin 34 (VSYNC) can synchronise the ramp in the frequency range [fmin, fmax]. This frequency range dependson the external capacitor connectedon Pin 27. A capacitor in the range [150nF, 220nF] is recommanded for application in the following range : 50Hz to 120Hz. Typical maximum and minimum frequency, at 25°C and without any correction (S correction or C correction), can be calculated by : fmax = 2.5 ⋅ f0 fmin = 0.33 ⋅ f0 If S or C corrections are applied, these values are slighty affected. If an external synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than half a second: the highest voltage of the ramp on Pin 27 is sampled on the sampling capacitor connected on Pin 25 (VAGCCAP) at each clock pulse and a transconductance amplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. DC Control Adjustments Then, a S correction shape can be added to this ramp. This frequency independent S correction is generated internally; its amplitude is DC adjustable on Pin 28 (VSAMP) and it can be centered to generate C correction, according to the voltage applied on Pin 29 (VSCENT). It is non effective for VSAMP lower than VREF /4 and maximum for VSAMP = 3/4 ⋅ VREF. 18/27 Endly, the amplitude of this S corrected ramp can be adjusted by the voltage applied on Pin 31 (VAMP). The adjusted ramp is available on Pin 30 (VOUT) to drive an external power stage. The gain of this stage is typically ±30% when voltage applied on Pin 31 is in the range VREF/4 to 3/4 ⋅ VREF. The DC value of this ramp is kept constant in the frequency range , for any correction applied on it. Its typical value is : VDCOUT = VMID = 7/16 ⋅ VREF. A DC voltage is available on Pin 32 (VDCOUT). It is driven by the voltage applied on Pin 33 (VPOS). For a voltage control range between VREF/4 and 3/4 ⋅ VREF, the voltage available on Pin 32 is : VDCOUT = 7/16 ⋅ VREF ± 300mV. So, the VDCOUT voltage is correlated with DC value of VOUT. It increases the accuracy when temperature varies. Basic Equations In first approximation, the amplitude of the ramp on Pin 30 (VOUT) is : VOUT - VMID = (VCAP - VMID) [1 + 0.16 ⋅ (VAMP - VREF/2)] with VMID = 7/16 ⋅ VREF ; typically 3.5V VMID is the middle value of the ramp on Pin 27 VCAP = V27 , ramp with fixed amplitude. On Pin 32 (VDCOUT), the voltage (in volts) is calculated by : VDCOUT =VMID + 0.16 ⋅ (VPOS - VREF/2). VPOS is the voltage applied on Pin 33. The center of the S correction can be approximatively calculated according to the voltage applied on Pin 29 (VSCENT) : VCENTER = VMID + 0.25 ⋅ (VSCENT - VREF/2) This is an internal voltage used to adjust the C correction. The S correction can be adjusted along the ramp according to this parameter. It is ineffective when VSAMP is lower than VREF/4. The current available on Pin 27 (when VSAMP = VREF /4) is : IOSC = 3/8 ⋅ VREF ⋅ COSC ⋅ f COSC : capacitor connected on Pin 27 f synchronisation frequency The recommanded capacitor value on Pin 25 (VAGC) is 470nF. Its assumes a good stability of the internal closed loop. TDA9103 INTERNAL SCHEMATICS Figure 23 Figure 24 VREF Q1 VCC HDUTY 2 D22 Q4 Q8 D25 VCC D24 1 PLL2C Q9 D23 Q5 M7 9103-23.AI Q6 9103-22.AI Q6 Figure 25 Figure 26 VCC VCC Q15 D26 Q16 HFLY 3 Q13 D27 VCC D29 5 HREF Figure 27 9103-25.AI 9103-24.AI D28 Figure 28 VCC D31 S4/S3/S2/S1 Pins 6-7-8-9 D34 10 C0 D35 9103-26.AI M20 Q32 9103-27.AI D30 VCC Q33 19/27 TDA9103 INTERNAL SCHEMATICS (continued) Figure 29 Figure 30 M5 M4 M6 VCC Q46 D10 PLL1F 12 Q8 D9 9103-28.AI Q7 Figure 31 9103-29.AI Q69 R0 11 Figure 32 VCC VCC D20 D13 14 FH-MIN Q15 13 HLOCK-CAP D14 Figure 33 9103-31.AI Q17 9103-30.AI M11 D19 Figure 34 VCC Q22 VCC D27 D24 Q21 16 XRAY-IN Q26 15 H-POS Q23 Figure 35 9103-33.AI 9103-32.AI D28 D25 Figure 36 VCC D7 21 H-OUTCOLL VCC D6 D2 Q3 17 HSYNC Q1 Q4 D0 VCC D8 20/27 D9 9103-35.AI 9103-34.AI 20 H-OUTEM TDA9103 INTERNAL SCHEMATICS (continued) Figure 37 Figure 38 VCC VCC NPN NMOS NMOS NPN VAGCCAP 25 PMOS PMOS 26 VREF 9103-37.AI 9103-36.AI NPN Figure 39 VREF PNP VCC PNP VREF VCC 12V VCAP 27 NPN PNP NPN NMOS 9103-38.AI NPN Figure 40 Figure 41 VREF VCC VREF PNP PNP PNP PNP VCC NPN VS-CENT 29 NPN NPN 9103-40.AI NPN NPN 9103-39.AI VS-AMP 28 21/27 TDA9103 INTERNAL SCHEMATICS (continued) Figure 42 Figure 43 VCC VREF NPN VCC NPN 31 V-AMP 30 VOUT NPN Figure 44 9103-42.AI 9103-41.AI PNP Figure 45 VCC VCC PNP NPN 32 VDCOUT PNP V-POS 33 PNP PNP NPN NPN Figure 46 9103-44.AI 9103-43.AI NPN VREF Figure 47 VCC VCC VREF VREF NPN PNP 36 E/WOUT NPN VSYNC 34 PNP 22/27 9103-46.AI 9103-45.AI NPN TDA9103 INTERNAL SCHEMATICS (continued) Figure 48 Figure 49 VCC VCC VREF VREF PNP PNP PNP NPN E/W-AMP 37 KEYST 38 PNP NPN Figure 50 9103-48.AI NPN 9103-47.AI NPN Figure 51 VCC Q23 D21 VCC D28 Q24 Q26 REGIN 40 39 B+-ADJ Q20 Q19 9103-49.AI Figure 52 9103-50.AI D22 D27 Figure 53 Q16 VCC VCC D18 D13 41 COMP Q14 I SENSE 42 D17 Q10 D12 9103-52.AI 9103-51.AI Q15 23/27 9103-53.EPS J5 TP6 J2 TP2 1 2 CS SWITCH 3 4 J17 VSYNC BLK 1 J19 J3 1 HSYNC R73 10kΩ TP5 HFLY XRAY IN R74 10kΩ J18 HFLY 1 HFLY TP7 TP4 +12V TP3 on R2 1 2 0kΩ C8 100 µF 10k Ω R33 10k Ω R71 HDF + R1 3.9 kΩ S1 off HSHIFT R3 10 kΩ 1µF C36 R5 1 2 0kΩ C9 100nF + R4 3.9 kΩ + R8 1 2 0kΩ R6 1 0 kΩ 1µF C34 1µF C35 R9 1 0 kΩ C30 47 µF + R10 3.9 kΩ + HREF KEYST R13 3.9 kΩ C6 220nF R32 7.5k Ω 680pF 5% C2 C45 220pF C1 22nF R1 4 12 0kΩ + R31 1.8k Ω C3 10nF HREF C7 4.7 µF C29 100nF R7 3.9 kΩ + 1µF C39 R11 12 0kΩ FHMIN R1 2 10kΩ BPLUS 34 9 22 23 20 21 24 25 26 27 28 29 30 31 32 19 18 17 16 15 14 13 12 11 33 35 8 10 36 37 38 39 40 7 6 5 4 3 41 2 470nF C5 150nF TP1 C4 VSHIFT 42 R16 3.9 kΩ 1 T D A 9 1 0 3 IC1 PINCSH R1 5 10kΩ R17 120 kΩ 0/5V to 2/6V INTERFACE R20 120 kΩ +12V R1 8 10kΩ J3b 1 2 3 4 5 6 7 R19 3.9 kΩ 100nF C27 + C28 47 µF VREF C42 1µF + C43 1µF + D4 1N4148 C38 1µF + C37 1 µF + C29 470pF R68 1M Ω R2 1 10kΩ R23 120 kΩ R22 3.9 kΩ J2b VSIZE 3.9k Ω R69 +12V R67 22k Ω R2 4 10kΩ R26 120 kΩ C48 1nF 1 2 3 4 SCOR TP9 TP8 C40 1 µF + R25 3.9 kΩ J1b R80 2 .7 kΩ R2 7 10kΩ R29 120kΩ 1 2 3 4 C41 1 µF + VREF CCOR R28 3.9 kΩ 24/27 R3 0 10kΩ HSIZE R50 1kΩ 1kΩ R35 VERTICAL DEFLECTION STAGE R36 12k Ω R70 12kΩ C11 470pF C10 100nF 5.6k Ω R37 Q6 + 2 5 C14 470 µF 4 6 BC557 Q1 Q10 BC547 33 Ω + + C11 470pF C15 220nF 1.5 Ω R41 22k Ω + C32 100nF 2.7k Ω R56 12k Ω Q2 STD5N20 R45 47k Ω R59 T1 1/2W 1Ω R40 220 Ω 1/2W R39 C19 1nF 560 Ω 3 1 2 J22 CON2 3 1 2 J23 1 J21 E/W 3 1 2 J24 1 J25 75k Ω R79 VP B+ 1 J11 1 J20 1 J12 HORIZONTAL DRIVER STAGE HDRIVE V YOKE -12V 2.2 Ω 1W C44 220pF VP Q9 TIP122 R46 + EHT FEEDBACK G 5576-01 TP11 R57 1/2W R58 C47 10nF C25 22 µF 250V R78 22k Ω 1.5k Ω R66 33k Ω R65 C46 10nF 10k Ω R55 C20 100 µF R47a 47 Ω 3W VP R44 10 Ω 3W R47b +12V Q4 BC547 1kΩ R53 +12V C13 470 µF 1W 33Ω R36 5.6k Ω -12V 1 7 R64 3.3k Ω D3 BYT 13-800 G 5446-00 C24 220pF 400V R61 T2 VM + C12 100 µF 35V 3 R54 470 Ω BC547 Q3 10k Ω R52 IR430F D1 1N4004 +12V R51 10k Ω C21 10 µF + Q8 BC547 1kΩ R60 Q5 BC557 BC547 10k Ω R76 E/W POWER STAGE R48 R77 10k Ω 1kΩ 1.5k Ω R49 3.3k Ω R75 B+ CONVERTER C33 100pF + Q7 R72 1k Ω R63 1k Ω R62 1k Ω +12V C22 100 µF C23 220µF 63V TDA9103 APPLICATION DIAGRAM TDA9103 A demonstration board has been developped by SGS-THOMSON and is available through your usual SGS-THOMSON office. This board has been designed in order to give first the possibility to evaluate the TDA9103 in STAND ALONE, and then to be easily connected to an existing monitor. In stand alone evaluation, for exemple, flyback simulator is implemented in order to be able to close the 2nd PLL loop, potentiometers are also present to easily adjust all functions. Then for testing in a real application, the upper part of the board can be detached and the remaining part can be connected to real application. In addition to this, the application board has been volontary designed separating clearly all the blocks. This led to quite large PCB but give much more space for measuring anything on the board. 9103-60.TIF Figure 54 25/27 TDA9103 9103-61.EPS TDA9103 Figure 55 26/27 TDA9103 PACKAGE MECHANICAL DATA 42 PINS - PLASTIC PACKAGE E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 1 PMSDIP42.EPS Gage Plane e3 21 e2 SDIP42 A A1 A2 B B1 c D E E1 e e1 e2 e3 L Min. 0.51 3.05 0.36 0.76 0.23 37.85 15.24 12.70 2.54 Millimeters Typ. 3.81 0.46 1.02 0.25 38.10 13.72 1.778 15.24 3.30 Max. 5.08 4.57 0.56 1.14 0.38 38.35 16.00 14.48 18.54 1.52 3.56 Min. 0.020 0.120 0.0142 0.030 0.0090 1.490 0.60 0.50 0.10 Inches Typ. 0.150 0.0181 0.040 0.0098 1.5 0.540 0.070 0.60 0.130 Max. 0.200 0.180 0.0220 0.045 0.0150 1.510 0.629 0.570 0.730 0.060 0.140 SDIP42.TBL Dimensions Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 27/27