S6D0110 Preliminary 11 132 RGB Source & 176 Gate Driver With Internal GRAM FOR 65,536 Colors TFT-LCD July 9, 2002 Ver. 0.4 Prepared by: GOOHYUNG CHUNG [email protected] Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary S6D0110 Specification Revision History Version 0.0 0.1 0.2 0.3 0.4 2 Content Original Modified descriptions for operating voltage. (page 4) Modified figure for pad configuration. (page 6) Added descriptions for IM2-0 pin mode setting. (page 10) Added descriptions for /RD pin. (page 10) Modified table for register selection. (page 12) Added table for GRAM address. (page 17-18) Modified table for Instruction. (page 20) Modified descriptions for R00h. (page 22) Added descriptions for SM bit in R01h. (page 23) Modified descriptions for BT2-0 bits in R03h. (page 26) Modified descriptions for CAD bit in R04h. (page 28) Modified descriptions for VDV4-0 bits in R0Eh. (page 30) Added descriptions for R08h, R09h. (page 36) Modified figure for window address setting range. (page 41) Modified table for GRAM data and grayscale level. (page 43) Modified figure for voltage regulation function. (page 47) Added descriptions and table for system interface.(page 48) Modified figure for high-speed RAM write in window address range. (page 56) Added descriptions and figure for gate driver scan mode setting. (page 69) Modified figure for setup procedure of 8color display mode.(page 83) Modified figure for instruction setup flow. (page 85-86) Modified figure for interlaced drive. (page 89) Modified descriptions for restriction on the 1st/2 nd screen driving position register setting. (page 93) Modified descriptions for introduction. (page 3) Modified descriptions for Features. (page 4) Modified figure for block diagram. (page 5) Modified figure for pad configuration. (page 6) Added table for pad dimension. (page 7) Added figure for align key configuration and its coordinate. (page 8-9) Added table for pad center coordinates. (page 10-13) Modified and Added descriptions for pin description. (page 14-18) Modified descriptions for power supply circuit. (page 21) Modified figure for voltage setting. (page 22) Added figure for application circuit. (page 102) Modified table for pad dimension. (page 7) Added table for blanking period setting. (page 43) Modified descriptions for reset function. (page 53) Modified descriptions for VC2-0 and VRL3-0 bit. (page 36) Added descriptions and table contents for BGR bit. (page 39-40) Author Date G. H. Jung March 16 , 2002 M. S. Song April 1 , 2002 M. S. Song April 12 , 2002 M. S. Song April 30 , 2002 M. S. Song July 9, 2002 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary INTRODUCTION The S6D0110 is 1-chip solution for TFT-LCD panel: source driver with built-in memory, gate driver, power IC are integrated on one chip. This IC can display to a maximum of 132-RGB x 176-dot graphics on 65k-color TFT panel. The S6D0110 also supports bit-operation functions, 8/16-bit high-speed bus interface, and high-speed RAM-write functions enable efficient data transfer and high-speed rewriting of data to the internal GRAM. The moving picture area can be specified in internal GRAM by window function. The specified window area can be updated selectively so that moving picture is able to displayed simultaneously independent of still picture area. The S6D0110 has various functions for reducing the power consumption of a LCD system: It operates at low voltage (minimum 1.8V) and the IC has an internal GRAM to store 132-RGB x 176-dot 65k-color image. In addition, it has the internal booster that generates the LCD driving voltage, breeder resistance and the voltage follower circuit for LCD driver. This LSI is suitable for any medium-sized or small portable mobile solution requiring long-term driving capabilities, such as digital cellular phones supporting a web browser, bi-directional pagers, and small PDAs. 3 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary FEATURES 132-RGB x 176-dot TFT-LCD display controller/driver IC for 65,536 colors (396ch-source driver/176ch-gate driver) 16-/8-bit high-speed bus interface and serial peripheral interface (SPI) High-speed burst-RAM write function Writing to a window-RAM address area by using a window-address function Bit-operation functions for graphic processing − − Write-data mask functions in bit units Logical operation in pixel unit and conditional write function Various color-display control functions − − 65,536 colors can be displayed at the same time (gamma adjust included) Vertical scroll display function in raster-row units Internal RAM capacity: 132 x 16 x 176 = 371,712 bits Low-power operation supports: − − − − − Power-save functions such as the standby mode and sleep mode Partial LCD drive of two screens in any position Maximum 12-times step-up circuit for liquid crystal drive voltage Voltage followers to decrease direct current flow in the LCD drive breeder-resistors Equalizing function for the switching performance of step-up circuits and operational amplifiers N-raster row inversion drive (Reverse the polarity of driving voltage in every selected raster row is possible) Internal oscillation and hardware reset Structure for TFT-display retention volume (Cst/Cadd structure) Alternating functions for TFT-display counter-electrode power supply − N-line alternating drive of Vcom (Vgoff is also available for N-line alternating drive for Cadd) Internal power supply circuit − − Step-up circuit: five to nine times, positive-polarity inversion Adjustment of Vcom(Vgoff) amplitude: internal 22-level digital potentiometer Operating voltage • Applying voltage − VDD to VSS = 1.8 to 2.5 V (non-regulating) (logic voltage range – non-regulated) VDD3 to VSS = 2.3 to 3.3 V (regulating) (logic voltage range – regulated) − Vci to VSS = 2.5 to 3.3 V (internal reference power-supply voltage) − Vci1 to VSS = 1.7 to 2.75 V (2.5 x 0.68 ~ 2.75) (power supply for step-up circuits) • Generating voltage − For the source driver: AVDD to VSS = 3.5 to 5.5V (power supply for liquid crystal output circuits) GVDD to VSS = 3.0 to 5.0V (reference power supply for grayscale voltages) − For the gate driver: VGH to VGL = 14 to 30 V, VGH to VSS = +7.0 to +20 V, VgoffL = (VGL+0.5) to –7.5V, VgoffH = ~ to -1.5V − For the TFT-display counter electrode: Vcom amplitude(max) = 6V, VcomH to VSS(max) = GVDD VcomL to VSS(max) = 1.0 V to -Vci + 0.5 V 4 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary BLOCK DIAGRAM S1 S2 S3 : : : : S394 S395 S396 G0 G1 G2 : : G175 G176 G177 VGH VGL Vgoff Grayscale voltage generator 178 CH. Gate Driver GVDD AVDD Gate control VCL VCI1/2/3/4 VBS VGS CGND AVSS VREG1 VREG1OUT VREG2 VREG2OUT REGP/REGN VCOMH/L/R VCOMOUT VGOFFH/L VGOFFOUT / 2 / 3 Built-in Power Supply circuit 396 CH. Source Driver / 64 Gamma adjusting circuit M/AC circuit Address counter Built-in GRAM 132x16x176 = 371,712 bits Latch circuit / 64 / 64 Write data latch / 2 Read data latch / 16 CL1 M FLM EQ DISPTMG OSC1 OSC2 VCI / 16 Bit operation Timing Generator Index register Control register / 16 OSC VDD Power Regulator System Interface 8-/16-bit parallel, 3-pin SPI VDD3 VSS RESETB IM[2:0] CS RS E RW DB[15:2] DB1/SDO DB0/SDI PRegB RDVDD VDD3 Figure 1. Block Diagram 5 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary G97 G99 G101 G103 G105 DUMMY58 DUMMY57 DUMMY56 DUMMY60 DUMMY59 G0 G1 G3 G5 G7 G9 PAD CONFIGURATION DUMMY55 DUMMY54 DUMMY53 G107 G109 G111 G113 G115 G117 G119 G121 DUMMY1 VCOMOUT VCOMOUT CONTACT1 CONTACT2 RESETB1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 VGH VGH VCI3 VCI3 C23+ C23+ C23C23C22+ C22+ C22C22C21+ C21+ C21- G161 G163 G165 G167 G169 G171 G173 G175 DUMMY52 DUMMY51 DUMMY50 DUMMY49 DUMMY48 DUMMY47 DUMMY46 DUMMY45 S1 S2 S3 S4 S5 S6 S7 S8 C21C41+ C41+ C41C41C31+ C31+ C31C31VGL VGL VGL VGL CGND CGND CGND VDD3O IM0/ID VSSO IM1 VDD3O IM2 VDD3O DUMMY6 VSSO PREGB VDD3O RESETB2 VSSO DUMMY7 DUMMY8 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DUMMY9 VSSO DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI DUMMY10 VSSO RD WR/SCL RS CS DUMMY11 VSSO AVSS AVSS AVSS AVSS 19700 um AVSS AVSS 2980 um AVSS AVSS VSSO VSS VSS VSS VSS VSS VDD3O S6D0110 VDD3 VDD3 (0,0) Y VDD3 RDVDD RDVDD RDVDD RDVDD VDD VDD VDD VDD X VBS VCI VCI VCI VCI VCI VCI4 OSC1 OSC2 CL1 M FLM EQ DISPTMG TEST VGS VGS VGS VGS VGS VGS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCOML VCOML DUMMY12 DUMMY13 VCOMR VREG1OUT VREG1 GVDD GVDD GVDD GVDD VCOMH VCL VCL VCI1 VCI1 VCI1 VCI1 REGP REGN VCI2 AVDD AVDD VCI3 S389 S390 S391 S392 S393 S394 S395 S396 DUMMY36 DUMMY35 DUMMY34 DUMMY33 DUMMY32 DUMMY31 DUMMY30 DUMMY29 G177 G176 G174 G172 G170 G168 G166 G164 VCI3 C11C11C11C11C11+ C11+ C11+ C11+ C12C12C12C12C12+ C12+ C12+ C12+ VGOFF VGOFF VGOFFOUT VGOFFOUT VGOFFH VGOFFH VGOFFL VGOFFL VREG2 VREG2 VREG2OUT VREG2OUT DUMMY14 DUMMY15 DUMMY16 G124 G122 G120 G118 G116 G114 G112 G110 G108 DUMMY28 DUMMY27 DUMMY26 DUMMY17 RESETB3 DUMMY18 DUMMY19 VCOMOUT VCOMOUT G98 G100 G102 G104 G106 DUMMY23 DUMMY24 DUMMY25 DUMMY21 DUMMY22 G2 G4 G6 G8 G10 DUMMY20 Figure 2. Pad Configuration 6 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 1. S6D0110 Pad Dimensions Items Pad name. Chip size1) Size X Y - 19580 2860 INPUT PAD 54 100 OUTPUT PAD 36 70 Unit um Pad size NOTES: 1. Scribe line is not included in this chip size (Scribe line: 120um) 7 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary ALIGN KEY CONFIGURATION AND COORDINATE LEFT COG ALIGN KEY RIGHT COG ALIGN KEY 190 um 190 um 190 um (-9512, -1315) 45 um 30 um 45 um 45 um 30 um 30 um 40 um 190 um (9512, -1315) 40 um 30 um 30 um 45 um 45 um 40 um 30 um 45 um 45 um LEFT ILB ALIGN KEY 30 um 40 um 30 um 45 um RIGHT ILB ALIGN KEY 37 120 9 100 29 110 76 (-9699, -1227) 76 (9699, 1341) 29 100 9 120 37 Figure 3. COG and ILB align key 8 110 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Metal Size 45um Bump Size 45um 55um 45um 55um 45um 55um 55um Bump key ILB key (-9694,1205) ILB key COG key COG key Figure 4. Bump align key and align key configuration NOTES: 2. Gold bump height: 15um(typ.) 2. Wafer thickness: 470um 9 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary PAD CENTER COORDINATES Table 2. Pad Center Coordinates [Unit: um] NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PAD name DUMMY<1> VCOMOUT VCOMOUT CONTACT1 CONTACT2 RESETB1 DUMMY<2> DUMMY<3> DUMMY<4> DUMMY<5> VGH VGH VCI3 VCI3 C23+ C23+ C23C23C22+ C22+ C22C22C21+ C21+ C21C21C41+ C41+ C41C41C31+ C31+ C31C31VGL VGL VGL VGL CGND CGND CGND VDD3O IM<0> VSSO IM<1> VDD3O IM<2> VDD3O DUMMY<6> VSSO PREGB VDD3O RESETB2 VSSO DUMMY<7> DUMMY<8> DB<15> DB<14> DB<13> DB<12> X -9360 -9280 -9200 -9120 -9040 -8960 -8880 -8280 -7780 -7280 -7200 -7120 -7040 -6960 -6880 -6800 -6720 -6640 -6560 -6480 -6400 -6320 -6240 -6160 -6080 -6000 -5920 -5840 -5760 -5680 -5600 -5520 -5440 -5360 -5280 -5200 -5120 -5040 -4960 -4880 -4800 -4720 -4640 -4560 -4480 -4400 -4320 -4240 -4160 -4080 -4000 -3920 -3840 -3760 -3680 -3600 -3520 -3440 -3360 -3280 Y -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PAD name DB<11> DB<10> DB<9> DB<8> DUMMY<9> VSSO DB<7> DB<6> DB<5> DB<4> DB<3> DB<2> DB1/SDO DB0/SDI DUMMY<10> VSSO R/W E RS CSB DUMMY<11> VSSO AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS VSS* VSS VSS VSS VSS VSS VDD3* VDD3 VDD3 VDD3 RDVDD RDVDD RDVDD RDVDD VDD VDD VDD VDD VBS VCI VCI VCI VCI VCI VCI4 OSC1 OSC2 CL1 M FLM X -3200 -3120 -3040 -2960 -2880 -2800 -2720 -2640 -2560 -2480 -2400 -2320 -2240 -2160 -2080 -2000 -1920 -1840 -1760 -1680 -1600 -1520 -1440 -1360 -1280 -1200 -1120 -1040 -960 -880 -800 -720 -640 -560 -480 -400 -320 -240 -160 -80 0 80 160 240 320 400 480 560 640 720 800 880 960 1040 1120 1200 1280 1360 1440 1520 Y -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PAD name EQ DISPTMG TEST VGS VGS VGS VGS VGS VGS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCOML VCOML DUMMY<12> DUMMY<13> VCOMR VREG1OUT VREG1 GVDD GVDD GVDD GVDD VCOMH VCL VCL VCI1 VCI1 VCI1 VCI1 REGP REGN VCI2 AVDD AVDD VCI3 VCI3 C11C11C11C11C11+ C11+ C11+ C11+ C12C12C12C12C12+ C12+ C12+ C12+ VGOFF Notes: No. 91 & 92, No.97 & 98 PAD must be short by external wiring. 10 X 1600 1680 1760 1840 1920 2000 2080 2160 2240 2320 2400 2480 2560 2640 2720 2800 2880 2960 3040 3120 3200 3280 3360 3440 3520 3600 3680 3760 3840 3920 4000 4080 4160 4240 4320 4400 4480 4560 4640 4720 4800 4880 4960 5040 5120 5200 5280 5360 5440 5520 5600 5680 5760 5840 5920 6000 6080 6160 6240 6320 Y -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 NO. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PAD name VGOFF VGOFFOUT VGOFFOUT VGOFFH VGOFFH VGOFFL VGOFFL VREG2 VREG2 VREG2OUT VREG2OUT DUMMY<14> DUMMY<15> DUMMY<16> DUMMY<17> RESETB3 DUMMY<18> DUMMY<19> VCOMOUT VCOMOUT DUMMY<20> DUMMY<21> DUMMY<22> G<2> G<4> G<6> G<8> G<10> G<12> G<14> G<16> G<18> G<20> G<22> G<24> G<26> G<28> G<30> G<32> G<34> G<36> G<38> G<40> G<42> G<44> G<46> G<48> G<50> G<52> G<54> G<56> G<58> G<60> G<62> G<64> G<66> G<68> G<70> G<72> G<74> X 6400 6480 6560 6640 6720 6800 6880 6960 7040 7120 7200 7280 7780 8280 8880 8960 9040 9120 9200 9280 9360 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 Y -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1356 -1078 -1040 -1002 -964 -926 -888 -850 -812 -774 -736 -698 -660 -622 -584 -546 -508 -470 -432 -394 -356 -318 -280 -242 -204 -166 -128 -90 -52 -14 24 62 100 138 176 214 252 290 328 366 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 3. Pad Center Coordinates (continued) [Unit: um] NO. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 PAD name G<76> G<78> G<80> G<82> G<84> G<86> G<88> G<90> G<92> G<94> G<96> G<98> G<100> G<102> G<104> G<106> DUMMY<23> DUMMY<24> DUMMY<25> DUMMY<26> DUMMY<27> DUMMY<28> G<108> G<110> G<112> G<114> G<116> G<118> G<120> G<122> G<124> G<126> G<128> G<130> G<132> G<134> G<136> G<138> G<140> G<142> G<144> G<146> G<148> G<150> G<152> G<154> G<156> G<158> G<160> G<162> G<164> G<166> G<168> G<170> G<172> G<174> G<176> G<177> DUMMY<29> DUMMY<30> X 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9720 9610 9472 9434 9396 9358 9320 9282 9244 9206 9168 9130 9092 9054 9016 8978 8940 8902 8864 8826 8788 8750 8712 8674 8636 8598 8560 8522 8484 8446 8408 8370 8332 8294 8256 8218 8180 8142 8104 8066 8028 7990 7952 Y 404 442 480 518 556 594 632 670 708 746 784 822 860 898 936 974 1012 1050 1088 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 NO. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 PAD name DUMMY<31> DUMMY<32> DUMMY<33> DUMMY<34> DUMMY<35> DUMMY<36> S<396> S<395> S<394> S<393> S<392> S<391> S<390> S<389> S<388> S<387> S<386> S<385> S<384> S<383> S<382> S<381> S<380> S<379> S<378> S<377> S<376> S<375> S<374> S<373> S<372> S<371> S<370> S<369> S<368> S<367> S<366> S<365> S<364> S<363> S<362> S<361> S<360> S<359> S<358> S<357> S<356> S<355> S<354> S<353> S<352> S<351> S<350> S<349> S<348> S<347> S<346> S<345> S<344> S<343> X 7914 7876 7838 7800 7762 7724 7686 7648 7610 7572 7534 7496 7458 7420 7382 7344 7306 7268 7230 7192 7154 7116 7078 7040 7002 6964 6926 6888 6850 6812 6774 6736 6698 6660 6622 6584 6546 6508 6470 6432 6394 6356 6318 6280 6242 6204 6166 6128 6090 6052 6014 5976 5938 5900 5862 5824 5786 5748 5710 5672 Y 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 NO. PAD name 361 S<342> 362 S<341> 363 S<340> 364 S<339> 365 S<338> 366 S<337> 367 S<336> 368 S<335> 369 S<334> 370 S<333> 371 S<332> 372 S<331> 373 S<330> 374 S<329> 375 S<328> 376 S<327> 377 S<326> 378 S<325> 379 S<324> 380 S<323> 381 S<322> 382 S<321> 383 S<320> 384 S<319> 385 S<318> 386 S<317> 387 S<316> 388 S<315> 389 S<314> 390 S<313> 391 S<312> 392 S<311> 393 S<310> 394 S<309> 395 S<308> 396 S<307> 397 S<306> 398 S<305> 399 S<304> 400 S<303> 401 S<302> 402 S<301> 403 S<300> 404 S<299> 405 S<298> 406 S<297> 407 S<296> 408 S<295> 409 S<294> 410 S<293> 411 S<292> 412 S<291> 413 S<290> 414 S<289> 415 S<288> 416 S<287> 417 S<286> 418 S<285> 419 S<284> 420 S<283> X 5634 5596 5558 5520 5482 5444 5406 5368 5330 5292 5254 5216 5178 5140 5102 5064 5026 4988 4950 4912 4874 4836 4798 4760 4722 4684 4646 4608 4570 4532 4494 4456 4418 4380 4342 4304 4266 4228 4190 4152 4114 4076 4038 4000 3962 3924 3886 3848 3810 3772 3734 3696 3658 3620 3582 3544 3506 3468 3430 3392 Y 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 NO. PAD name 421 S<282> 422 S<281> 423 S<280> 424 S<279> 425 S<278> 426 S<277> 427 S<276> 428 S<275> 429 S<274> 430 S<273> 431 S<272> 432 S<271> 433 S<270> 434 S<269> 435 S<268> 436 S<267> 437 S<266> 438 S<265> 439 S<264> 440 S<263> 441 S<262> 442 S<261> 443 S<260> 444 S<259> 445 S<258> 446 S<257> 447 S<256> 448 S<255> 449 S<254> 450 S<253> 451 S<252> 452 S<251> 453 S<250> 454 S<249> 455 S<248> 456 S<247> 457 S<246> 458 S<245> 459 S<244> 460 S<243> 461 S<242> 462 S<241> 463 S<240> 464 S<239> 465 S<238> 466 S<237> 467 S<236> 468 S<235> 469 S<234> 470 S<233> 471 S<232> 472 S<231> 473 S<230> 474 S<229> 475 S<228> 476 S<227> 477 S<226> 478 S<225> 479 S<224> 480 S<223> X 3354 3316 3278 3240 3202 3164 3126 3088 3050 3012 2974 2936 2898 2860 2822 2784 2746 2708 2670 2632 2594 2556 2518 2480 2442 2404 2366 2328 2290 2252 2214 2176 2138 2100 2062 2024 1986 1948 1910 1872 1834 1796 1758 1720 1682 1644 1606 1568 1530 1492 1454 1416 1378 1340 1302 1264 1226 1188 1150 1112 Y 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 11 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Table 4. Pad Center Coordinates (continued) [Unit: um] NO. 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 12 PAD name S<222> S<221> S<220> S<219> S<218> S<217> S<216> S<215> S<214> S<213> S<212> S<211> S<210> S<209> S<208> S<207> S<206> S<205> S<204> S<203> S<202> S<201> S<200> S<199> S<198> S<197> S<196> S<195> S<194> S<193> DUMMY<37> DUMMY<38> DUMMY<39> DUMMY<40> DUMMY<41> DUMMY<42> DUMMY<43> DUMMY<44> S<192> S<191> S<190> S<189> S<188> S<187> S<186> S<185> S<184> S<183> S<182> S<181> S<180> S<179> S<178> S<177> S<176> S<175> S<174> S<173> S<172> S<171> X 1074 1036 998 960 922 884 846 808 770 732 694 656 618 580 542 504 466 428 390 352 314 276 238 200 162 124 86 48 10 -28 -66 -104 -142 -180 -218 -256 -294 -332 -370 -408 -446 -484 -522 -560 -598 -636 -674 -712 -750 -788 -826 -864 -902 -940 -978 -1016 -1054 -1092 -1130 -1168 Y 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 NO. PAD name 541 S<170> 542 S<169> 543 S<168> 544 S<167> 545 S<166> 546 S<165> 547 S<164> 548 S<163> 549 S<162> 550 S<161> 551 S<160> 552 S<159> 553 S<158> 554 S<157> 555 S<156> 556 S<155> 557 S<154> 558 S<153> 559 S<152> 560 S<151> 561 S<150> 562 S<149> 563 S<148> 564 S<147> 565 S<146> 566 S<145> 567 S<144> 568 S<143> 569 S<142> 570 S<141> 571 S<140> 572 S<139> 573 S<138> 574 S<137> 575 S<136> 576 S<135> 577 S<134> 578 S<133> 579 S<132> 580 S<131> 581 S<130> 582 S<129> 583 S<128> 584 S<127> 585 S<126> 586 S<125> 587 S<124> 588 S<123> 589 S<122> 590 S<121> 591 S<120> 592 S<119> 593 S<118> 594 S<117> 595 S<116> 596 S<115> 597 S<114> 598 S<113> 599 S<112> 600 S<111> X -1206 -1244 -1282 -1320 -1358 -1396 -1434 -1472 -1510 -1548 -1586 -1624 -1662 -1700 -1738 -1776 -1814 -1852 -1890 -1928 -1966 -2004 -2042 -2080 -2118 -2156 -2194 -2232 -2270 -2308 -2346 -2384 -2422 -2460 -2498 -2536 -2574 -2612 -2650 -2688 -2726 -2764 -2802 -2840 -2878 -2916 -2954 -2992 -3030 -3068 -3106 -3144 -3182 -3220 -3258 -3296 -3334 -3372 -3410 -3448 Y 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 NO. PAD name 601 S<110> 602 S<109> 603 S<108> 604 S<107> 605 S<106> 606 S<105> 607 S<104> 608 S<103> 609 S<102> 610 S<101> 611 S<100> 612 S<99> 613 S<98> 614 S<97> 615 S<96> 616 S<95> 617 S<94> 618 S<93> 619 S<92> 620 S<91> 621 S<90> 622 S<89> 623 S<88> 624 S<87> 625 S<86> 626 S<85> 627 S<84> 628 S<83> 629 S<82> 630 S<81> 631 S<80> 632 S<79> 633 S<78> 634 S<77> 635 S<76> 636 S<75> 637 S<74> 638 S<73> 639 S<72> 640 S<71> 641 S<70> 642 S<69> 643 S<68> 644 S<67> 645 S<66> 646 S<65> 647 S<64> 648 S<63> 649 S<62> 650 S<61> 651 S<60> 652 S<59> 653 S<58> 654 S<57> 655 S<56> 656 S<55> 657 S<54> 658 S<53> 659 S<52> 660 S<51> X -3486 -3524 -3562 -3600 -3638 -3676 -3714 -3752 -3790 -3828 -3866 -3904 -3942 -3980 -4018 -4056 -4094 -4132 -4170 -4208 -4246 -4284 -4322 -4360 -4398 -4436 -4474 -4512 -4550 -4588 -4626 -4664 -4702 -4740 -4778 -4816 -4854 -4892 -4930 -4968 -5006 -5044 -5082 -5120 -5158 -5196 -5234 -5272 -5310 -5348 -5386 -5424 -5462 -5500 -5538 -5576 -5614 -5652 -5690 -5728 Y 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 NO. 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 PAD name S<50> S<49> S<48> S<47> S<46> S<45> S<44> S<43> S<42> S<41> S<40> S<39> S<38> S<37> S<36> S<35> S<34> S<33> S<32> S<31> S<30> S<29> S<28> S<27> S<26> S<25> S<24> S<23> S<22> S<21> S<20> S<19> S<18> S<17> S<16> S<15> S<14> S<13> S<12> S<11> S<10> S<9> S<8> S<7> S<6> S<5> S<4> S<3> S<2> S<1> DUMMY<45> DUMMY<46> DUMMY<47> DUMMY<48> DUMMY<49> DUMMY<50> DUMMY<51> DUMMY<52> G<175> G<173> X -5766 -5804 -5842 -5880 -5918 -5956 -5994 -6032 -6070 -6108 -6146 -6184 -6222 -6260 -6298 -6336 -6374 -6412 -6450 -6488 -6526 -6564 -6602 -6640 -6678 -6716 -6754 -6792 -6830 -6868 -6906 -6944 -6982 -7020 -7058 -7096 -7134 -7172 -7210 -7248 -7286 -7324 -7362 -7400 -7438 -7476 -7514 -7552 -7590 -7628 -7666 -7704 -7742 -7780 -7818 -7856 -7894 -7932 -7970 -8008 Y 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 5. Pad Center Coordinates (continued) [Unit: um] NO. 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 PAD name G<171> G<169> G<167> G<165> G<163> G<161> G<159> G<157> G<155> G<153> G<151> G<149> G<147> G<145> G<143> G<141> G<139> G<137> G<135> G<133> G<131> G<129> G<127> G<125> G<123> G<121> G<119> G<117> G<115> G<113> G<111> G<109> G<107> DUMMY<53> DUMMY<54> DUMMY<55> DUMMY<56> DUMMY<57> DUMMY<58> G<105> G<103> G<101> G<99> G<97> G<95> G<93> G<91> G<89> G<87> G<85> G<83> G<81> G<79> G<77> G<75> G<73> G<71> G<69> G<67> G<65> X -8046 -8084 -8122 -8160 -8198 -8236 -8274 -8312 -8350 -8388 -8426 -8464 -8502 -8540 -8578 -8616 -8654 -8692 -8730 -8768 -8806 -8844 -8882 -8920 -8958 -8996 -9034 -9072 -9110 -9148 -9186 -9224 -9262 -9300 -9338 -9376 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 Y 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1362 1252 1088 1050 1012 974 936 898 860 822 784 746 708 670 632 594 556 518 480 442 404 366 328 290 252 214 NO. PAD name 781 G<63> 782 G<61> 783 G<59> 784 G<57> 785 G<55> 786 G<53> 787 G<51> 788 G<49> 789 G<47> 790 G<45> 791 G<43> 792 G<41> 793 G<39> 794 G<37> 795 G<35> 796 G<33> 797 G<31> 798 G<29> 799 G<27> 800 G<25> 801 G<23> 802 G<21> 803 G<19> 804 G<17> 805 G<15> 806 G<13> 807 G<11> 808 G<9> 809 G<7> 810 G<5> 811 G<3> 812 G<1> 813 G<0> 814 DUMMY<59> 815 DUMMY<60> X -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 -9610 -9720 Y 176 138 100 62 24 -14 -52 -90 -128 -166 -204 -242 -280 -318 -356 -394 -432 -470 -508 -546 -584 -622 -660 -698 -736 -774 -812 -850 -888 -926 -964 -1002 -1040 -1078 -1116 NO. PAD name X Y NO. PAD name X Y 13 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary PIN DESCRIPTION Table 6. Power supply pin description Symbol I/O Description VDD Power System power supply. As S6D0110 have internal regulator, VDD range varies with each mode. Non-regulated(PregB = 1) : +1.8 ~ +2.5 V Regulated (PregB = 0) : +1.9V VDD3 Power System power supply for internal regulator as external power. (VDD3: +2.5 to +3.3 V) VSS Power System ground(0V) CGND Power System ground level for step up circuit block. AVSS Power System ground level for analog circuit block. VCI Power An internal reference power supply for V REG1OUT/VREG2OUT. Connect VDD when VDD = 2.5 to 3.3 V. Connect a 2.5 to 3.3 V external-voltage power supply when VDD = 1.8 to 2.5 V. AVDD O A power output pin for source driver that is generated from power block. Connect a capacitor for stabilization. (AVDD: 3.5 to 5.5 V) Interconnect this pin to VCI2 pin. GVDD O A Standard level for grayscale voltage generator. Connect a capacitor for stabilization. VGS I Reference voltage for grayscale voltage generator. VCI1 I A reference voltage for step-up circuit 1. VCI2 I A reference voltage for step-up circuit 2. VCI3 I A reference voltage in step-up circuit 3. VCI4 I A reference voltage in step-up circuit 4. Connect VCI, VDD, or an external power supply lower than 3.3 V. VCL O A power supply pin for generating VcomL. When VcomL is higher than VSS, outputs VSS level. 14 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 7. Power supply pin description (continued) Symbol I/O VBS I REGN, REGP I/O Input pins for reference voltages of VREG1OUT, and VREG2OUT when the internal reference-voltage generation circuit is not used. Leave these pins open when the internal reference-voltage generation circuit is used. O This pin outputs a reference voltage for VREG1 between AVDD(DDVDH) and VSS. When the internal reference voltage is not used, the reference voltage can be generated from the voltage of REGP. Connect this pin to VREG1 and a capacitor for stabilization. When this pin is not used, leave it open. VREG1OUT VREG2OUT O VcomOUT O Description Reference voltage for step-up circuit3. When VGH (max) = 20V, connect this pin to VCI. When VGH (max) = 15V, connect this pin to VSS. This pin outputs a reference voltage for VREG2 between VSS and VGL When the internal reference voltage is not used, the reference voltage can be generated from the voltage of REGN. Connect this pin to VREG2 and a capacitor for stabilizatio0n. When this pin is not used, leave it open. A power supply for the TFT-display counter electrode. The alternating cycle can be set by the M pin. Connect this pin to the TFT-display counter electrode. This pin is also used as equalizing function: When EQ = “High” period, all source driver’s outputs (S1 to S396) are short to Vcom level (Hi-z). In case of VcomL < 0V, equalizing function must not be used. (Set EQ bit (R07h) to be “00” for preventing the abnormal function.) VcomR I A reference voltage of VcomH. When VcomH is externally adjusted, halt the internal adjuster of VcomH by setting the register and insert a variable resistor between GVDD and VSS. When this pin is not externally adjusted, leave it open and adjust VcomH by setting the internal register. VcomH O This pin indicates a high level of Vcom generated in driving the Vcom alternation. Connect this pin to the capacitor for stabilization. VcomL O When the Vcom alternation is driven, this pin indicates a low level of Vcom. An internal register can be used to adjust the voltage. Connect this pin to a capacitor for stabilization. When the VCOMG bit is low, the VcomL output stops and a capacitor for stabilization is not needed. VGH O A positive power output pin for gate driver, internal step-up circuits, bias circuits, and operational amplifiers. Connect a capacitor for stabilization. Interconnect this pin to VCI3 pin. VGL O A Negative power output pin for gate driver, bias circuits, and operational amplifiers. Connect a capacitor for stabilization. When internal VGL generator is not used, connect an external-voltage power supply higher than -15.0 V. 15 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Table 8. Power supply pin description (continued) Symbol I/O Vgoff I Power supply pin for off level for gate of TFT. Connect this pin to VgoffOUT. O An power output pin for gate driver. This pin is a negative voltage for the gate off level. Alternation can be synchronized by M pin. Set the internal register according to the structure of the TFT-display retention volume. For the amplitude at the alternation driving, this pin outputs a voltage between VcomH and VcomL with the VgoffL reference voltage.. VgoffH O When the Vgoff alternation is driven, this pin indicates a high level of Vgoff. Connect a capacitor for stabilization. When the CAD bit is low, the VgoffH output stops and a capacitor for stabilization is not needed. VgoffL O When the Vgoff alternation is driven, this pin indicates a low level of Vgoff. Connect a capacitor for stabilization. An internal register can be used to adjust the voltage. C11+,C11to C23+,C23- - Connect the step-up capacitor according to the step-up factor. C31+, C31- - Connect a step-up capacitor for generating the VGL level. C41+, C41- - Connect a step-up capacitor for generating the -V CL level. VgoffOUT 16 Description S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 9. System interface pin description Symbol I/O IM2-1, IM0/ID I CSB I RS I E (/WR,SCL) I R/W (/RD) I DB0/SDI I/O DB1/SDO I/O DB2-DB15 I/O RESETB1/ RESETB2/ RESETB3 I Description Selects the MPU interface mode: IM2 IM1 IM0/ID MPU interface mode VSS VSS VSS 68-system 16-bit bus interface VSS VSS VDD3 68-system 8bit bus interface VSS VDD3 VSS 80-system 16bit bus interface VSS VDD3 VDD3 80-system 8bit bus interface VDD3 VSS ID Serial peripheral interface (SPI) When a SPI mode is selected, the IM0 pin is used as the ID setting for a device code. Chip select pin. Low: S6D0110 is selected and can be accessed High: S6D0110 is not selected and cannot be accessed Must be fixed at VSS level when not in use. Register select pin. Low: Index/status, High: Control IM2 IM1 Pin func. Pin description For a 68-system bus interface, serves as an enable VSS VSS E signal to activate data read/write operation. For an 80-system bus interface, serves as a write VSS VDD3 /WR strobe signal and writes data at the low level. For a serial peripheral interface, serves as the VDD3 VSS SCL synchronous clock signal. IM2 IM1 Pin func. Pin description For a 68-system bus interface, serves as a signal to VSS VSS R/W select data read/write operation. Low: Write , High: Read For an 80-system bus interface, serves as a read VSS VDD3 /RD strobe signal and reads data at the low level. When SPI mode is selected, fix this pin at “VSS” level. Bi-directional data input pin for the first bit of 16-bit data bus or serial data of SPI. For an 8-bit bus interface, data bus uses DB15-DB8; fix unused DB7-DB0 to the VDD3 or VSS level. For a serial peripheral interface (SPI), The input data is fetched at the rising edge of the SCL signal. Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the VDD3 or VSS level. For a serial peripheral interface (SPI), serves as the serial data output pin(SDO). Successive bit values are output on the falling edge of the SCL signal. Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the VDD3 or VSS level. Reset pin. Initializes the LSI when low. Must be reset after power-on. 17 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Table 10. Display pin description Symbol I/O Description Source driver output pins. The SS bit can change the shift direction of the source signal. For example, if SS = 0, RAM address 0000 is output from S1. If SS = 1, it is output from S396. S1, S4, S7, ... S(3n-1) : display Red (R) (SS = 0) S2, S5, S8, ... S(3n-2) : display Green (G) (SS = 0) S3, S6, S9, ... S(3n) : display Blue (B) (SS = 0) Gate driver output pins. The output of driving circuit is whether VGH, output gate selecting level or Vgoff, gate nonselecting level. S1 - S396 O G1 - G176 O G0, G177 O Gate driver output pins for IC maker’s testing. Please, leave it disconnected. CL1 O Output pin for one-raster-row-cycle pulse. M O Output pin for AC-cycle signal. FLM O Output pin for frame-start pulse. EQ O Output pin for timing for equalizing Low : Normal display, High : Equalizing DISPTMG O Gate off signal in the partial display Low : Non-display, High : Normal output Table 11. Oscillator and internal power regulator pin description Symbol I/O OSC1/ OSC2 I/O PregB I Internal power regulator control input pin. When the internal regulated power (RDVDD) is used as VDD, PregB is fixed to “low” level. When the external logic power(VDD3) is used as VDD, PregB is fixed to “high” level. RDVDD O Internal power regulated-VDD output (typ. 1.9V). When PregB is “low”, RDVDD is connected to VDD pin. When PRegB is “high”, leave this pin open. 18 Description Connect an external resistor for R-C oscillation. When input the clock from outside, input to OSC1, and open OSC2. S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary FUNCTIONAL DESCRIPTION System Interface The S6D0110 has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8-bit bus, and a serial interface (SPI: Serial Peripheral Interface port). The IM2-0 pins select the interface mode. The S6D0110 has three 16-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information for control register and GRAM. The WDR temporarily stores data to be written into control register and GRAM. The RDR temporarily stores data read from GRAM. Data written into the GRAM from the MPU is first written into the WDR and then written into the GRAM by internal operation automatically. Data is read through the RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are valid. When a logic operation is performed inside of the S6D0110 by using the display data stored in the GRAM and the data written from the MPU, the data read through the RDR is used. Accordingly, the MPU does not need to read data twice nor to fetch the read data into the MPU. This enables high-speed processing. Execution time for instruction, except oscillation start, i s 0-clock cycle so that instructions can be written in succession. Table 12. Register Selection (80-system 8/16 Parallel Interface) /WR 0 1 0 1 /RD 1 0 1 0 RS 0 0 1 1 Operations Write indexes into IR Reads internal status Writes into control registers and GRAM through WDR Reads from GRAM through RDR Table 13. Register Selection (Serial Peripheral Interface) R/W Bits 0 1 0 1 RS Bits 0 0 1 1 Operations Writes index into IR Reads internal status Writes data into control registers and GRAM through WDR Reads data from GRAM through RDR Bit Operation The S6D0110 supports the following functions: a write data mask function that selects and writes data into the GRAM in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the GRAM and writes into the GRAM. With the 16-bit bus interface, these functions can greatly reduce the processing loads of the MPU graphics software and can rewrite the display data in the GRAM at high speed. For details, see the Graphics Operation Function section. 19 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Address Counter (AC) The address counter (AC) assign addresses to the GRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing into the GRAM, the AC is automatically increased/decreased by 1 according to ID1-0 bit of control register. After reading data from GRAM, the AC is not updated. A window address function allows data to be written only to a window area specified by GRAM. Graphics RAM (GRAM) The graphics RAM (GRAM) has sixteen bits/pixel and stores the bit-pattern data for 132 RGB x 176 dot display. Grayscale Voltage Generator The grayscale voltage circuit generates a LCD driver circuit that corresponds to the grayscale levels as specified in the grayscale ϒ-adjusting resistor. 65,536 colors can be displayed at the same time. For details, see the ϒ-adjusting resistor section. Timing Generator The timing generator generates timing signals for the operation of internal circuits such as GRAM. The RAM read timing for display and the internal operation timing for MPU access is generated separately to avoid interference with one another. The timing generator generates the interface signals (M, FLM, CL1, EQ, DISPTMG). Oscillation Circuit (OSC) The S6D0110 can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be reduced. For details, see the Oscillation Circuit section. Source Driver Circuit This liquid crystal display source driver circuit consists of 396 source drivers (S1 to S396). Display pattern data is latched when 396-bit data has arrived. The latched data then enables the source drivers to generate drive waveform outputs. The SS bit can change the shift direction of 396-bit data by selecting an appropriate direction for the device-mounted configuration. Gate Driver Circuit This liquid crystal display gate driver circuit consists of 178 gate drivers (G0 to G177). The VGH or Vgoff level is output by the signal from the gate control circuit. G0 and G177 are IC maker’s test pins. 20 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Power Supply Circuit Figure 2 shows a configuration of the voltage generation circuit for S6D0110. The step-up circuits consist of stepup circuits 1 to 4. Step-up circuit 1 doubles or triples the voltage supplied to Vci1, and that voltage is doubled, tripled, or quadrupled in step-up circuit 2. Step-up circuit 3 reverses the VGH level with reference to VSS or VBS and generates the VGL level. Step-up circuit 4 reverses the Vci level with reference to VSS and generates the VCL level. These step-up circuits generate power supplies AVDD, GVDD, VGH, VGL, Vgoff, and Vcom. Reference voltages GVDD, Vcom, and Vgoff for the grayscale voltage are amplified in amplification circuits 1 and 2 from the internalvoltage adjustment circuit or the REGP or REGN voltage, and generate each level depending on that voltage. Connect Vcom to the TFT panel. VREG2 OUT VREG1 OUT Amplfiication circuit2 (Vgoff adjustment) VREG2 VREG1 Amplification circuit1 (VDH adjustment) VDH output amplifier VcomH adjustment circuit REGP VDHout VDH Vcom amplitude adjustment circuit REGN Vci Vci Regulator Vciout VcomH output amplifier Voltage adjustment circuit VcomH Vcom Adjust VcomH voltage (when using an external variable resistor) VcomR VcomL output amplifier Vci1 When using Vciout C11C11+ C12- Step-up circuit 1 C12+ VcomL VgoffH amplitude adjustment circuit VLOUT1 DDVDH VgoffH output amplifier DDVDH Vci2 C21- VgoffH Vgoffout C21+ C22C22+ Step-up circuit 2 C23- VgoffL output amplifier VgoffL C23+ VLOUT2 VGH VGH Vci3 C31C31+ Step-up circuit 3 VLOUT3 VGL VGL Vci Vci4 C41C41+ VLOUT4 VCL Step-up circuit 4 Vdd Vss Vci Vss Figure 5. Configuration of the Internal Power-Supply Circuit Notes: Use the 1uF capacitor. 21 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Pattern Diagrams for Voltage Setting The following figure shows a pattern diagram for the voltage setting and an example of waveforms. VGH(+7 ~ +20V) BT2-0 AVDD(+3.5 ~ +5.5V) DDVDH VREG1OUT BT2-0 VCOM4-0 VC2-0 Vci(2.5V ~ 3.3V) Vci1 GVDD(+3.0 ~ +5.0V) VDH VcomH(+3.0 ~ VDH) VRH3-0 VDD(1.8V ~ 3.3V) VDV4-0 VSS(0V) (-1 times) (-1 times) VcomL(VCL+0.5 to 1.0V) VCL VRL3-0 VgoffH(to -5.0V) VREG2OUT VgoffL (VGL+0.5 to -16.0V) VGL(-9 to -16.5V) Note: Adjust the conditions of AVDD-GVDD>0.5V, VcomL-VCL>0.5V, and Vgoff-VGL>0.5V with loads because they differ depending on the display load to be driven. In addition, Vci can be directly input to Vci1. VGH Sn(source output) GVDD(VDH) VcomH VCOM VcomL VgoffH Gn(Gate output) VgoffL Figure 6. Pattern diagram and an example of waveforms 22 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Set up Flow of Power Supply Apply the power in a sequence as shown in Figure 7. The stable time of the oscillation circuit, step-up circuit, and operational amplifier depend on the external resistor or capacitance. Power Supply (Vdd on) 1ms Power-on reset and display off 10ms or more (Stable time of the oscillation circuit) Bits for power-supply initial setting: VCOM, VC20, VRH3Issues instructions for 0, CAD, VRL3power supply setting (1) 0, VCM4-0, VDV40, VRN4-0, VRP4-0 (setting of the sourcedriver grayscale voltage) Issues instruction for power supply setting (2) 50ms or more (Stable times of step-up circuit 1 and 2) 200ms or more (Stable time of the stepup operational amplifier) Bits for display off. DTE=0 D1-0=00 GON=0 PON=0 Issues instruction for power supply setting (3) Bits for power-supply operation start setting: BT2-0, DC20, AP2-0 Bits for source-driver operational amplifier operaton-start setting: SAP2-0 Bits for step-up circuit3 operation start PON=1 Issues instruction for other mode setting Bits for display on: DTE =1, D10=11, GON=1 Display off sequence* Display off Bits for display off: DTE =0, D10=00, GON=0 Bits for source-driver operational amplifier Instruction for power supply setting(1)operation-stop setting: SAP2-0 Bits for power supply stop setting: AP2-0 for operational Instruction for power supply setting(2) amplifier, DC2-0 for step-up circuit Power supply (Vdd off) Power-off sequence Display-on Sequence* Diplay on Normal Display Bits for display on: DTE =1, D10=11, GON=1 Power-on sequence Figure 7. Set up Flow of Power Supply 23 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary GRAM ADDRESS Table 14. GRAM address (SS=”0”) … … … S385 S386 S387 S388 S389 S390 S391 S392 S393 S394 S395 S396 DB … … 15 DB 0 G176 "0000"H "0001"H "0002"H "0003"H G2 G175 "0100"H "0101"H "0102"H "0103"H G3 G174 "0200"H "0201"H "0202"H "0203"H G4 G173 "0300"H "0301"H "0302"H "0303"H G5 G172 "0400"H "0401"H "0402"H "0403"H G6 G171 "0500"H "0501"H "0502"H "0503"H G170 "0600"H "0601"H "0602"H "0603"H G8 G169 "0700"H "0701"H "0702"H "0703"H "0903"H G11 G166 "0A00"H "0A01"H "0A02"H "0A03"H G12 G165 "0B00"H "0B01"H "0B02"H "0B03"H G13 G164 "0C00"H "0C01"H "0C02"H "0C03"H G14 G163 "0D00"H "0D01"H "0D02"H "0D03"H G15 G162 "0E00"H "0E01"H "0E02"H "0E03"H G16 G161 "0F00"H "0F01"H "0F02"H "0F03"H G17 G160 "1000"H "1001"H "1002"H "1003"H G18 G159 "1100"H "1101"H "1102"H "1103"H G19 G158 "1200"H "1201"H "1202"H "1203"H G20 G157 "1300"H "1301"H "1302"H "1303"H …… "0803"H "0902"H …… "0802"H "0901"H …… "0801"H "0900"H …… "0800"H G167 …… G168 …… G9 G10 G169 G168 "A800"H "A801"H "A802"H "A803"H G170 G167 "A900"H "A901"H "A902"H "A903"H G171 G166 "AA00"H "AA01"H "AA02"H "AA03"H G172 G165 "AB00"H "AB01"H "AB02"H "AB03"H G173 G164 "AC00"H "AC01"H "AC02"H "AC03"H G174 G163 "AD00"H "AD01"H "AD02"H "AD03"H G175 G162 "AE00"H "AE01"H "AE02"H "AE03"H G176 G161 "AF00"H "AF01"H "AF02"H "AF03"H … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … DB DB … … 0 15 DB DB … … 0 15 DB DB … … 0 15 DB 0 "0080"H "0081"H "0082"H "0083"H "0180"H "0181"H "0182"H "0183"H "0280"H "0281"H "0282"H "0283"H "0380"H "0381"H "0382"H "0383"H "0480"H "0481"H "0482"H "0483"H "0580"H "0581"H "0582"H "0583"H "0680"H "0681"H "0682"H "0683"H "0780"H "0781"H "0782"H "0783"H "0880"H "0881H "0882"H "0883"H "0980"H "0981"H "0982"H "0983"H "0A80"H "0A81"H "0A82"H "0A83"H "0B80"H "0B81"H "0B82"H "0B83"H "0C80"H "0C81"H "0C82"H "0C83"H "0D80"H "0D81"H "0D82"H "0D83"H "0E80"H "0E81"H "0E82"H "0E83"H "0F80"H "0F81"H "0F82"H "0F83"H "1080"H "1081"H "1082"H "1083"H "1180"H "1181"H "1182"H "1183"H "1280"H "1281"H "1282"H "1283"H "1380"H "1381"H "1382"H "1383"H …… DB DB … … 0 15 …… DB DB … … 0 15 …… DB DB … … 0 15 G1 G7 24 DB … … 15 …… GS=0 GS=1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S/G Output "A880"H "A881"H "A880"H "A883"H "A980"H "A981"H "A980"H "A983"H "AA80"H "AA81"H "AA80"H "AA83"H "AB80"H "AB81"H "AB80"H "AB83"H "AC80"H "AC81"H "AC80"H "AC83"H "AD80"H "AD81"H "AD80"H "AD83"H "AE80"H "AE81"H "AE80"H "AE83"H "AF80"H "AF81"H "AF80"H "AF83"H S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 15. GRAM address (SS=”1”) … … … S385 S386 S387 S388 S389 S390 S391 S392 S393 S394 S395 S396 DB … … 15 DB … … 15 DB 0 G1 G176 "0083"H "0082"H "0081"H "0080"H G2 G175 "0183"H "0182"H "0181"H "0180"H G3 G174 "0283"H "0282"H "0281"H "0280"H G4 G173 "0383"H "0382"H "0381"H "0380"H G5 G172 "0483"H "0482"H "0481"H "0480"H G6 G171 "0583"H "0582"H "0581"H "0580"H G7 G170 "0683"H "0682"H "0681"H "0680"H G8 G169 "0783"H "0782"H "0781"H "0780"H G9 G168 "0883"H "0882"H "0881H "0880"H G10 G167 "0983"H "0982"H "0981"H "0980"H G11 G166 "0A83"H "0A82"H "0A81"H "0A80"H G12 G165 "0B83"H "0B82"H "0B81"H "0B80"H G13 G164 "0C83"H "0C82"H "0C81"H "0C80"H G163 "0D83"H "0D82"H "0D81"H "0D80"H G15 G162 "0E83"H "0E82"H "0E81"H "0E80"H G16 G161 "0F83"H "0F82"H "0F81"H "0F80"H G17 G160 "1083"H "1082"H "1081"H "1080"H G18 G159 "1183"H "1182"H "1181"H "1180"H G19 G158 "1283"H "1282"H "1281"H "1280"H G20 G157 "1383"H "1382"H "1381"H "1380"H …… …… …… …… …… …… G14 G169 G168 "A883"H "A880"H "A881"H "A880"H G170 G167 "A983"H "A980"H "A981"H "A980"H G171 G166 "AA83"H "AA80"H "AA81"H "AA80"H G172 G165 "AB83"H "AB80"H "AB81"H "AB80"H G173 G164 "AC83"H "AC80"H "AC81"H "AC80"H G174 G163 "AD83"H "AD80"H "AD81"H "AD80"H G175 G162 "AE83"H "AE80"H "AE81"H "AE80"H G176 G161 "AF83"H "AF80"H "AF81"H "AF80"H … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … … DB DB … … 0 15 DB DB … … 0 15 DB DB … … 0 15 DB 0 "0003"H "0002"H "0001"H "0000"H "0103"H "0102"H "0101"H "0100"H "0203"H "0202"H "0201"H "0200"H "0303"H "0302"H "0301"H "0300"H "0403"H "0402"H "0401"H "0400"H "0503"H "0502"H "0501"H "0500"H "0603"H "0602"H "0601"H "0600"H "0703"H "0702"H "0701"H "0700"H "0803"H "0802"H "0801"H "0800"H "0903"H "0902"H "0901"H "0900"H "0A03"H "0A02"H "0A01"H "0A00"H "0B03"H "0B02"H "0B01"H "0B00"H "0C03"H "0C02"H "0C01"H "0C00"H "0D03"H "0D02"H "0D01"H "0D00"H "0E03"H "0E02"H "0E01"H "0E00"H "0F03"H "0F02"H "0F01"H "0F00"H "1003"H "1002"H "1001"H "1000"H "1103"H "1102"H "1101"H "1100"H "1203"H "1202"H "1201"H "1200"H "1303"H "1302"H "1301"H "1300"H …… DB DB … … 0 15 …… DB DB … … 0 15 …… DB DB … … 0 15 …… GS=0 GS=1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S/G Output "A803"H "A802"H "A801"H "A800"H "A903"H "A902"H "A901"H "A900"H "AA03"H "AA02"H "AA01"H "AA00"H "AB03"H "AB02"H "AB01"H "AB00"H "AC03"H "AC02"H "AC01"H "AC00"H "AD03"H "AD02"H "AD01"H "AD00"H "AE03"H "AE02"H "AE01"H "AE00"H "AF03"H "AF02"H "AF01"H "AF00"H 25 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary INSTRUCTIONS The S6D0110 uses the 16-bit bus architecture. Before the internal operation of the S6D0110 starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a highperformance microcomputer. The internal operation of the S6D0110 is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB15 to DB0), make up the S6D0110 instructions. There are nine categories of instructions that: Specify the index Read the status Control the display Control power management Process the graphics data Set internal GRAM addresses Transfer data to and from the internal GRAM Set grayscale level for the internal grayscale palette table Interface with the gate driver and power supply IC - Normally, instructions that write data are used the most. However, an auto-update of internal GRAM addresses after each data write can lighten the microcomputer program load. As instructions are executed in 0 cycles, they can be written in succession. 26 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary INSTRUCTION TABLE Table 16. Instruction table 1 Reg. No RS DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 R/W DB 9 DB 8 DB 7 DB 6 DB 5 IR 0 0 * * * * * * * * * ID6 ID5 SR 1 0 L7 L6 L5 L4 L3 L2 L1 L0 0 0 0 0 1 * * * * * * * * * * * 1 1 0 0 0 0 0 0 0 1 0 0 0 R01h 0 1 0 0 0 0 0 SM GS SS 0 0 0 R02h 0 1 0 0 0 0 B/C EOR 0 0 NW5 R03h 0 1 0 0 BT1 BT0 DC2 DC1 DC0 R04h 0 1 CAD 0 0 VRN4 VRN3 VRN2 VRN1 VRN0 0 0 0 R05h 0 1 0 0 0 BGR R06h 0 1 CP15 R00h FLD1 FDL0 SAP2 SAP1 SAP0 0 BT2 0 CP14 CP13 CP12 CP11 CP10 HWM 0 0 0 I/D1 CP9 CP8 CP7 CP6 CP5 DB 4 DB 3 DB 2 DB 1 DB 0 Register Name / Description Index / ID4 ID3 ID2 ID1 ID0 Sets the index register value Status read / 0 0 0 0 0 Reads the driving raster-row position Start oscillation / * * * * 1 Starts the oscillation circuit Device code read / 1 0 0 0 0 Read 0110H Driver output control / SM: gate driver division drive control NL4 NL3 NL2 NL1 NL0 GS: gate driver shift direction SS: source driver shift direction NL4-0: number of driving lines LCD-Driving-waveform control / FLD1-0: number of interlaced field NW4 NW3 NW2 NW1 NW0 B/C: LCD drive AC waveform NW5-0: number of n-raster-row of Cpattern Power control 1 / SAP2-0: BT2-0: AP2 AP1 AP0 SLP STB DC2-0: AP2-0: SLP: STB: Power control 2 / VRP4 VRP3 VRP2 VRP1 VRP0 CAD: VRN4-0: VRP4-0: Entry mode / BGR: I/D0 AM LG2 LG1 LG0 HWM: I/D1-0: AM: LG2-0: CP4 CP3 CP2 CP1 CP0 R07h 0 1 0 0 0 PT1 PT0 VLE2 VLE1 SPT 0 0 GON DTE CL REV D1 D0 R08h 0 1 0 0 0 0 FP3 FP2 FP0 0 0 0 0 BP3 BP2 BP1 BP0 R09h 0 1 0 0 0 0 BLP2 2 BLP2 1 BLP2 0 0 0 0 0 R0Bh 0 1 NO1 NO0 SDT1 SDT0 R0Ch 0 1 0 0 0 0 R0Dh 0 1 0 0 0 0 R0Eh 0 1 0 0 VCO MG R0Fh 0 1 0 0 0 FP1 BLP1 BLP1 BLP1 BLP1 BLP2 3 2 1 0 3 EQ1 EQ0 DIV1 DIV0 0 0 0 0 0 0 0 0 0 0 0 0 VRL3 VRL2 VRL1 VRL0 0 0 0 PON VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 VCM4 VCM3 VCM2 VCM1 VCM0 0 0 0 SCN4 SCN3 SCN2 SCN1 SCN0 0 0 0 0 0 RTN3 RTN2 RTN1 RTN0 0 VC2 VC1 VC0 VRH3 VRH2 VRH1 VRH0 Compare register / Display control / PT1-0: VLE2-1: SPT: GON: DTE: CL: REV: D1-0: Blank period control 1/ BP3-0: Back porch setting FP3-0: Front porch setting Blank period control 2/ Frame cycle control / NO1-0: SDT1-0: EQ1-0: DVI1-0: RTN3-0: Power control 3 / VC2-0: Power control 4 / VRL3-0: PON: VRH3-0: Power control 5 / VCOMG: VDV4-0: VCM4-0: Gate scan position / SCN4-0: scan starting position of gate 27 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Table 17. Instruction table 2 Reg. No RS DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 R/W DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 R11h 0 1 0 0 0 0 0 0 0 0 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 R14h 0 1 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 R15h 0 1 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 R16h 0 1 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 R17h 0 1 VEA7 R20h 0 1 WM15 WM14 WM13 WM12 WM11 WM10 WM9 R21h 0 1 AD15 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 1 WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 PKP 12 PKP 32 PKP 52 PRP 12 PKN 12 PKN 32 PKN 52 PRN 12 PKP 11 PKP 31 PKP 51 PRP 11 PKN 11 PKN 31 PKN 51 PRN 11 PKP 10 PKP 30 PKP 50 PRP 10 PKN 10 PKN 30 PKN 50 PRN 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKP 02 PKP 22 PKP 42 PRP 02 PKN 02 PKN 22 PKN 42 PRN 02 PKP 01 PKP 21 PKP 41 PRP 01 PKN 01 PKN 21 PKN 41 PRN 01 PKP 00 PKP 20 PKP 40 PRP 00 PKN 00 PKN 20 PKN 40 PRN 00 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 VSA7 VSA6 AD14 AD13 AD12 AD11 AD10 WM8 WM7 WM6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 WM5 WM4 WM3 WM2 WM1 WM0 R22h 1 1 R30h 0 1 0 0 0 0 0 R31h 0 1 0 0 0 0 0 R32h 0 1 0 0 0 0 0 R33h 0 1 0 0 0 0 0 R34h 0 1 0 0 0 0 0 R35h 0 1 0 0 0 0 0 R36h 0 1 0 0 0 0 0 R37h 0 1 0 0 0 0 0 28 Register Name / Description Vertical scroll control / VL7-0: 1st screen driving position / SE17-10: SS17-10 2nd screen driving position / SE27-20: SS27-20 Horizontal RAM Address position / HEA7-0: HSA7-0 Vertical RAM Address position / HEA7-0: HSA7-0 RAM write data mask / WM15-0: RAM address set / AD15-0: Write data to GRAM / WD15-0: Read data from GRAM / RD15-0: Gamma control 1 / Adjust Gamma voltage Gamma control 2 / Adjust Gamma voltage Gamma control 3 / Adjust Gamma voltage Gamma control 4 / Adjust Gamma voltage Gamma control 5 / Adjust Gamma voltage Gamma control 6 / Adjust Gamma voltage Gamma control 7 / Adjust Gamma voltage Gamma control 8 / Adjust Gamma voltage S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary INSTRUCTION DESCRIPTIONS Index The index instruction specifies the RAM control indexes (R00h to R3Fh). It sets the register number in the range of 00000 to 111111 in binary form. However, R40 to R44 are disabled since they are test registers. R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0 * * * * * * * * * ID6 ID5 ID4 ID3 ID2 ID1 ID0 Status Read The status read instruction read out the internal status of the IC. R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R 0 L7 L6 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 0 0 L7–0: Indicate the driving raster-row position where the liquid crystal display is being driven. Start Oscillation (R00h) The start oscillation instruction restarts the oscillator from the Halt State in the standby mode. After this instruction, wait at least 10 ms for oscillation to stabilize before giving the next instruction. (See the Standby Mode section) If this register is read forcibly, *0110H is read. R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 1 * * * * * * * * * * * * * * * 1 R 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 29 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Driver Output Control (R01h) R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 1 0 0 0 0 0 SM GS SS 0 0 0 NL4 NL3 NL2 NL1 NL0 GS: Selects the output shift direction of the gate driver. When GS = 0, G1 shifts to G176. When GS = 1, G176 shifts to G1. SM: Select the division drive method of the gate driver. When SM = 0, even/odd division is selected; SM = 1, upper/lower division drive is selected. Various connections between TFT panel and the IC can be supported with the combination of SM and GS bit. SS: Selects the output shift direction of the source driver. When SS = 0, S1 shifts to S396. When SS = 1, S396 shifts to S1. When SS = 0, <R><G><B> color is assigned from S1. When SS = 1, <R><G><B> color is assigned from S396. Re-write to the RAM when intending to change the SS bit. NL4–0: Specify number of lines for the LCD drive. Number of lines for the LCD drive can be adjusted for every eight raster-rows. GRAM address mapping does not depend on the setting value of the drive duty ratio. Select the set value for the panel size or higher. Table 18. NL bit and Drive Duty (SCN4-0=00000) NL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 NL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 NL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 NL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 NL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Display size Setting disabled 396 X 16 dots 396 X 24 dots 396 X 32 dots 396 X 40 dots 396 X 48 dots 396 X 56 dots 396 X 64 dots 396 X 72 dots 396 X 80 dots 396 X 88 dots 396 X 96 dots 396 X 104 dots 396 X 112 dots 396 X 120 dots 396 X 128 dots 396 X 136 dots 396 X 144 dots 396 X 152 dots 396 X 160 dots 396 X 168 dots 396 X 176 dots Number of LCD driver lines Setting disabled 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 Gate driver used Setting disabled G1 to G16 G1 to G24 G1 to G32 G1 to G40 G1 to G48 G1 to G56 G1 to G64 G1 to G72 G1 to G80 G1 to G88 G1 to G96 G1 to G104 G1 to G112 G1 to G120 G1 to G128 G1 to G136 G1 to G144 G1 to G152 G1 to G160 G1 to G168 G1 to G176 NOTE: Blank period (All gates output Vgoff level) have to be inserted after all gates are scanned. 30 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary LCD-Driving-Waveform Control (R02h) R/W W RS 1 DB15 0 DB14 0 DB13 0 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 FLD 1 FLD 0 B/C EOR 0 0 NW5 NW4 NW3 NW2 NW1 NW0 FLD1-0: These bits are for the set up of the interlaced driver’s n raster-row. See the following table and figure for the set up value and field raster-row and scanning method. Table 19. Association chart for scanning FLD1-0 and n raster-row FLD1 0 FLD0 0 Scanning method Set up disabled 0 1 1 field 1 0 Set up disabled 1 1 3 field (interlaced) G1 4 G3 4 G175 4 G2 4 ..... G174 4 G176 TFT Panel (a) When FLD1-0= 01(normal scanning) G1 4 G4 4 G7 4 .....4 G174 G2 4 G5 4 G8 4 .....4 G175 G3 4 G6 4 G9 4 .....4 G176 TFT Panel TFT Panel TFT Panel Frame 1/3 Frame 2/3 Frame 3/3 1 frame (b) When FLD1-0= 11(interlaced scanning) Figure 8. n raster-row interlaced scanning method B/C: When B/C = 0, a B-pattern waveform is generated and alternates in every frame for LCD drive. When B/C = 1, a n raster-row waveform is generated and alternates in each raster-row specified by bits EOR and NW4–NW0 in the LCD-driving-waveform control register (R02h). For details, see the n-raster-row Reversed AC Drive section. 31 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary EOR: When the C-pattern waveform is set (B/C = 1) and EOR = 1, the odd/even frame-select signals and the nraster-row reversed signals are EORed(Exclusive-OR) for alternating drive. EOR is used when the LCD is not alternated by combining the set values of the number of the LCD drive raster-row and the n raster-row. For details, see the n-raster-row Reversed AC Drive section. NW5–0: Specify the number of raster-rows that will alternate in the C-pattern waveform setting (B/C = 1). NW4– NW0 alternate for every set value + 1 raster-row, and the first to the 64th raster-rows can be selected. 32 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Power Control 1 (R03h) Power Control 2 (R04h) R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 1 0 0 BT0 DC2 DC1 DC0 AP2 AP1 AP0 SLP STB CAD 0 SAP 0 VRN 3 BT1 1 SAP 1 VRN 4 BT2 W SAP 2 0 VRN 2 VRN 1 VRN 0 0 0 0 VRP 4 VRP 3 VRP 2 VRP 1 VRP 0 SAP2-0: The amount of fixed current from the fixed current source in the operational amplifier for the source driver is adjusted. When the amount of fixed current is large, LCD driving ability and the display quality become high, but the current consumption is increased. Adjust the fixed current considering the display quality and the current consumption. During no display, when SAP2-0 = “000”, the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. SAP2 SAP1 SAP0 Amount of Current in Operational Amplifier 0 0 0 Operation of the operational amplifier and step-up circuit stops. 0 0 1 Small 0 1 0 Small or medium 0 1 1 Medium 1 0 0 Medium or large 1 0 1 Large 1 1 0 Setting Inhibited 1 1 1 Setting Inhibited BT2–0: The output factor of step-up is switched. Adjust scale factor of the step-up circuit by the voltage used. When the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. Adjust the frequency considering the display quality and the current consumption. BT2 BT1 BT0 VLOUT1 Output VLOUT2 Output Notes* 0 0 0 2 X Vci1 3 X Vci2 VLOUT2 = Vci1 X six times 0 0 1 2 X Vci1 4 X Vci2 VLOUT2 = Vci1 X eight times 0 1 0 3 X Vci1 3 X Vci2 VLOUT2 = Vci1 X nine times 0 1 1 3 X Vci1 2 X Vci2 VLOUT2 = Vci1 X six times 1 0 0 2 X Vci1 Vci1 + 2 X Vci2 VLOUT2 = Vci1 X five times 1 0 1 2 X Vci1 Vci1 + 3 X Vci2 VLOUT2 = Vci1 X seven times 1 1 0 Step-up stopped 3 X Vci2 VLOUT2 = Vci2 X three times 1 1 1 Step-up stopped 4 X Vci2 VLOUT2 = Vci2 X four times Notes: The step-up factors of VLOUT2 are derived from Vci1 when VLOUT1 and Vci2 are shorted. The conditions of VLOUT1 5.5V and VLOUT2 15.0V must be satisfied. 33 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary DC2-0: The operating frequency in the step-up circuit is selected. When the step-up operating frequency is high, the driving ability of the step-up circuit and the display quality become high, but the current consumption is increased. Adjust the frequency considering the display quality and the current consumption. DC2 DC1 DC0 Step-up Cycle in Step-up Circuit1 Step-up Cycle in Step-up Circuit 2/3/4 0 0 0 DCCLK / 1 DCCLK / 4 0 0 1 DCCLK / 2 DCCLK / 4 0 1 0 DCCLK / 4 DCCLK / 4 0 1 1 DCCLK / 2 DCCLK / 16 1 0 0 DCCLK DCCLK / 8 1 0 1 DCCLK / 2 DCCLK / 8 1 1 0 DCCLK / 4 DCCLK / 8 1 1 1 DCCLK / 4 DCCLK / 16 AP2– 0: The amount of fixed current in the operational amplifier for the power supply can be adjusted. When the amount of fixed current is large, the LCD driving ability and the display quality become high, but the current consumption is increased. Adjust the fixed current considering the display quality and the current consumption. During no display, when AP2-0 = “000”, the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. AP2 AP1 AP0 Amount of Current in Operational Amplifier 0 0 0 Operation of the operational amplifier and step-up circuit stops. 0 0 1 Small 0 1 0 Small or medium 0 1 1 Medium 1 0 0 Medium or large 1 0 1 Large 1 1 0 Setting Inhibited 1 1 1 Setting Inhibited SLP: When SLP = 1, the S6D0110 enters the sleep mode, where the internal display operations are halted except for the R-C oscillator, thus reducing current consumption. Only the following instructions can be executed during the sleep mode. − Power control (BT2 –0, DC3–0, AP2–0, SLP, STB, VC2-0, CAD, VR3-0, VRL3-0, VRH4-0, VCOMG, VDV4-0, and VCM4-0 bits) During the sleep mode, the other GRAM data and instructions cannot be updated although they are retained and G1 to G228 output is fixed to VSS level, and register set-up is protected (maintained). 34 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary STB: When STB = 1, the S6D0110 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses are supplied. For details, see the Standby Mode section. Only the following instructions can be executed during the standby mode. − − Standby mode cancel(STB = “0”) Start oscillation CAD: Set this bit according to the structure for the TFT-display retention volume. CAD = 0: Set this bit when the Cst retention volume is structured. In this case, Vgoff level is fixed to VgoffL level regardless of the Vcom alternating drive. CAD = 1: Set this bit when the Cadd retention volume is structured. At the Vcom alternating drive, the Vgoff voltage is output in the VgoffL voltage reference by the amount of Vcom alternating amplitude. VRP4-0: Control oscillation (positive polarity) of 64-grayscale. For details, see the Oscillation Adjusting Circuit section. VRN4-0: Control oscillation (negative polarity) of 64-grayscale. For details, see the Oscillation Adjusting Circuit section. 35 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Power Control 3 (R0Ch) Power Control 4 (R0Dh) Power Control 5 (R0Eh) R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VC2 VC1 Vc0 W 1 0 0 0 0 PON 0 VCO MG VDV 4 VRL 0 VDV 0 0 0 VRL 1 VDV 1 0 1 VRL 2 VDV 2 0 W VRL 3 VDV 3 0 0 0 VCM 4 VRH 3 VCM 3 VRH 2 VCM 2 VRH 1 VCM 1 VRH 0 VCM 0 VC2-0: Adjust reference voltage of VREG1, VREG2OUT and Vciout to optional rate of Vci. Also, when VC2 = “1”, it is possible to stop the internal reference voltage generator. This leads to optional power on for VREG1OUT/Vciout with REGP and VREG2OUT with REGN externally. Internal Reference Voltage (REGP) of Internal Reference Voltage (REGN) of VC2 VC1 VC0 VREG1OUT and Vciout VREG2OUT 0 0 0 0.92 X Vci 0.08 X Vci 0 0 1 0.83 X Vci 0.17 X Vci 0 1 0 0.73 X Vci 0.27 X Vci 0 1 1 0.68 X Vci 0.32 X Vci 1 0 0 Vci VSS 1 * * Stops generation of the internal reference voltages of VREG1OUT and Vciout (REGP can be input externally) Stops generation of the internal reference voltage of VREG2OUT (REGN can be input externally). Notes: Leave these settings open because the voltage other than that for halting the internal circuit is output for REGP and REGN. VRL3-0: Set magnification of amplification for VREG2OUT voltage (voltage for the reference voltage, VREG2 while generating Vgoffout.) It allows magnifying the amplification of REGN from 2 to 8.5 times. VRL VRL VRL VRL VREG2OUT Voltage VRL VRL VRL VRL VREG2OUT Voltage 3 2 1 0 3 2 1 0 0 0 0 0 -(Vci – REGN) X 3.0 1 0 0 0 -(Vci – REGN) X 6.5 0 0 0 1 -(Vci – REGN) X 3.5 1 0 0 1 -(Vci – REGN) X 7.0 0 0 1 0 -(Vci – REGN) X 4.0 1 0 1 0 -(Vci – REGN) X 7.5 0 0 1 1 -(Vci – REGN) X 4.5 1 0 1 1 -(Vci – REGN) X 8.0 0 1 0 0 -(Vci – REGN) X 5.0 1 1 0 0 -(Vci – REGN) X 8.5 0 1 0 1 -(Vci – REGN) X 5.5 1 1 0 1 -(Vci – REGN) X 9.0 0 1 1 0 -(Vci – REGN) X 6.0 1 1 1 0 -(Vci – REGN) X 9.5 0 1 1 1 Stopped 1 1 1 1 Stopped Notes: 1. These settings apply when the internal reference-voltage generation circuit is stopped and the VREG2OUT voltage is generated specifying REGN as the reference voltage. 2. Adjust the settings between the voltage set by (Vci – VC2-0) or the (Vci – REGN) voltage and VRL0 to VRL3 so that the VREG2OUT voltage is higher than –16.0 V. 3. The VREG2OUT voltage is the factor when Vci is the reference voltage. 36 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary PON: This is an operation-starting bit for the booster circuit 4. PON = 0 is to stop and PON = 1 to start operation. For further information about timing for adjusting to the PON = 1, please refer to the set up flow of power supply circuit. VRH3-0: Set the amplified factor of the VREG1OUT voltage (the voltage for the reference voltage, VREG2 while generating VgoffOUT). It allows to amplify from 1.45 to 2.85 times of REGN input voltage. VRH 3 VRH 2 VRH 1 VRH 0 VREG1OUT Voltage VRH 3 VRH 2 VRH 1 VRH 0 VREG1OUT Voltage 0 0 0 0 REGP X 1.45 times 1 0 0 0 REGP X 2.175 times 0 0 0 1 REGP X 1.55 times 1 0 0 1 REGP X 2.325 times 0 0 1 0 REGP X 1.65 times 1 0 1 0 REGP X 2.475 times 0 0 1 1 REGP X 1.75 times 1 0 1 1 REGP X 2.625 times 0 1 0 0 REGP X 1.80 times 1 1 0 0 REGP X 2.700 times 0 1 0 1 REGP X 1.85 times 1 1 0 1 REGP X 2.775 times 0 1 1 0 REGP X 1.90 times 1 1 1 0 REGP X 2.850 times 0 1 1 1 Stopped 1 1 1 1 Stopped Notes: 1. These settings apply when the internal reference-voltage generation circuit is stopped and the VREG1OUT voltage is generated specifying REGP as the reference voltage. 2. Adjust the settings between the voltage set by VC2-0 or the REGP voltage and VRH0 to VRH3 so that the VREG1OUT voltage is lower than 5.0 V. VCOMG: When VCOMG = 1, VcomL voltage can output to negative voltage (-5V). When VCOMG = 0, VcomL voltage becomes VSS and stops the amplifier of the negative voltage. Therefore, low power consumption is accomplished. Also, When VCOMG = 0 and when Vcom is driven in A/C, set up of the VDV4-0 is invalid. In this case, adjustment of Vcom/Vgoff A/C oscillation must be adjusted VcomH with VCM4-0. VDV4-0: Set the alternating amplitudes of Vcom and Vgoff at the Vcom alternating drive. These bits amplify Vcom and Vgoff 0.6 to 1.23 times the VREG1 voltage. When the Vcom alternation is not driven, the settings become invalid. VDV 4 VDV 3 VDV 2 VDV 1 VDV 0 Vcom Amplitude VDV 4 VDV 3 VDV 2 VDV 1 VDV 0 Vcom Amplitude 0 0 0 0 0 VREG1 X 0.60 1 0 0 0 1 VREG1 X 1.08 0 0 0 0 1 VREG1 X 0.63 1 0 0 1 0 VREG1 X 1.11 0 0 0 1 0 VREG1 X 0.66 1 0 0 1 1 VREG1 X 1.14 : : : : : : 1 0 1 0 0 VREG1 X 1.17 0 1 1 0 0 VREG1 X 0.96 1 0 1 0 1 VREG1 X 1.20 0 1 1 0 1 VREG1 X 0.99 1 0 1 1 0 VREG1 X 1.23 0 1 1 1 0 VREG1 X 1.02 1 0 1 1 1 Setting Inhibited 0 1 1 1 1 Setting Inhibited 1 1 * * * Setting Inhibited 1 0 0 0 0 VREG1 X 1.05 Notes : Adjust the settings between VREG1 and VDV0 to VDV4 so that the Vcom and Vgoff amplitudes are lower than 6.0 V. 37 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary VCM4-0: Set the VcomH voltage (a high-level voltage at the Vcom alternating drive). These bits amplify the VcomH voltage 0.4 to 0.98 times the VREG1 voltage. When VCOM4-0 = 1, the adjustment of the internal volume stops, and VcomH can be adjusted from VcomR by an external resistor. VCM4 VCM3 VCM2 VCM1 VCM0 VcomH Voltage 0 0 0 0 0 VREG1 X 0.40 times 0 0 0 0 1 VREG1 X 0.42 times 0 0 0 1 0 VREG1 X 0.44 times : : : : : 0 1 1 0 0 VREG1 X 0.64 times 0 1 1 0 1 VREG1 X 0.66 times 0 1 1 1 0 VREG1 X 0.68 times 0 1 1 1 1 The internal volume stops, and VcomH can be adjusted from VcomR by an external variable resistor. 1 0 0 0 0 VREG1 X 0.70 times 1 0 0 0 1 VREG1 X 0.72 times 1 0 0 1 0 VREG1 X 0.74 times : : : : : : 1 1 1 0 0 VREG1 X 0.94 times 1 1 1 0 1 VREG1 X 0.96 times 1 1 1 1 0 VREG1 X 0.98 times 1 1 1 1 1 The internal volume stops, and VcomH can be adjusted from VcomR by an external variable resistor. : Notes: Adjust the settings between VREG1 and VCM0 to VCM4 so that the VcomH voltage is lower than GVDD. 38 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Entry Mode (R05h) Compare Register (R06h) R/W W RS 1 DB15 0 DB14 0 DB13 0 DB12 BGR DB11 0 DB10 0 DB9 HWM DB8 0 DB7 0 DB6 0 DB5 I/D1 DB4 I/D0 DB3 AM DB2 LG2 DB1 LG1 DB0 LG0 W 1 CP15 CP14 CP13 CP12 CP11 CP10 CP9 CP8 CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0 The write date sent from the microcomputer is modified in the S6D0110 written to the GRAM. The display data in the GRAM can be quickly rewritten to reduce the load of the microcomputer software processing. For details, see the Graphics Operation Function section. HWM: When HWM=1, data can be written to the GRAM at high speed. In high-speed write mode, four words of data are written to the GRAM in a single operation at the writing to RAM four times. Write to RAM four times, otherwise the four words cannot be written to the GRAM. Thus, set the lower 2 bits to 0 when setting the RAM address. For details, see the High Speed RAM Write Mode section. I/D1-0: When I/D1-0 = 1, the address counter (AC) is automatically increased by 1 after the data is written to the GRAM. When I/D1-0 = 0, the AC is automatically decreased by 1 after the data is written to the GRAM. Automatic address counter updating is not performed when reading data from GRAM. The increment/decrement setting of the address counter by I/D1-0 is performed independently for the upper (AD15-8) and lower (AD7-0) addresses. The AM bit sets the direction of moving through the addresses when the GRAM is written. AM: Set the automatic update method of the AC after the data is written to the GRAM. When AM = 0, the data is continuously written in parallel. When AM = 1, the data is continuously written vertically. When window address range is specified, the GRAM in the window address range can be written to according to the I/D1-0 and AM settings. Table 20. Address Direction Setting I/D1-0=”00” H: decrement V: decrement I/D1-0=”01” H: increment V: increment 0000h 0000h I/D1-0=”10” H: decrement V: increment 0000h I/D1-0=”11” H: increment V: increment 0000h AM=0 Horizontal AF83h 0000h AF83h AF83h 0000h 0000h AF83h 0000h AM=1 Vertical AF83h AF83h AF83h AF83h 39 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary BGR: When 16-bit data is written to GRAM, bit-order of the data can be reversed by use of this bit. Therefore, bitorder of the data is set to be <R><G><B> when BGR is 0, <B><G><R> when BGR is 1. Please be aware that setting BGR to 1 will convert the order of the CP15-0 and WM15-0 bits in the same way. LG2– 0: Compare the data read from the GRAM by the microcomputer with the compare registers (CP7–0) by a compare/logical operation and write the results to GRAM. For details, see the Logical/Compare Operation Function. CP15–0: Set the compare register for the compare operation with the data read from the GRAM or written by the microcomputer. Write data sent from the micro computer (DB15-0) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 Logical/compare operation (LG2-0) Logical operation (with read data and write data) LG2-0 = “000”: Replace LG2-0 = “001”: OR LG2-0 = “010”: AND LG2-0 = “011”: EOR Write data mask* (WM15-0) Compare operation (with read data and write data) LG2-0 = “100”: Replacement of matched read data LG2-0 = “101”: Replacement of unmatched read data LG2-0 = “110”: Replacement of matched write data LG2-0 = “111”: Replacement of unmatched write data Write data mask (WM15-0) GRAM NOTE: The write data mask (WM11-0) is set by the register in the RAM Write Data Mask section Figure 9. Logical/compare operation Display Control (R07h) R/W W RS 1 DB15 0 DB14 0 DB13 0 DB12 PT1 DB11 PT0 DB10 VLE2 DB9 VLE1 DB8 SPT DB7 0 DB6 0 DB5 GON DB4 DTE DB3 CL DB2 REV DB1 D1 DB0 D0 PT1-0: Normalize the source outputs when non-displayed area of the partial display is driven. For details, see the Screen-division Driving Function section. VLE2–1: When VLE1 = 1, a vertical scroll is performed in the 1st screen. When VLE2 = 1, a vertical scroll is performed in the 2nd screen. Vertical scrolling on the two screens cannot be controlled at the same time. VLE2 0 0 1 1 40 VLE1 0 1 0 1 2nd Screen Fixed display Fixed display Scroll display Setting disabled 1st Screen Fixed display Scroll display Fixed display Setting disabled S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary SPT: When SPT = 1, the 2-division LCD drive is performed. For details, see the Screen-division Driving Function section. GON: Gate off level is set to be VSS when GON = 0. When GON= 0 and DISPTMG= 0, G1 to G176 output is fixed to VSS level. When GON= 1, G1 to G176 output is fixed to VGH or Vgoff level. See the instruction set up flow for further description on the display on/off flow. GON 0 1 Gate output VGH/VSS VGH/Vgoff DTE: DISPTMG output is fixed to VSS when DTE = 0. DTE 0 1 DISPTMG output Halt (VSS) Operation (VDD/VSS) CL: When CL = 1, number of display is 8-color mode. For details, see the 8-color Display Mode. CL 0 1 Number of display colors 65,536 colors 8 colors 41 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary REV: Displays all character and graphics display sections with reversal when REV = 1. For details, see the Reversed Display Function section. Since the grayscale level can be reversed, display of the same data is enabled on normally white and normally black panels. 1) Combination with the partial display REV 0 1 GRAM data 16’h0000 : 16’hFFFF 16’h0000 : 16’hFFFF Display data Vcom=L V63 : V0 V0 : V63 Vcom=H V0 : V63 V63 : V0 Source output level Non-display area PT1-0=(0,1) PT1-0=(1,0) Vcom=L Vcom=H Vcom=L Vcom=H PT1-0=(1,1) Vcom=L Vcom=H V63 V0 VSS VSS Hi-z Hi-z V63 V0 VSS VSS Hi-z Hi-z 2) Combination with the D1-0 REV 0 1 GRAM data 16’h0000 : 16’hFFFF 16’h0000 : 16’hFFFF D1-0=(1,1) Vcom=L Vcom=H V63 V0 : : V0 V63 V0 V63 : : V63 V0 Source output level D1-0=(1,0) D1-0=(0,1) Vcom=L Vcom=H Vcom=L Vcom=H D1-0=(0,0) Vcom=L Vcom=H V63 V0 VSS VSS VSS VSS V63 V0 VSS VSS VSS VSS D1– 0: Display is on when D1 = 1 and off when D1 = 0. When off, the display data remains in the GRAM, and can be displayed instantly by setting D1 = 1. When D1 is 0, the display is off with the entire source outputs set to the VSS level. Because of this, the S6D0110 can control the charging current for the LCD with AC driving. Control the display on/off while control GON and DTE. For details, see the Instruction Set Up Flow. When D1–0 = 01, the internal display of the S6D0110 is performed although the display is off. When D1-0 = 00, the internal display operation halts and the display is off. D1 D0 Source output S6D0110 internal display operation Master/slave signal (CL1, FLM, M, DISPTMG) Halt Operate Operate Operate 0 0 VSS Halt 0 1 VSS Operate 1 0 Unlit display Operate 1 1 Display Operate Notes: 1. Writing from the microcomputer to the GRAM is independent from D1–0. 2. In sleep and standby mode, D1–0 = 00. However, the register contents of D1–0 are not modified. 42 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Blanking period control 1 (R08h) Blanking period control 2 (R09h) R/W W RS 1 DB15 0 DB14 0 DB13 0 DB12 0 DB11 FP3 DB10 FP2 DB9 FP1 DB8 FP0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 BP3 DB2 BP2 DB1 BP1 DB0 BP0 W 1 0 0 0 0 BLP1 3 BLP1 2 BLP1 1 BLP1 0 BLP2 3 BLP2 2 BLP2 1 BLP2 0 0 0 0 0 The blanking period in the front and end of the display area can be defined using this register. When N-raster-row is driving, a blank period is inserted after all screens are drawn. Front and Back porch can be adjusted using FP3-0 and BP3-0 bits (R08h). In interlace drive mode, Blank period can be adjusted using BLP130 and BLP23-0 bit (R09h).the GRAM can be quickly rewritten to reduce the load of the microcomputer software processing. For details, see the Graphics Operation Function section. FP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Blanking period 0 raster-row 1 raster-row 2 raster-row 3 raster-row 4 raster-row 5 raster-row 6 raster-row 7 raster-row 8 raster-row 9 raster-row 10 raster-row 11raster-row 12 raster-row 13 raster-row 14 raster-row 15 raster-row BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Blanking period 0 raster-row 1 raster-row 2 raster-row 3 raster-row 4 raster-row 5 raster-row 6 raster-row 7 raster-row 8 raster-row 9 raster-row 10 raster-row 11raster-row 12 raster-row 13 raster-row 14 raster-row 15 raster-row BLP13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BLP12 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BLP11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BLP10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Blanking period 0 raster-row 1 raster-row 2 raster-row 3 raster-row 4 raster-row 5 raster-row 6 raster-row 7 raster-row 8 raster-row 9 raster-row 10 raster-row 11raster-row 12 raster-row 13 raster-row 14 raster-row 15 raster-row BLP23 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BLP22 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BLP21 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BLP20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Blanking period 0 raster-row 1 raster-row 2 raster-row 3 raster-row 4 raster-row 5 raster-row 6 raster-row 7 raster-row 8 raster-row 9 raster-row 10 raster-row 11raster-row 12 raster-row 13 raster-row 14 raster-row 15 raster-row 43 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Frame Cycle Control (R0Bh) R/W W RS 1 DB15 NO1 DB14 NO0 DB13 SDT1 DB12 SDT0 DB11 EQ1 DB10 EQ0 DB9 DIV1 DB8 DIV0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 RTN3 DB2 RTN2 DB1 RTN1 DB0 RTN0 RTN3-0: Set the 1H period. RTN3 0 0 0 . . . 1 1 RTN2 0 0 0 . . . 1 1 RTN1 0 0 1 . . . 1 1 RTN0 0 1 0 . . . 0 1 Clock cycles per raster row 16 17 18 . . . 30 31 DIV1-0: Set the division ratio of clocks for internal operation (DIV1-0). Internal operations are driven by clocks, which are frequency divided according to the DIV1-0 setting. Frame frequency can be adjusted along with the 1H period (RTN3-0). When changing number of the drive cycle, adjust the frame frequency. For details, see the Frame Frequency Adjustment Function section. DIV1 0 0 1 1 DIV0 0 1 0 1 Division Ratio 1 2 4 8 Internal operation clock frequency fosc/1 fosc/2 fosc/4 fosc/8 *fosc = R-C oscillation frequency EQ1-0: EQ period is sustained for the number of clock cycle which is set on EQ1-0. When VcomL<0, set these bits as “00” for preventing the abnormal function. EQ1 0 0 1 1 Frame Frequency = EQ0 0 1 0 1 fOSC Clock cycles per raster-row x division ratio x (Line+B) fOSC : R-C oscillation frequency Line: Number of raster-rows (NL bit) Clock cycles per raster-row: RTN bit Division ratio: DIV bit B: Blank period(Back porch + Front Porch) Figure 10. Formula for the frame frequency 44 EQ period No EQ 1 clock cycle 2 clock cycle 3 clock cycle [Hz] S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary SDT1-0: Set delay amount from gate edge (end) to source output. SDT1 0 0 1 1 SDT0 0 1 0 1 Delay amount of the source output 1 clock cycle 2 clock cycle 3 clock cycle 4 clock cycle 1H period 1H period Gn Sn EQ Delay amount of the source output Equalizing period Figure 11. Set Delay from Gate Output to Source Output NO1-0: Set amount of non-overlay for the gate output. NO1 0 0 1 1 NO0 0 1 0 1 1H period Amount of non-overlab 0 clock cycle 4 clock cycle 6 clock cycle 8 clock cycle 1H period CL1 Gn Gn+1 Non-overlap period Figure 12. Non-overlap Period 45 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Gate Scan Position (R0fh) R/W W RS 1 DB15 NO1 DB14 0 DB13 0 DB12 0 DB11 0 DB10 0 DB9 0 DB8 0 DB7 0 DB6 0 DB5 0 DB4 SCN4 DB3 SCN3 DB2 SCN2 DB1 SCN1 SCN 4-0: Set the scanning starting position of the gate driver. SCN4 SCN3 SCN2 SCN1 SCN0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 1 1 0 0 1 : : 1 0 0 0 1 0 : : 1 0 1 G1 Scanning start position GS=0 GS=1 G1 G176 G9 G168 G17 G160 : : : : G153 G24 G161 G16 G169 G8 G1 G16 G17 G160 G161 G160 G161 G176 G176 GS = 0 NL = 10010 SCN4-0 = 00000 GS = 1 NL = 10010 SCN4-0 = 00010 Note: Set NL4-0 on the gate scan end that does not exceed value 176 Figure 13. Relationship between NL and SCN set up value 46 DB0 SCN0 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Vertical Scroll Control (R11h) R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 1 0 0 0 0 0 0 0 0 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 VL7-0: Specify scroll length at the scroll display for vertical smooth scrolling. Any raster-row from the first to 176 th can be scrolled for the number of the raster-row. After 176th raster-row is displayed, the display restarts from the first raster-row. The display-start raster-row (VL7-0) is valid when VLE1 = 1 or VLE2 = 1. The raster-row display is fixed when VLE2-1 = 00. VL7 0 0 0 VL6 0 0 0 VL5 0 0 0 VL4 0 0 0 VL3 0 0 0 VL2 0 0 0 VL1 0 0 1 VL0 0 1 0 1 1 1 1 0 1 Scroll length 0 raster-row 1 raster-row 2 raster-row . . . 174 raster-row 175 raster-row . . . 1 0 1 0 1 1 0 1 0 1 Note: Don’t set any higher raster-row than 175 (“AF”H) 1st Screen Driving Position (R14h) 2nd Screen Driving Position (R15h) R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W W 1 1 SE17 SE27 SE16 SE26 SE15 SE25 SE14 SE24 SE13 SE23 SE12 SE22 SE11 SE21 SE10 SE20 SS17 SS27 SS16 SS26 SS15 SS25 SS14 SS24 SS13 SS23 SS12 SS22 SS11 SS21 SS10 SS20 SS17–10: Specify the driving start position for the first screen in a line unit. The LCD driving starts from the ‘set value +1’ common driver. SE17–10: Specify the driving end position for the first screen in a line unit. The LCD driving is performed to the 'set value + 1' gate driver. For instance, when SS17–10 = 07h and SE17–10 = 10h are set, the LCD driving is performed from G8 to G17, and black display driving is performed for G1 to G7, G18, and others. Ensure that SS17–10 ≤ SE17–10 ≤ AFh. For details, see the Screen-division Driving Function section. SS27–10: Specify the driving start position for the second screen in a line unit. The LCD driving starts from the 'set value + 1' gate driver. The second screen is driven when SPT = 1. SE27–20: Specify the driving end position for the second screen in a line unit. The LCD driving is performed to the 'set value + 1' gate driver. For instance, when SPT = 1, SS27–20 = 20h, and SE27– 20 = AFh are set, the LCD driving is performed from G33 to G80. Ensure that SS17–10 ≤ SE17–10 ≤ SS27–20 ≤ SE27– 20 ≤ AFh. For details, see the Screen-division Driving Function section. 47 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Horizontal Ram Address Position (R16h) Vertical Ram Address Position (R17h) R/W W RS 1 DB15 HEA 7 DB14 HEA 6 DB13 HEA 5 DB12 HEA 4 DB11 HEA 3 DB10 HEA 2 DB9 HEA 1 DB8 HEA 0 DB7 HSA 7 DB6 HSA 6 DB5 HSA 5 DB4 HSA 4 DB3 HSA 3 DB2 HSA 2 DB1 HSA 1 DB0 HSA 0 W 1 VEA 7 VEA 6 VEA 5 VEA 4 VEA 3 VEA 2 VEA 1 VEA 0 VSA 7 VSA 6 VSA 5 VSA 4 VSA 3 VSA 2 VSA 1 VSA 0 HSA7-0/HEA7-0: Specify the horizontal start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by HEA 7-0 from the address specified by HSA7-0. Note that an address must be set before RAM is written. Ensure 00h ≤ HSA7-0 ≤ HEA7-0 ≤ 83h. VSA7-0/VEA7-0: Specify the vertical start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by VEA7-0 from the address specified by VSA7-0. Note that an address must be set before RAM is written. Ensure 00h ≤ VSA7-0 ≤ VEA7-0 ≤ AFh. HEA HSA 0000H VSA Window address setting range Window address “00”h £ HSA7-0 ≤ HEA7-0 ≤ “83”h “00”h ≤ VSA7-0 ≤ VEA7-0 ≤ “AF”h VEA GRAM address space AF83H NOTE: 1. Ensure that the window address area is within the GRAM address space 2. In high-speed write mode, data are written to GRAM in four-words. Thus, dummy write operations should be inserted depending on the window address area. For details, see the High-Speed Burst RAM Write Function section Figure 14. Window address setting range 48 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary RAM Write Data Mask (R20h) R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 1 WM15 WB14 WM13 WM12 WM11 WM10 WM9 WM8 WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0 WM15–0: In writing to the GRAM, these bits mask writing in a bit unit. When WM15 = 1, this bit masks the write data of DB15 and does not write to the GRAM. Similarly, the WM14 to 0 bits mask the write data of DB14 to 0 in a bit unit. For details, see the Graphics Operation Function section. RAM Address Set (R21h) R/W W RS 1 DB15 AD15 DB14 AD14 DB13 AD13 DB12 AD12 DB11 AD11 DB10 AD10 DB9 AD9 DB8 AD8 DB7 AD7 DB6 AD6 DB5 AD5 DB4 AD4 DB3 AD3 DB2 AD2 DB1 AD1 DB0 AD0 AD15–0: Initially set GRAM addresses to the address counter (AC). Once the GRAM data is written, the AC is automatically updated according to the AM and I/D bit settings. This allows consecutive accesses without resetting address. Once the GRAM data is read, the AC is not automatically updated. GRAM address setting is not allowed in the standby mode. Ensure that the address is set within the specified window address AD15 to AD0 “0000H” to “0083”H “0100H” to “0183”H “0200H” to “0283”H “0300H” to “0383”H : : : “AC00H” to “AC83”H “AD00H” to “AD83”H “AE00H” to “AE83”H “AF00H” to “AF83”H GRAM setting Bitmap data for G1 Bitmap data for G2 Bitmap data for G3 Bitmap data for G4 : : : Bitmap data for G173 Bitmap data for G174 Bitmap data for G175 Bitmap data for G176 49 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Write Data to Gram (R22h) R/W W RS 1 DB15 WD15 DB14 WD14 DB13 WD13 DB12 WD12 DB11 WD11 DB10 WD10 DB9 WD9 DB8 WD8 DB7 WD7 DB6 WD6 DB5 WD5 DB4 WD4 DB3 WD3 DB2 WD2 DB1 WD1 DB0 WD0 WD15-0: Write 16-bit data to the GRAM. This data selects the grayscale level. After a write, the address is automatically updated according to AM and I/D bit settings. During the standby mode, the GRAM cannot be accessed. DB15 WD15 DB14 WD14 DB13 WD13 DB12 WD12 DB11 WD11 DB10 WD10 DB9 WD9 DB8 WD8 DB7 WD7 DB6 WD6 DB5 WD5 DB4 WD4 DB3 WD3 DB2 WD2 DB1 WD1 DB0 WD0 ↓ R4 ↓ R3 ↓ R2 ↓ R1 ↓ R0 ↓ G5 ↓ G4 ↓ G3 1 pixel ↓ G2 ↓ G1 ↓ G0 ↓ B4 ↓ B3 ↓ B2 ↓ B1 ↓ B0 Figure 15. Write data to GRAM Table 21. GRAM Data and Grayscale Level GRAM data setup Selected grayscale N P GRAM data setup Selected grayscale N P GRAM data setup Selected grayscale N P GRAM data setup G R/B G R/B G R/B 000000 00000 V0 V63 010000 01000 V16 V47 100000 - V32 V31 110000 - V48 V15 000001 000010 00001 V1 V2 V62 V61 010001 010010 01001 V17 V18 V46 V45 100001 100010 10000 - V33 V34 V30 V29 110001 110010 11000 - V49 V50 V14 V13 000011 - V3 V60 010011 - V19 V44 100011 10001 V35 V28 110011 11001 V51 V12 000100 000101 00010 - V4 V5 V59 V58 010100 010101 01010 - V20 V21 V43 V42 100100 100101 10010 V36 V37 V27 V26 110100 110101 11010 V52 V53 V11 V10 000110 00011 V6 V57 010110 01011 V22 V41 100110 - V38 V25 110110 - V54 V9 000110 001000 00100 V7 V8 V56 V55 010110 011000 01100 V23 V24 V40 V39 100110 101000 10011 - V39 V40 V24 V23 110110 111000 11011 - V55 V56 V8 V7 001001 - V9 V54 011001 - V25 V38 101001 10100 V41 V22 111001 11100 V57 V6 001010 001011 00101 - V10 V11 V53 V52 011010 011011 01101 - V26 V27 V37 V36 101010 101011 10101 V42 V43 V21 V20 111010 111011 11101 V58 V59 V5 V4 001100 00110 V12 V51 011000 01100 V28 V35 101100 - V44 V19 111100 - V60 V3 001101 001100 00110 V13 V14 V50 V49 011001 011010 01101 V29 V30 V34 V33 101101 101100 10110 - V45 V46 V18 V17 111101 111110 11110 - V61 V62 V2 V1 001101 - V15 V48 011011 - V31 V32 101101 10111 V47 V16 111111 11111 V63 V0 50 G R/B Selected grayscale N P S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Read Data from GRAM (R22h) R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R 1 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 RD11–0: Read 16-bit data from the GRAM. When the data is read to the microcomputer, the first-word read immediately after the GRAM address setting is latched from the GRAM to the internal read-data latch. The data on the data bus (DB15– 0) becomes invalid and the second-word read is normal. When bit processing, such as a logical operation, is performed within the S6D0110, only one read can be processed since the latched data in the first word is used. Sets the I/D, AM, HSA/HEA, and VSA/VEA bits Sets the I/D, AM, HSA/HEA, and VSA/VEA bits Address: N set Address: N set First word Dummy read (invalid data) GRAM -> Read data latch First word Second word Read (data of address N) Read data latch -> DB15-0 Second word Address: M set Dummy read (invalid data) GRAM -> Read data latch Write (data of address N) DB15-0 -> GRAM Automatic address update: N+α First word Dummy read (invalid data) GRAM -> Read data latch First word Second word Read (data of address M) Read-data latch -> DB15-0 Second word i) Data read to the microcomputer Dummy read (invalid data) GRAM -> Read data latch Write (data of address N+α) DB15-0 -> GRAM ii) Logical operation processing in S6D0110 Figure 16. GRAM read sequence 51 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Gamma Control (R30h To R37h) R/W RS DB15 DB14 DB13 DB12 DB11 W 1 0 0 0 0 0 W 1 0 0 0 0 0 W 1 0 0 0 0 0 W 1 0 0 0 0 0 W 1 0 0 0 0 0 W 1 0 0 0 0 0 W 1 0 0 0 0 0 W 1 0 0 0 0 0 DB10 PKP 12 DB9 PKP 11 DB8 PKP 10 PKP 32 PKP 52 PRP 12 PKP 31 PKP 51 PRP 11 PKP 30 PKP 50 PRP 10 PKN 12 PKN 32 PKN 52 PKN 11 PKN 31 PKN 51 PKN 10 PKN 30 PKN 50 PRN 12 PRN 11 PRN 10 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKP52–00: Gamma micro adjustment register for the positive polarity output PRP12-00: Gradient adjustment register for the positive polarity output PKN52-00: Gamma micro adjustment register for the negative polarity output PRN12-00: Gradient adjustment register for the negative polarity output For details, see the Gamma Adjustment Function. 52 DB2 PKP 02 DB1 PKP 01 DB0 PKP 00 PKP 22 PKP 42 PRP 02 PKP 21 PKP 41 PRP 01 PKP 20 PKP 40 PRP 00 PKN 02 PKN 22 PKN 42 PKN 01 PKN 21 PKN 41 PKN 00 PKN 20 PKN 40 PRN 02 PRN 01 PRN 00 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary RESET FUNCTION The S6D0110 is internally initialized by RESET input. The reset input must be held for at least 1 ms. Do not access the GRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms). Instruction Set Initialization 1. 2. 3. 4. Start oscillation executed Driver output control (NL4–0 = 10101, SS = 0, CS = 0) B-pattern waveform AC drive (FLD1-0 = 01, B/C = 0, EOR = 0, NW5–0 = 00000) Power control 1 (SAP2-0 = 000, BT2-0 = 000, DC2–0 = 000, AP2–0 = 000: LCD power off, SLP = 0, STB = 0: Standby mode off) 5. Power control 2 (CAD = 0, VRN4-0 = 00000, VRP4-0 = 00000) 6. Entry mode set (HWM = 0, I/D1-0 = 11: Increment by 1, AM = 0: Horizontal move, LG2–0 = 000: Replace mode) 7. Compare register (CP15–0: 0000000000000000) 8. Display control (PT1-0 = 00, VLE2– 1 = 00: No vertical scroll, SPT = 0, GON = 0, DTE = 0, CL = 0: 65536 color mode, REV = 0, D1–0 = 00: Display off) 9. Display control (FP3-0=0101, BP3-0=0011, BLP13-0=0010, BLP23-0=0010) 10. Frame cycle control (NO1-0 = 00, SDT1-0 = 00, EQ1-0 = 00: no equalizer, DIV1-0 = 00: 1-divided clock, RTN3-0 = 0000: 16 clock cycle in 1H period) 11. Power control 3 (VC2-0 = 000) 12. Power control 4 (VRL3-0 = 0000, PON=0, VRH3-0 = 0000) 13. Power control 5 (VCOMG = 0, VDV4-0 = 00000, VCM4-0 = 00000) 14. Gate scanning starting position (SCN4-0 = 00000) 15. Vertical scroll (VL7–0 = 0000000) 16. 1st screen division (SE17-10 = 11111111, SS17-10 = 00000000) 17. 2nd screen division (SE27-20 = 11111111, SS27-20 = 00000000) 18. Horizontal RAM address position (HEA7-0 = 10000011, HSA7-0 = 00000000) 19. Vertical RAM address position (VEA7-0 = 10101111, VSA7-0 = 00000000) 20. RAM write data mask (WM15– 0 = 0000h: No mask) 21. RAM address set (AD15– 0 = 0000h) 22. Gamma control (PKP02– 00 = 000, PKP12–10 = 000, PKP22–20 = 000, PKP32– 30 = 000, PK42–40 = 000, PKP52– 50 = 000, PRP02–00 = 000, PRP12– 10 = 000) (PKN02– 00 = 000, PKN12–10 = 000, PKN22–20 = 000, PKN32– 30 = 000, PKN42– 40 = 000, PKN52–50 = 000, PRN02–00 = 000, PRN12–10 = 000) GRAM Data Initialization GRAM is not automatically initialized by reset input but must be initialized by software while display is off (D1– 0 = 00). Output Pin Initialization 1. LCD driver output pins (Source output) : Output VSS level (Gate output) : Output Vgoff level 2. Oscillator output pin (OSC2): Outputs oscillation sign 53 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary VOLTAGE REGULATION FUNCTION The S6D0110 have internal voltage regulator. Voltage regulation function is controlled by PregB pin. If PregB= “H”, voltage regulation is stopped. PregB= “L” enables internal voltage regulation function. By use of this function, internal logic circuit damage can be prohibited. Furthermore, power consumption also be obtained. Detailed function description and application setup is described in the following diagram. Internal VDD Level Shifter INPUT INTERNAL LOGIC GND PREGB VDD3 (External Power) Range: 2.5~3.3V PregB= 'L' : REGULATOR ON VOLTAGE REGULATOR RVDD Internal VDD (1.9V) VDD (a) Voltage regulation function enabled Internal VDD Level Shifter INPUT PREGB VDD3 VOLTAGE REGULATOR PregB= 'H' : REGULATOR OFF RVDD VDD (External Power) 1.8~2.5V Internal VDD (b) Voltage regulation function disabled Figure 13. Voltage regulation function 54 INTERNAL LOGIC S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary SYSTEM INTERFACE System interface mode of S6D0110 can be fixed by use of IM2/1/0 pin. Instruction setting and GRAM access is executed via system interface. Table 22. IM bits and System Interface IM2 0 0 0 0 1 1 * IM1 0 0 1 1 0 1 * IM0 0 1 0 1 * * * System Interface 68-system 16-bit interface 68-system 8-bit interface 80-system 16-bit interface 80-system 8-bit interface Serial peripheral interface (SPI) Setting disabled Setting disabled DB Pin DB15 ~ 0 DB15 ~ 8 DB15 ~ 0 DB15 ~ 8 DB1 ~ 0 - PARALLEL DATA TRANSFER 16-BIT BUS INTERFACE Setting the IM2/1/0 (interface mode) to the VSS/VSS/VSS level allows 68-system E-clock-synchronized 16-bit parallel data transfer. Setting the IM2/1/0 to the VSS/VDD3/VSS level allows 80-system 16-bit parallel data transfer. When the number of bus or the mounting area is limited, use an 8-bit bus interface. CSn CSB A1 MPU RS /WR /WR /RD /RD D15-D0 16 S6D0110 DB15-DB0 Figure 17. Interface to 16-bit microcomputer 55 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary 8-BIT BUS INTERFACE Setting the IM2/1/0 (interface mode) to the VSS/VSS/VDD3 level allows 68-system E-clock-synchronized 8-bit parallel data transfer using pins DB15–DB8. Setting the IM2/1/0 to the VSS/VDD3/VDD3 level allows 80-system 8bit parallel data transfer. The 16-bit instructions and RAM data are divided into upper/lower eight bits and the transfer starts from the upper eight bits. Fix unused pins DB7– DB0 to the VDD3 or VSS level. Note that the upper bytes must also be written when the index register is written. MPU CSn CSB A1 RS /WR /WR /RD /RD D7-D0 S6D0110 DB15-DB8 8 DB7-DB0 8 Figure 18. Interface to 8-bit microcomputer Note: The S6D0110 supports the transfer synchronization function, which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00H instruction four times. The next transfer starts from the upper eight bits. Executing synchronization function periodically can recover any runaway in the display system RS R/W E DB15 to DB8 Upper or Lower “00 ”H “00”H “00”H “00”H (1) (2) (3) (4) Upper Lower 8-bit transfer synchronization Figure 19. 8-bit transfer synchronization 56 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary SERIAL DATA TRANSFER Setting the IM 2/1 pin to the VDD3/VSS level allows serial peripheral interface (SPI) transfer, using the chip select line (CS*), serial transfer clock line (SCL), serial input data (SDI), and serial output data (SDO). For a serial interface, the IM0/ID pin function uses an ID pin. If the chip is set up for serial interface, the DB15-2 pins that are not used must be fixed at VDD3 or VSS. The S6D0110 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It ends serial data transfer at the rising edge of CS* input. The S6D0110 is selected when the 6-bit chip address in the start byte matches the 6-bit device identification code that is assigned to the S6D0110. When selected, the S6D0110 receives the subsequent data string. The LSB of the identification code can be determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be assigned to a single S6D0110 because the seventh bit of the start byte is used as a register select bit (RS): that is, when RS = 0, data can be written to the index register or status can be read, and when RS = 1, an instruction can be issued or data can be written to or read from RAM. Read or write is selected according to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is 0, and is transmitted when the R/W bit is 1. After receiving the start byte, the S6D0110 receives or transmits the subsequent data byte-by-byte. The data is transferred with the MSB first. All S6D0110 instructions are 16 bits. Two bytes are received with the MSB first (DB15 to 0), then the instructions are internally executed. After the start byte has been received, the first byte is fetched as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the instruction. Four bytes of RAM read data after the start byte are invalid. The S6D0110 starts to read correct RAM data from the fifth byte. Table 23. Start Byte Format Transfer bit S Start byte format Transfer start 1 2 0 1 3 4 Device ID code 1 1 5 6 0 ID 7 RS 8 R/W NOTE: ID bit is selected by the IM0/ID pin. Table 24. RS and R/W Bit Function RS 0 0 1 1 RW 0 1 0 1 Function Set index register Read status Writes instruction or RAM data Reads instruction or RAM data 57 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary A) Timing Basic Data Transfer through Clock Synchronized Serial Bus Interface Transfer start Transfer end CS* (input) SCL (input) SDI (input) 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 1 1 0 ID R RW DB 15 DB 14 DB 13 DB 12 DB 11 14 DB 10 15 DB 9 16 DB 8 17 18 19 20 21 22 23 24 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 DB 2 DB 1 DB 0 RS R/W Device ID Index register setting instruction RAM data write Start byte SDO (output) DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 Status read instruction read RAM data read B) Timing of Consecutive Data-Transfer through Clock-synchronized serial Bus Interface CS* (input) 1 SCL (input) 2 3 4 SDI (input) 5 6 7 8 Start byte 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Instruction 1: upper Instruction 2: lower Instruction 2: upper Start Instruction 1: execution time End NOTE: The first byte after the start byte is always the upper eight bits. C) RAM-Data Read-Transfer Timing CS* (input) SCL (input) Start byte RS=1 R/W=1 SDI (input) SDO (output) Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read: upper 8-bits RAM read: lower 8-bits Start End NOTE: 5-byte of RAM read data after the start byte are invalid. The S6D0110 starts to read the correct RAM data from sixth byte Figure 20. Procedure for transfer on clock synchronized serial bus interface 58 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary D) Status Read/Instruction Read CS* (input) Start byte RS=1 R/W=1 SDI (input) SDO (output) Dummy read 1 Start Status read upper 8-bit Status read lower 8-bit End NOTE: 2-byte of the RAM read after the start byte is invalid. The S6D0110 starts to read the correct RAM data from the third data. Figure 21. Procedure for transfer on clock synchronized serial bus interface (continued) 59 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary HIGH-SPEED BURST RAM WRITE FUNCTION The S6D0110 has a high-speed burst RAM-write function that can be used to write data to RAM in one-fourth the access time required for an equivalent standard RAM-write operation. This function is especially suitable for applications that require the high-speed rewriting of the display data, for example, display of color animations, etc. When the high-speed RAM-write mode (HWM) is selected, data for writing to RAM is once stored to the S6D0110 internal register. When data is selected four times per word, all data is written to the on-chip RAM. While this is taking place, the next data can be written to an internal register so that high-speed and consecutive RAM writing can be executed for animated displays, etc. a) High-speed burst RAM write operation flow Microcomputer 16 Address counter (AC) Register 1 Register 2 Register 3 Register 4 64 16 “0000”H “0001”H “0002”H “0003”H GRAM b) Example of the operation of high-speed consecutive writing to RAM CS* (input) 1 2 3 4 1 2 3 4 1 2 3 4 E (input) DB15-0 (input/output) Index (R22) RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM data data data data data data data data data data data data 1 2 3 4 5 6 7 8 9 10 11 12 RAM write execution time RAM write data (64 bits) RAM address (AC 15-0) RAM data 1 to 4 “0000”H RAM write execution time Index RAM write execution time* RAM data 5 to 8 RAM data 9 to 12 “0004”H “0008”H “000A”H Figure 22. Example of the operation of high-speed consecutive writing to RAM 60 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary When high-speed write mode is used, note the following. 1. The logical and compare operations cannot be used. 2. Data is written to RAM each four words. When an address is set, the lower two bits in the address must be set to the following values. *When ID0=0, the lower two bits in the address must be set to 11 and be written to RAM. *When ID0=1, the lower two bits in the address must be set to 00 and be written to RAM. 3. Data is written to RAM each four words. If less than four words of data is written to RAM, the last data will not be written to RAM. 4. When the index register and RAM data write (R22h) have been selected, the data is always written first. RAM cannot be written to and read from at the same time. HWM must be set to 0 while RAM is being read. 5. High-speed and normal RAM write operations cannot be executed at the same time. The mode must be switched and the address must then be set. 6. When high-speed RAM write is used with a window address-range specified, dummy write operation may be required to suit the window address range-specification. Refer to the High-Speed RAM Write in the Window Address section. Table 25. Comparison between Normal and High-speed RAM Write Operations Logical operation function Compare operation function Swap function Write mask function Can Can Can Can RAM address set Can be specified by word RAM read Can be read by word RAM write Can be written by word Window address NOTE: 1 word = 2 byte. be be be be Normal RAM Write (HWM=0) used used used used Can be set by word High-speed RAM Write (HWM=1) Cannot be used Cannot be used Can be used Can be used ID0 bit=0: Set the lower two bits to 11 ID0 bit=1: Set the lower two bits to 00 Cannot be used Dummy write operations may have to be inserted according to a window address-range specification Can be set by word 61 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary HIGH-SPEED RAM WRITE IN THE WINDOW ADDRESS When a window address range is specified, GRAM data that is in an optional window area can be updated quickly and continuously by use of dummy write operation. So that the number of RAM access become 4N as shown in the table below. Dummy write operation must be inserted at the first or last of a row of data, depending on the horizontal windowaddress range specification bits (HSA1 to 0, HEA1 to 0). Numbers of dummy write operations of a row must be 4N. Table 26. Number of Dummy Write Operations in High-Speed RAM Write (HSA bits) HSA1 0 0 1 1 HSA0 0 1 0 1 Number of dummy write operations to be inserted at the start of a row 0 1 2 3 Table 27. Table 28. Number of Dummy Write Operations in High-Speed RAM Write (HEA bits) HEA1 0 0 1 1 HEA0 0 1 0 1 Number of dummy write operations to be inserted at the end of a row 3 2 1 0 NOTE: Each row of access must consist of 4 X N operations, including the dummy writes. Horizontal access count = first dummy write count + write data count + last dummy write count = 4 X N 62 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary An example of high-speed RAM write with a window address-range specified is shown below. The window address-range can be accessed consecutively and quickly by inserting two dummy writes at the start of a row and three dummy writes at the end of a row, as determined by using the window address-range specification bits (HSA1 to 0=10, HEA1 to 0=00). Writing in the horizontal direction AM=0, ID0=1 h0000 Window address-range setting HSA=h12, HEA=h30 VSA=h08, VEA=hA0 GRAM address map h0812 Window address range specification (rewritable area) High-speed RAM write mode setting HWM=1 hA030 Address set AD=h0810* hAF83 Window address-range setting HSA=h12, HEA=h30 VSA=h08, VEA=hA0 Dummy RAM write X 2 RAM write X 31 X 153 Dummy RAM write X 3 NOTE: The address set for the high-speed RAM write must be 00 or 11 according to the value of the ID0 bit. Only pre-specified window address-range will be overwritten. Figure 23. Example of High-speed RAM Write with a window address-range specification 63 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary WINDOW ADDRESS FUNCTION When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal address register (start: HSA7-0, end: HEA 7-0) and vertical address register (start: VSA7-0, end: VEA7-0) can be updated consecutively. Data is written to addresses in the direction specified by the AM and ID1-0bit. When image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. The window must be specified to be within the GRAM address area described as following example. Addresses must be set within the window address. [Restriction on window address-range settings] (horizontal direction) 00H ≤ HSA7-0 ≤ HEA7-0 ≤ 83H (vertical direction) 00H ≤ VSA7-0 ≤ VEA7-0 ≤ AFH [Restriction on address settings during the window address] (RAM address) HSA7-0 ≤ AD7-0 ≤ HEA7-0 VSA7-0 ≤ AD15-8 ≤ VEA7-0 Note: In high-speed RAM-write mode, the lower two bits of the address must be set as shown below according to the value of the ID0 bit. ID0=0: The lower two bits of the address must be set to 11. ID0=1: The lower two bits of the address must be set to 00. GRAM address map “0000”H “0083”H “2010”H “2110”H “202F”H “212F”H “5F10”H “5F2F”H “AF00”H Window address-range specification area HSA7-0 = “10”H, HSE7-0 = “2F”H VSA7-0 = “20”H, VEA7-0 = “5F”H “AF83”H I/D = 1 (increment) AM = 0 (horizontal writing) Figure 24. Example of address operation in the window address specification 64 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary GRAPHICS OPERATION FUNCTION The S6D0110 can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. This function supports the following: 1. A write data mask function that selectively rewrites some of the bits in the 16-bit write data. 2. A logical operation write function that writes the data sent from the microcomputer and the original RAM data by a logical operation. 3. A conditional write function that compares the original RAM data or write data and the compare-bit data and writes the data sent from the microcomputer only when the conditions match. Even if the display size is large, the display data in the graphics RAM (GRAM) can be quickly rewritten. The graphics bit operation can be controlled by combining the entry mode register, the bit set value of the RAMwrite-data mask register, and the read/write from the microcomputer. Table 29. Graphics Operation I/D Bit setting AM LG2-0 Write mode 1 0/1 0 000 Horizontal drawing Write mode 2 0/1 1 000 Vertical data replacement, vertical-border drawing Write mode 3 0/1 0 110 111 Write mode 4 0/1 1 110 111 Read/write mode 1 0/1 0 Read/write mode 2 0/1 1 Read/write mode 3 0/1 0 100 101 Read/write mode 4 0/1 1 100 101 Operation mode 001 010 011 001 010 011 Operation and usage data replacement, horizontal-border Conditional horizontal data replacement, horizontalborder drawing Conditional vertical data replacement, vertical-border drawing Horizontal data write with logical operation, horizontalborder drawing Vertical data write with logical operation, verticalborder drawing Conditional horizontal data replacement, horizontalborder drawing Conditional vertical data replacement, vertical-border drawing 65 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Microcomputer 16 +1/-1 Read-data latch +256 Write-data latch 16 Address counter (AC) 16 Logical/Compare operation (LG2- 0): 16 000:replacement,001:OR,010:AND,011:EOR, 100:replacement with matched read, 101:replacement with unmatched read, 110:replacement with matched write, 111:replacement with unmatched write 3 Logical operation bit (LG2=0) 16 Compare bit (CP15-0) 16 Write bit mask 16 16 Graphic RAM (GRAM) Figure 25. Data processing flow of graphic operation 66 Write-mask register (WM15-0) S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary WRITE-DATA MASK FUNCTION The S6D0110 has a bit-wise write-data mask function that controls writing the two-byte data from the microcomputer to the GRAM. Bits that are 0 in the write-data mask register (WM15– 0) cause the corresponding DB bit to be written to the GRAM. Bits that are 1 prevent writing to the corresponding GRAM bit to the GRAM; the data in the GRAM is maintained. This function can be used when only one-pixel data is rewritten or the particular display color is selectively rewritten. DB15 Data from the microcomputer R4 DB0 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 WM15 Write data mask 1 WM0 DB15 GRAM data * B0 1 DB0 * * * * G05 G04 G03 G02 G01 G00 * * * * * Figure 26. Example of write-data mask function operation 67 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary GRAPHICS OPERATION PROCESSING 1. Write mode 1: AM = 0, LG2– 0 = 000 This mode is used when the data is horizontally written at high speed. It can also be used to initialize the graphics RAM (GRAM) or to draw borders. The write-data mask function (WM15–0) is also enabled in these operations. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the GRAM. Operation Examples: 1) I/D = “1”, AM = “0”, LG2-0 = “000” 2) WM15-0 = “07FF’H 3) AC = “0000”H WM15 Write data mask: WM0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 DB15 DB0 Write data (1): 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 Write data (2): 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 “0000”H 1 1 0 0 0 * * * * “0001”H * * * * * * * 1 0 0 1 1 * * Write data (1) * * “0002”H * * * * * * Write data (2) GRAM NOTE: The bits in the GRAM, *’s, are not changed Figure 27. Writing operation of write mode 1 68 * S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary 2. Write mode 2: AM = 1, LG2-0 = 000 This mode is used when the data is vertically written at high speed. It can also be used to initialize the GRAM, develop the font pattern in the vertical direction, or draw borders. The write-data mask function (WM15– 0) is also enabled in these operations. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the upper-right edge (I/D = 1) or upper-left edge (I/D = 0) following the I/D bit after it has reached the lower edge of the GRAM. Operation Examples: 1) I/D = “1”, AM = “1”, LG2-0 = “000” 2) WM15-0 = “07FF’H 3) AC = “0000”H WM15 Write data mask: WM0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 DB15 DB0 Write data (1): 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 Write data (2): 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Write data (3): 0 1 1 1 1 1 0 0 1 1 * * * 0 0 0 1 0 0 * * * * * * 0 0 0 1 “0000”H 1 * * Write data (1) “0100”H 1 1 0 0 0 * * * * * * * * * * * Write data (2) “0200”H 0 1 1 1 1 * * * * * * * * * * * Write data (3) GRAM NOTE: 1. The bits in the GRAM, * ‘s, are not changed. 2. After writing to address “AF00”H, the AC jumps to “0001”H Figure 28. Writing operation of write mode 2 69 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary 3. Write mode 3: AM = 0, LG2-0 = 110/111 This mode is used when the data is horizontally written by comparing the write data and the set value of the compare register (CP15–0). When the result of the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the GRAM. In this operation, the write-data mask function (WM15–0) is also enabled. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the GRAM. Operation Examples: 1) I/D = “1”, AM = “0”, LG2-0 = “110” 2) CP15-0 = “2860”H 3) WM15-0 = “0000”H 4) AC = “0000”H WM15 Write data mask: 0 WM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP15 Compare register: 0 CP0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 Compare operation 0 Conditional replacement DB0 0 0 0 0 (Unmatched) DB15 Write data (2): 0 (Matched) DB15 Write data (1): 0 DB0 1 1 0 0 C 0 0 Compare Conditional operation replacement C R “0000”H 0 0 1 0 1 0 0 0 R 0 0 1 1 1 0 0 * * * * * * * * * * * * * * * * * * * Matched replacement of write data (1) GRAM Figure 29. Writing operation write mode 3 70 1 0 0 0 0 1 1 0 0 0 0 0 * * Replacement “0001”H 0 0 * * * * * * * * * S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary 4. Write mode 4: AM =1, LG2-0 = 110/111 This mode is used when a vertical comparison is performed between the write data and the set value of the compare register (CP15– 0) to write the data. When the result by the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the GRAM. In this operation, the write-data mask function (WM15– 0) are also enabled. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the upper-right edge (I/D = 1) or upper-left edge (I/D = 0) after it has reached the lower edge of the GRAM. Operation Examples: 1) I/D = “1”, AM = “1”, LG2-0 = “111” 2) CP15-0 = “2860”H 3) WM15-0 = “0000”H 4) AC = “0000”H WM15 WM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write data mask: CP15 Compare register: 0 CP0 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 1 1 1 1 DB0 1 0 0 0 0 “0000”H 1 “0100”H * * * * * * * * * * * * * * * * 0 1 1 0 0 1 1 0 C R Compare operation 0 Conditional replacement C R 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 Replacement * * * * * * * * * * * * * * * * “0001”H “0000”H 0 Conditional replacement DB0 (Matched) DB15 Write data (2): 0 (Unmatched) DB15 Write data (1): 0 Compare operation 0 1 1 1 1 1 Write data (1) Write data (2) GRAM “AF00”H NOTE: 1. The bits in the GRAM, * ‘s, are not changed. 2. After writing to address “AF00”H, the AC jumps to “0001”H Figure 30. Writing operation of write mode 4 71 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary 5. Read/Write mode 1: AM = 0, LG2-0 = 001/010/011 This mode is used when the data is horizontally written at high speed by performing a logical operation with the original data. It reads the display data (original data), which has already been written in the GRAM, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the GRAM. This mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: RD* low level) as the write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. However, the bus cycle requires the same time as the read operation. The write-data mask function (WM15–0) is also enabled in these operations. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edges of the GRAM. Operation Examples: 1) I/D = “1”, AM = “0”, LG2-0 = “001”(OR) 2) WM15-0 = “0000 ”H 3) AC = “0000 ”H WM15 Write data mask: 0 WM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB15 0 DB0 Write data (1): 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 Read data (1): 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 Write data (2): 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Read data (2): 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 Logical operation(OR) 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 Logical operation(OR) “0000 ”H 1 1 0 1 “0001 ”H 1 1 0 0 Read data(1) + Write data (1) 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 Read data(2) + Write data (2) GRAM Figure 31. Writing operation of read/write mode 1 72 0 0 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary 6. Read/Write mode 2: AM = 1, LG1-0 = 001/010/011 This mode is used when the data is vertically written at high speed by performing a logical operation with the original data. It reads the display data (original data), which has already been written in the GRAM, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the GRAM. This mode can read the data during the same access-pulse width (68-system: enabled high level, 80-system: RD* low level) as for the write operation since the read operation of the original data does not latch the read data into the microcomputer and temporarily holds it in the read-data latch. However, the bus cycle requires the same time as the read operation. The write-data mask function (WM15–0) is also enabled in these operations. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the upper-right edge (I/D = 1) or upper-left edge (I/D = 0) following the I/D bit after it has reached the lower edge of the GRAM. Operation Examples: 1) I/D = “1”, AM = “1”, LG2-0 = “001”(OR) 2) WM15-0 = “FFE0 ”H 3) AC = “0000”H WM15 Write data mask: 1 WM0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 DB15 0 DB0 Write data (1): 1 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 Read data (1): 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 Write data (2): 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Read data (2): 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 “0000”H Logical operation(OR) 1 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 Logical operation(OR) 1 0 “0001”H “0000”H * * * * * * * * * * * 1 1 1 1 1 Read data (1) + Write data (1) “0100”H * * * * * * * * * * * 0 0 0 0 0 Read data (2) + Write data (2) GRAM “AF00”H NOTE: 1. The bits in the GRAM, * ‘s, are not changed. 2. After writing to address “AF00”H, the AC jumps to “0001”H Figure 32. Writing operation of read/write mode 2 73 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary 7. Read/Write mode 3: AM = 0, LG2-0 = 100/101 This mode is used when the data is horizontally written by comparing the original data and the set value of compare register (CP15– 0). It reads the display data (original data), which has already been written in the GRAM, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the GRAM only when the result of the comparison satisfies the condition. This mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: RD* low level) as write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. However, the bus cycle requires the same time as the read operation. The write-data mask function (WM15–0) is also enabled in these operations. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edges of the GRAM. Operation Examples: 1) I/D = “1”, AM = “0”, LG2-0 = “100” 2) CP15-0 = “2860”H 3) WM15-0 = “0000”H 4) AC = “0000”H WM15 Write data mask: WM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP15 Compare register: 0 0 CP0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 (Matched) DB15 Read data (1): 0 0 Write data (1): 1 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1 0 0 (Unmatched) DB15 0 0 DB0 0 1 1 0 0 1 0 0 DB0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Write data (2): 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 “0000”H 1 1 1 1 0 0 C 0 0 0 Read data (2): 1 0 Compare operation Compare operation R Conditional replacement 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 C R Conditional replacement 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Matched replacement of write data (1) GRAM Figure 33. Writing operation of read/write mode 3 74 0 1 1 0 Replacement “0001”H 0 1 1 0 1 0 0 1 1 1 0 0 0 0 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary 8. Read/Write mode 4: AM =1, LG2-0 = 100/101 This mode is used when the data is vertically written by comparing the original data and the set value of the compare register (CP15–0). It reads the display data (original data), which has already been written in the GRAM, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the GRAM only when the result of the compare operation satisfies the condition. This mode reads the data during the same access-pulse width (68-system: enabled high level, 80-system: RD* low level) as the write operation since reading the original data does not latch the read data into the microcomputer but temporarily holds it in the read-data latch. However, the bus cycle requires the same time as the read operation. The write-data mask function (WM15– 0) is also enabled in these operations. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the upper-right edge (I/D = 1) or upper-left edge (I/D = 0) following the I/D bit after it has reached the lower edge of the GRAM. Operation Examples: 1) I/D = “1”, AM = “1”, LG2-0 = “101” 2) CP15-0 = “2860”H 3) WM15-0 = “0000”H 4) AC = “0000”H WM15 Write data mask: 0 0 WM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP15 Compare register: 0 0 CP0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 (Unmatched) DB15 DB0 Read data (1): 1 0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 Write data (1): 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 (Matched) DB15 Read data (2): Write data (2): 0 0 1 0 1 0 1 1 0 0 0 DB0 0 0 0 1 0 1 1 1 Compare operation 1 0 0 0 0 0 C Compare operation R Conditional replacement 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Replacement C 0 0 0 R 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 Conditional replacement “0000”H “0000”H “0100”H “0001”H 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 Write data (1) Write data (2) GRAM “AF00”H NOTE: 1. The bits in the GRAM, * ‘s, are not changed. 2. After writing to address “AF00”H, the AC jumps to “0001”H Figure 34. Writing operation of read/write mode 4 75 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary GATE DRIVER SCAN MODE SETTING Gate scan mode of S6D0110 is set by SM and GS bit. GS bit determines the scan direction whether the gate driver scans forward or reverse direction. SM bit determines the method of display division (Even/Odd or Upper/Lower division drive). Using this function, various connections between S6D0110 and the liquid crystal panels can be accomplished Figure 35. Scan mode setting SM GS Scan Mode G1 ODD 0 G2 EVEN TFT Panel G1èG2èG3è G4è····èG173è G174èG175èG176 0 G1 G175 G176 G175 G176 G2 S6D0110 G1 ODD 0 G2 EVEN TFT Panel G174èG175èG176 G173è····èG4è G1èG2èG3è 1 G1 G175 G176 G175 G176 G2 S6D0110 G1 G175 TFT Panel G1èG3è G5è····èG173èG175 G2èG4è G6è····èG174èG176 G2 1 0 G176 G1 G175 G176 G2 S6D0110 G1 G175 TFT Panel G176èG174è G172è····èG4èG2 G175èG173è G171è····èG3èG1 G2 1 1 G176 G1 G175 G176 S6D0110 76 G2 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary GAMMA ADJUSTMENT FUNCTION The S6D0110 provides the gamma adjustment function to display 65,536 colors simultaneously. The gamma adjustment executed by the gradient adjustment register and the micro-adjustment register that determines 8 grayscale levels. Furthermore, since the gradient adjustment register and the micro-adjustment register have the positive polarities and negative polarities, adjust them to match LCD panel respectively. Graphics RAM (GRAM) MSB R04 Positive polarity register Negative polarity register PKP02 PKP12 PKP22 PKP32 PKP42 PKP52 PRP02 PRP12 PKP01 PKP11 PKP21 PKP31 PKP41 PKP51 PRP01 PRP11 PKP00 PKP10 PKP20 PKP30 PKP40 PKP50 PRP00 PRP10 PKN02 PKN01 PKN00 PKN12 PKN11 PKN10 PKN22 PKN21 PKN20 PKN32 PKN31 PKN30 PKN42 PKN41 PKN40 PKN52 PKN51 PKN50 PRN02 PRN01 PRN00 PRN12 PRN11 PRN10 LSB R03 R02 R01 R00 G05 G04 G03 G02 G01 G00 V0 5 B04 6 B03 B02 B01 B00 5 V1 8 Grayscale amplifier 64 V63 32-grayscale control <R> 64-grayscale control <G> 32-grayscale control <B> LCD driver LCD driver LCD driver R G B LCD Figure 36. Grayscale control 77 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary STRUCTURE OF GRAYSCALE AMPLIFIER The structure of the grayscale amplifier is shown as below. Determine 8 level (VIN0-VIN7) by the gradient adjuster and the micro adjustment register. Also, Period of each level is split by the internal ladder resistance and generates level between V0 to V63. Gradient adjustment register VDH PRP/N0 3 PRP/N1 3 Oscillation adjustment register Micro adjustment register (6 X 3 bits) PKP/N0 3 PKP/N1 3 PKP/N2 PKP/N3 PKP/N4 PKP/N5 3 3 3 3 VRP/VRN 5 VINP0/VINN0 V0 VINP1/VINN1 V1 V2 8 to 1 selector V3 VINP2/VINN2 V8 8 to 1 selector V9 VINP3/VINN3 V20 8 to 1 selector V21 Ladder resistance VINP4/VINN4 Grayscale amplifier 8 to 1 selector VINP5/VINN5 8 to 1 selector V43 V44 V55 V56 V57 VINP6/VINN6 V62 8 to 1 selector VINP7/VINN7 VGS Figure 37. Structure of grayscale amplifier 78 V63 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary VDH ( ) KVP0 5R 4R RP0 v RP1 RP2 RP3 RP4 RP5 RP6 RP7 VRHP 0 to 28R 1R PKP0[2:0] KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 8 to1 SEL v 5R RP15 1R RP16 RP17 RP18 RP19 RP20 RP21 RP22 v KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 VINP1 PKP1[2:0] PRP0[2:0] RP8 RP9 RP10 RP11 RP12 RP13 RP14 8 to1 SEL VINP2 PKP2[2:0] KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 8 to1 SEL VINP3 PKP3[2:0] 1 6R RP23 1R RP24 RP25 RP26 RP27 RP28 RP29 RP30 v KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVN0 VINP0 8 to1 SEL VINP4 5R 4R RN0 v RN1 RN2 RN3 RN4 RN5 RN6 RN7 VRHN 0 to 28R 1R VINN0 PKN0[2:0] KVN1 KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 8 to1 SEL PKN1[2:0] PRN0[2:0] v RN8 RN9 RN10 RN11 RN12 RN13 RN14 5R RN15 1R RN16 RN17 RN18 RN19 RN20 RN21 RN22 v KVN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16 8 to1 SEL RP31 1R RP32 RP33 RP34 RP35 RP36 RP37 RP38 v VRLP 0 to 28R 4R 5R 8 to1 SEL v RP39 RP40 RP41 RP42 RP43 RP44 RP45 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 VINP5 PKP5[2:0] PRP1[2:0] 8 to1 SEL VINP6 RP46 KVN17 KVN18 KVN19 KVN20 KVN21 KVN22 KVN23 KVN24 8 to1 SEL VRP[2:0] RP47 VINN3 PKN3[2:0] 1 6R RN23 1R RN24 RN25 RN26 RN27 RN28 RN29 RN30 v KVN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32 8 to1 SEL VINN4 PKN4[2:0] 5R RN31 1R RN32 RN33 RN34 RN35 RN36 RN37 RN38 v VRLN 0 to 28R 4R 5R KVP49 VRP 0 to 31R 8R KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 VINN2 PKN2[2:0] PKP4[2:0] 5R VINN1 8 to1 SEL v RN39 RN40 RN41 RN42 RN43 RN44 RN45 RN46 VRN 0 to 31R KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 KVN49 VINN5 PKN5[2:0] PRN1[2:0] VINP7 8R KVN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40 8 to1 SEL VINN6 VINN7 VRN[2:0] RN47 EXVR Figure 38. Structure of Ladder/8 to 1 selector 79 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary GAMMA ADJUSTMENT REGISTER Grayscale Voltage Grayscale Voltage Grayscale Voltage This block is the register to set up the grayscale voltage adjusting to the gamma specification of the LCD panel. This register can independent set up to positive/negative polarities and there are 3 types of register groups to adjust gradient and oscillation on number of the grayscale, characteristics of the grayscale voltage. (but, R.G.B. is commonness.) Following graphics indicates the operation of each adjusting register. Grayscale Number a) Gradient adjustment Grayscale Number b) Oscillation adjustment Grayscale Number c) Micro-adjustment Figure 39. The operation of adjusting register GRADIENT ADJUSTING RESISTOR The gradient adjusting resistor is to adjust around middle gradient, specification of the grayscale number and the grayscale voltage without changing the dynamic range. To accomplish the adjustment, it controls the variable resistor (VRHP (N) / VRL (N)) of the ladder resistor for the grayscale voltage generator. Also, there is an independent resistor on the positive/negative polarities in order for corresponding to asymmetry drive. OSCILLATION ADJUSTING RESISTOR The oscillation-adjusting resistor is to adjust oscillation of the grayscale voltage. To accomplish the adjustment, it controls the variable resistor (VRP (N)) of the ladder resistor for the grayscale voltage generator located at lower side of the ladder resistor. (Adjust upper side by input GVDD level.) Also, there is an independent resistor on the positive/negative polarities as well as the gradient adjusting resistor. MICRO-ADJUSTING RESISTOR The micro-adjusting resistor is to make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it controls the each reference voltage level by the 8 to 1 selector towards the 8-leveled reference voltage generated from the ladder resistor. Also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors. 80 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 30. Gamma adjusting register Register Gradient adjustment Oscillation adjustment Positive polarity PRP0[2:0] PRP1[2:0] VRP[4:0] Negative polarity PRN0[2:0] PRN1[2:0] VRN[4:0] PKP0[2:0] PKN0[2:0] PKP1[2:0] PKN1[2:0] PKP3[2:0] PKN3[2:0] PKP4[2:0] PKN4[2:0] PKP5[2:0] PKN5[2:0] PKP6[2:0] PKN6[2:0] Micro-adjustment Set-up contents Variable resistor VRHP(N) Variable resistor VRLP(N) Variable resistor VRP(N) The voltage of grayscale number 1 is selected by the 8 to 1 selector The voltage of grayscale number 8 is selected by the 8 to 1 selector The voltage of grayscale number 20 is selected by the 8 to 1 selector The voltage of grayscale number 43 is selected by the 8 to 1 selector The voltage of grayscale number 55 is selected by the 8 to 1 selector The voltage of grayscale number 62 is selected by the 8 to 1 selector 81 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary LADDER RESISTOR/8 TO 1 SELECTOR This block outputs the reference voltage of the grayscale voltage. There are two ladder resistors including the variable resistor and the 8 to 1 selector selecting voltage generated by the ladder resistance voltage. The variable and 8 to 1 resistors are controlled by the gamma resistor. Also, there are pins that connect to the external volume resistor. And it allows to compensate the dispersion of length between one panel to another. VARIABLE RESISTOR There are 2 types of the variable resistors that is for the gradient adjustment (VRHP (N) / VRLP (N)) and for the oscillation adjustment (VRP (N)). The resistance value is set by the gradient adjusting resistor and the oscillation adjusting resistor as below. Table 31. Gradient Adjustment Register value PRP(N) [2:0] 000 001 010 011 100 101 110 111 Resistance value PRP(N) 0R 4R 8R 12R 16R 20R 24R 28R Table 32. Oscillation Adjustment Register value VRP(N) [2:0] 00000 00001 00010 . . . 11101 11110 11111 82 Resistance value VRP(N) 0R 1R 2R . . . 29R 30R 31R S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary THE 8 TO 1 SELECTOR In the 8 to 1 selector, the voltage level must be selected given by the ladder resistance and the micro-adjusting register. And output the voltage the six types of the reference voltage, the VIN1- to VIN6. Following figure explains the relationship between the micro-adjusting register and the selecting voltage. Table 33. Relationship between Micro-adjusting Register and Selected Voltage Register value PKP(N) [2:0] 000 001 010 011 100 101 110 111 VINP(N)1 KVP(N)1 KVP(N)2 KVP(N)3 KVP(N)4 KVP(N)5 KVP(N)6 KVP(N)7 KVP(N)8 VINP(N)2 KVP(N)9 KVP(N)10 KVP(N)11 KVP(N)12 KVP(N)13 KVP(N)14 KVP(N)15 KVP(N)16 Selected voltage VINP(N)3 VINP(N)4 KVP(N)17 KVP(N)25 KVP(N)18 KVP(N)26 KVP(N)19 KVP(N)27 KVP(N)20 KVP(N)28 KVP(N)21 KVP(N)29 KVP(N)22 KVP(N)30 KVP(N)23 KVP(N)31 KVP(N)24 KVP(N)32 VINP(N)5 KVP(N)33 KVP(N)34 KVP(N)35 KVP(N)36 KVP(N)37 KVP(N)38 KVP(N)39 KVP(N)40 VINP(N)6 KVP(N)41 KVP(N)42 KVP(N)43 KVP(N)44 KVP(N)45 KVP(N)46 KVP(N)47 KVP(N)48 83 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Table 34. Gamma Adjusting Voltage Formula (Positive polarity) Pins KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49 Formula GVDD GVDD- ∆ V*5R/SUMRP GVDD- ∆ V*9R/SUMRP GVDD- ∆ V*13R/SUMRP GVDD- ∆ V*17R/SUMRP GVDD- ∆ V*21R/SUMRP GVDD- ∆ V*25R/SUMRP GVDD- ∆ V*29R/SUMRP GVDD- ∆ V*33R/SUMRP GVDD- ∆ V*(33R+VRHP) /SUMRP GVDD- ∆ V*(34R+VRHP) /SUMRP GVDD- ∆ V*(35R+VRHP) /SUMRP GVDD- ∆ V*(36R+VRHP) /SUMRP GVDD- ∆ V*(37R+VRHP) /SUMRP GVDD- ∆ V*(38R+VRHP) /SUMRP GVDD- ∆ V*(39R+VRHP) /SUMRP GVDD- ∆ V*(40R+VRHP) /SUMRP GVDD- ∆ V*(45R+VRHP) /SUMRP GVDD- ∆ V*(46R+VRHP) /SUMRP GVDD- ∆ V*(47R+VRHP) /SUMRP GVDD- ∆ V*(48R+VRHP) /SUMRP GVDD- ∆ V*(49R+VRHP) /SUMRP GVDD- ∆ V*(50R+VRHP) /SUMRP GVDD- ∆ V*(51R+VRHP) /SUMRP GVDD- ∆ V*(52R+VRHP) /SUMRP GVDD- ∆ V*(68R+VRHP) /SUMRP GVDD- ∆ V*(69R+VRHP) /SUMRP GVDD- ∆ V*(70R+VRHP) /SUMRP GVDD- ∆ V*(71R+VRHP) /SUMRP GVDD- ∆ V*(72R+VRHP) /SUMRP GVDD- ∆ V*(73R+VRHP) /SUMRP GVDD- ∆ V*(74R+VRHP) /SUMRP GVDD- ∆ V*(75R+VRHP) /SUMRP GVDD- ∆ V*(80R+VRHP) /SUMRP GVDD- ∆ V*(81R+VRHP) /SUMRP GVDD- ∆ V*(82R+VRHP) /SUMRP GVDD- ∆ V*(83R+VRHP) /SUMRP GVDD- ∆ V*(84R+VRHP) /SUMRP GVDD- ∆ V*(85R+VRHP) /SUMRP GVDD- ∆ V*(86R+VRHP) /SUMRP GVDD- ∆ V*(87R+VRHP) /SUMRP GVDD- ∆ V*(87R+VRHP+VRLP) /SUMRP GVDD- ∆ V*(91R+VRHP+VRLP) /SUMRP GVDD- ∆ V*(95R+VRHP+VRLP) /SUMRP GVDD- ∆ V*(99R+VRHP+VRLP) /SUMRP GVDD- ∆ V*(103R+VRHP+VRLP) /SUMRP GVDD- ∆ V*(107R+VRHP+VRLP) /SUMRP GVDD- ∆ V*(111R+VRHP+VRLP) /SUMRP GVDD- ∆ V*(115R+VRHP+VRLP) /SUMRP GVDD- ∆ V*(120R+VRHP+VRLP) /SUMRP Micro-adjusting register value Reference voltage PKP02-00 = “000” PKP02-00 = “001” PKP02-00 = “010” PKP02-00 = “011” PKP02-00 = “100” PKP02-00 = “101” PKP02-00 = “110” PKP02-00 = “111” PKP12-10 = “000” PKP12-10 = “001” PKP12-10 = “010” PKP12-10 = “011” PKP12-10 = “100” PKP12-10 = “101” PKP12-10 = “110” PKP12-10 = “111” PKP22-20 = “000” PKP22-20 = “001” PKP22-20 = “010” PKP22-20 = “011” PKP22-20 = “100” PKP22-20 = “101” PKP22-20 = “110” PKP22-20 = “111” PKP32-30 = “000” PKP32-30 = “001” PKP32-30 = “010” PKP32-30 = “011” PKP32-30 = “100” PKP32-30 = “101” PKP32-30 = “110” PKP32-30 = “111” PKP42-40 = “000” PKP42-40 = “001” PKP42-40 = “010” PKP42-40 = “011” PKP42-40 = “100” PKP42-40 = “101” PKP42-40 = “110” PKP42-40 = “111” PKP52-50 = “000” PKP52-50 = “001” PKP52-50 = “010” PKP52-50 = “011” PKP52-50 = “100” PKP52-50 = “101” PKP52-50 = “110” PKP52-50 = “111” - VINP0 VINP1 VINP2 VINP3 VINP4 VINP5 VINP6 VINP7 SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP SUMRP: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN ∆ V: Potential difference between KV0 and KV49 = GVDD*SUMRP*SUMRN / [SUMRP*SUMRN+EXVR*(SUMRP+SUMRN)] 84 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 35. Gamma Voltage Formula (Positive Polarity) Grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Formula VINP0 VINP1 V3+(V1-V3)*(8/24) V8+(V1-V8)*(450/800) V8+(V3-V8)*(16/24) V8+(V3-V8)*(12/24) V8+(V3-V8)*(8/24) V8+(V3-V8)*(4/24) VINP2 V20+(V8-V20)*(22/24) V20+(V8-V20)*(20/24) V20+(V8-V20)*(18/24) V20+(V8-V20)*(16/24) V20+(V8-V20)*(14/24) V20+(V8-V20)*(12/24) V20+(V8-V20)*(10/24) V20+(V8-V20)*(8/24) V20+(V8-V20)*(6/24) V20+(V8-V20)*(4/24) V20+(V8-V20)*(2/24) VINP3 V43+(V20-V43)*(22/23) V43+(V20-V43)*(21/23) V43+(V20-V43)*(20/23) V43+(V20-V43)*(19/23) V43+(V20-V43)*(18/23) V43+(V20-V43)*(17/23) V43+(V20-V43)*(16/23) V43+(V20-V43)*(15/23) V43+(V20-V43)*(14/23) V43+(V20-V43)*(13/23) V43+(V20-V43)*(12/23) Grayscale voltage V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula V43+(V20-V43)*(11/23) V43+(V20-V43)*(10/23) V43+(V20-V43)*(9/23) V43+(V20-V43)*(8/23) V43+(V20-V43)*(7/23) V43+(V20-V43)*(6/23) V43+(V20-V43)*(5/23) V43+(V20-V43)*(4/23) V43+(V20-V43)*(3/23) V43+(V20-V43)*(2/23) V43+(V20-V43)*(1/23) VINP4 V55+(V43-V55)*(22/24) V55+(V43-V55)*(20/24) V55+(V43-V55)*(18/24) V55+(V43-V55)*(16/24) V55+(V43-V55)*(14/24) V55+(V43-V55)*(12/24) V55+(V43-V55)*(10/24) V55+(V43-V55)*(8/24) V55+(V43-V55)*(6/24) V55+(V43-V55)*(4/24) V55+(V43-V55)*(2/24) VINP5 V60+(V55-V60)*(20/24) V60+(V55-V60)*(16/24) V60+(V55-V60)*(12/24) V60+(V55-V60)*(8/24) V62+(V55-V62)*(350/800) V62+(V60-V62)*(16/24) VINP6 VINP7 85 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Table 36. Gamma Adjusting Voltage Formula (Negative polarity) Pins KVN0 KVN1 KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 KVN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16 KVN17 KVN18 KVN19 KVN20 KVN21 KVN22 KVN23 KVN24 KVN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32 KVN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40 KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 KVN49 Formula GVDD GVDD- ∆ V*5R/SUMRN GVDD- ∆ V*9R/SUMRN GVDD- ∆ V*13R/SUMRN GVDD- ∆ V*17R/SUMRN GVDD- ∆ V*21R/SUMRN GVDD- ∆ V*25R/SUMRN GVDD- ∆ V*29R/SUMRN GVDD- ∆ V*33R/SUMRN GVDD- ∆ V*(33R+VRHN)/SUMRN GVDD- ∆ V*(34R+VRHN)/SUMRN GVDD- ∆ V*(35R+VRHN)/SUMRN GVDD- ∆ V*(36R+VRHN)/SUMRN GVDD- ∆ V*(37R+VRHN)/SUMRN GVDD- ∆ V*(38R+VRHN)/SUMRN GVDD- ∆ V*(39R+VRHN)/SUMRN GVDD- ∆ V*(40R+VRHN)/SUMRN GVDD- ∆ V*(45R+VRHN)/SUMRN GVDD- ∆ V*(46R+VRHN)/SUMRN GVDD- ∆ V*(47R+VRHN)/SUMRN GVDD- ∆ V*(48R+VRHN)/SUMRN GVDD- ∆ V*(49R+VRHN)/SUMRN GVDD- ∆ V*(50R+VRHN)/SUMRN GVDD- ∆ V*(51R+VRHN)/SUMRN GVDD- ∆ V*(52R+VRHN)/SUMRN GVDD- ∆ V*(68R+VRHN)/SUMRN GVDD- ∆ V*(69R+VRHN)/SUMRN GVDD- ∆ V*(70R+VRHN)/SUMRN GVDD- ∆ V*(71R+VRHN)/SUMRN GVDD- ∆ V*(72R+VRHN)/SUMRN GVDD- ∆ V*(73R+VRHN)/SUMRN GVDD- ∆ V*(74R+VRHN)/SUMRN GVDD- ∆ V*(75R+VRHN)/SUMRN GVDD- ∆ V*(80R+VRHN)/SUMRN GVDD- ∆ V*(81R+VRHN)/SUMRN GVDD- ∆ V*(82R+VRHN)/SUMRN GVDD- ∆ V*(83R+VRHN)/SUMRN GVDD- ∆ V*(84R+VRHN)/SUMRN GVDD- ∆ V*(85R+VRHN)/SUMRN GVDD- ∆ V*(86R+VRHN)/SUMRN GVDD- ∆ V*(87R+VRHN)/SUMRN GVDD- ∆ V*(87R+VRHN+VRLN)/SUMRN GVDD- ∆ V*(91R+VRHN+VRLN)/SUMRN GVDD- ∆ V*(95R+VRHN+VRLN)/SUMRN GVDD- ∆ V*(99R+VRHN+VRLN)/SUMRN GVDD- ∆ V*(103R+VRHN+VRLN)/SUMRN GVDD- ∆ V*(107R+VRHN+VRLN)/SUMRN GVDD- ∆ V*(111R+VRHN+VRLN)/SUMRN GVDD- ∆ V*(115R+VRHN+VRLN)/SUMRN GVDD- ∆ V*(120R+VRHN+VRLN)/SUMRN SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN ∆ V: Potential difference between KV0 and KV49 = GVDD*SUMRP*SUMRN / [SUMRP*SUMRN+EXVR*(SUMRP+SUMRN)] 86 Micro-adjusting register value PKN02-00 = “000” PKN02-00 = “001” PKN02-00 = “010” PKN02-00 = “011” PKN02-00 = “100” PKN02-00 = “101” PKN02-00 = “110” PKN02-00 = “111” PKN12-10 = “000” PKN12-10 = “001” PKN12-10 = “010” PKN12-10 = “011” PKN12-10 = “100” PKN12-10 = “101” PKN12-10 = “110” PKN12-10 = “111” PKN22-20 = “000” PKN22-20 = “001” PKN22-20 = “010” PKN22-20 = “011” PKN22-20 = “100” PKN22-20 = “101” PKN22-20 = “110” PKN22-20 = “111” PKN32-30 = “000” PKN32-30 = “001” PKN32-30 = “010” PKN32-30 = “011” PKN32-30 = “100” PKN32-30 = “101” PKN32-30 = “110” PKN32-30 = “111” PKN42-40 = “000” PKN42-40 = “001” PKN42-40 = “010” PKN42-40 = “011” PKN42-40 = “100” PKN42-40 = “101” PKN42-40 = “110” PKN42-40 = “111” PKN52-50 = “000” PKN52-50 = “001” PKN52-50 = “010” PKN52-50 = “011” PKN52-50 = “100” PKN52-50 = “101” PKN52-50 = “110” PKN52-50 = “111” - Reference voltage VINN0 VINN1 VINN2 VINN3 VINN4 VINN5 VINN6 VINN7 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 37. Gamma Voltage Formula (Negative Polarity) Grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Formula VINN0 VINN1 V3+(V1-V3)*(8/24) V8+(V1-V8)*(450/800) V8+(V3-V8)*(16/24) V8+(V3-V8)*(12/24) V8+(V3-V8)*(8/24) V8+(V3-V8)*(4/24) VINN2 V20+(V8-V20)*(22/24) V20+(V8-V20)*(20/24) V20+(V8-V20)*(18/24) V20+(V8-V20)*(16/24) V20+(V8-V20)*(14/24) V20+(V8-V20)*(12/24) V20+(V8-V20)*(10/24) V20+(V8-V20)*(8/24) V20+(V8-V20)*(6/24) V20+(V8-V20)*(4/24) V20+(V8-V20)*(2/24) VINN3 V43+(V20-V43)*(22/23) V43+(V20-V43)*(21/23) V43+(V20-V43)*(20/23) V43+(V20-V43)*(19/23) V43+(V20-V43)*(18/23) V43+(V20-V43)*(17/23) V43+(V20-V43)*(16/23) V43+(V20-V43)*(15/23) V43+(V20-V43)*(14/23) V43+(V20-V43)*(13/23) V43+(V20-V43)*(12/23) Grayscale voltage V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula V43+(V20-V43)*(11/23) V43+(V20-V43)*(10/23) V43+(V20-V43)*(9/23) V43+(V20-V43)*(8/23) V43+(V20-V43)*(7/23) V43+(V20-V43)*(6/23) V43+(V20-V43)*(5/23) V43+(V20-V43)*(4/23) V43+(V20-V43)*(3/23) V43+(V20-V43)*(2/23) V43+(V20-V43)*(1/23) VINN4 V55+(V43-V55)*(22/24) V55+(V43-V55)*(20/24) V55+(V43-V55)*(18/24) V55+(V43-V55)*(16/24) V55+(V43-V55)*(14/24) V55+(V43-V55)*(12/24) V55+(V43-V55)*(10/24) V55+(V43-V55)*(8/24) V55+(V43-V55)*(6/24) V55+(V43-V55)*(4/24) V55+(V43-V55)*(2/24) VINN5 V60+(V55-V60)*(20/24) V60+(V55-V60)*(16/24) V60+(V55-V60)*(12/24) V60+(V55-V60)*(8/24) V62+(V55-V62)*(350/800) V62+(V60-V62)*(16/24) VINN6 VINN7 87 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary V0 Output Level Negative Polarity Positive Polarity DB15-11, 4-0: 11111 DB10-5: 111111 DB15-11, 4-0: 00000 DB10-5: 000000 V63 RAM data Figure 40. Relationship between RAM data and output voltage Sn Negative polarity Vcom Positive polarity Figure 41. Relationship between source output and Vcom 88 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary THE 8-COLOR DISPLAY MODE The S6D0110 carries 8-color display mode. Using grayscale levels are V0 and V63 and all other level power supplies are halt. So that it attempts to lower power consumption. Also, during the 8-color mode, the Gamma micro adjustment register, PKP00-PKP52 and PKN00-PKN52 are invalid. Rewrite the data of GRAM R/B to 00000 or 11111, G to 000000 or 111111 before set the mode. The level power supply (V1-V62) is in OFF condition during the 8-color mode in order to select V0/V63. Graphics RAM (GRAM) MSB R04 Positive polarity register Negative polarity register PKP02 PKP01 PKP00 PKP12 PKP11 PKP10 PKP22 PKP21 PKP20 PKP32 PKP31 PKP30 PKP42 PKP41 PKP40 PKP52 PKP51 PKP50 PRP02 PRP01 PRP00 PRP12 PRP11 PRP10 PKN02 PKN01 PKN00 PKN12 PKN11 PKN10 PKN22 PKN21 PKN20 PKN32 PKN31 PKN30 PKN42 PKN41 PKN40 PKN52 PKN51 PKN50 PRN02 PRN01 PRN00 PRN12 PRN11 PRN10 LSB R03 R02 R01 R00 V0 8 Grayscale amplifier 2 G05 G04 G03 G02 5 G01 G00 B04 6 B03 B02 B01 B00 5 ON/OFF control <R> ON/OFF control <G> ON/OFF control <B> LCD driver LCD driver LCD driver R G B V63 LCD Figure 42. 8-color display control 89 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary < 6 5 , 5 3 6 -c o l o r = > 8 - c o l o r > OFF G O N =“1 ” D T E = “1 ” D 1 - 0 =“1 0” Wait (2 frame or higher) ON G O N =“1 ” D T E = “0 ” D 1 - 0 =“1 0” Wait (2 frame or higher) OFF <8-color => 65,536 -color> OFF G O N = “1 ” D T E = “1 ” D 1 - 0 =“1 0” Wait (2 frame or higher) ON G O N = “1 ” D T E = “0 ” D 1 - 0 =“1 0” Wait (2 frame or higher) OFF G O N =“0 ” D T E = “0 ” D 1 - 0 =“0 0” G O N = “0 ” D T E = “0 ” D 1 - 0 =“0 0” RAM setup RAM setup C L = “1 ” C L = “0 ” Wait (40ms or higher) ON Wait (40ms or higher) ON G O N =“0 ” D T E = “0 ” D 1 - 0 =“0 1” Wait (2 frame or higher) ON G O N = “0 ” D T E = “0 ” D 1 - 0 =“0 1” Wait (2 frame or higher) ON G O N =“1 ” D T E = “0 ” D 1 - 0 =“0 1” ON G O N =“1 ” D T E = “0 ” D 1 - 0 =“1 1” Wait (2 frame or higher) ON G O N = “1 ” D T E = “0 ” D 1 - 0 =“0 1” ON G O N = “1 ” D T E = “0 ” D 1 - 0 =“1 1” Wait (2 frame or higher) ON G O N =“1 ” D T E = “1 ” D 1 - 0 =“1 1” Display by 8-color mode G O N = “1 ” D T E = “1 ” D 1 - 0 =“1 1” Display by 65,536-color mode Figure 43. Set up procedure for the 8-color mode 90 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary SYSTEM STRUCTURE EXAMPLE G174 G176 G173 G175 Following diagram indicates the system structure, which composes the 132 (width) x 176 (length) dots TFT-LCD panel. G2 G4 CSB RS E R/W DB[15:0] IM[2:0] RESETB S6D0110 CSB RS E R/W DB[15:0] IM[2:0] RESETB S1 S2 S3 S394 S395 S396 G1 G3 132RGB x 176 dot TFT LCD Panel Figure 44. System structure 91 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Instruction set up flow < Display on> <Display off> EQ=0 Power setting Display off GON= 1 DTE= 1 Display on D1-0= 10 GON= 0 DTE= 0 D1-0= 01 Wait (more than 2 frames) Wait (more than 2 frames) Display off GON= 1 DTE= 0 Display on D1-0= 10 GON= 1 DTE= 0 D1-0= 01 Wait (more than 2 frames) Display on Display off GON= GON= 0 1 DTE= 0 DTE= 0 D1-0= 11 D1-0= 00 Wait (more than 2 frames) Power off SAP2-0= 000 AP2-0= 000 Display on GON= 1 DTE= 1 D1-0= 11 Display OFF Display ON Continue to the display on flow Continue to the display on flow Figure 45. Instruction set up flow 92 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary < Standby> < Sleep> Display off flow Display off flow Standby Sleep set Standby set (STB= 1 ) set Sleep set (SLP= 1 ) Sleep Oscillation start Sleep cancel (SLP= 0 ) Cancel Standby Wait 10ms cancel Power setting Standby cancel (STB= 0 ) Display on flow Power setting Display on flow Figure 46. Instruction setup flow (continued) 93 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary OSCILLATION CIRCUIT The S6D0110 can oscillate between the OSC1 and OSC2 pins using an internal R-C oscillator with an external oscillation resistor. Note that in R-C oscillation, the oscillation frequency is changed according to the external resistance value, wiring length, or operating power-supply voltage. If Rf is increased or power supply voltage is decrease, the oscillation frequency decreases. For the relationship between Rf resistor value and oscillation frequency, see the Electric Characteristics Notes section. 1) External Clock Mode Clock OSC1 (200kHz) Damping resistance (2 k Ω ) OSC2 S6D0110 2) External Resistance Oscillation Mode OSC1 Rf OSC2 S6D0110 N O T E : T h e Rf resistance must be located near the OSC1/OSC2 pin on the chip Figure 47. Oscillation Circuit 94 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary N-RASTER-ROW REVERSED AC DRIVE The S6D0110 supports not only the LCD reversed AC drive in a one-frame unit but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 64 raster-rows. When a problem affecting display quality occurs, the n-raster-row reversed AC drive can improve the quality. Determine the number of the raster-rows n (NW bit set value +1) for alternating after confirmation of the display quality with the actual LCD panel. However, if the number of AC raster-row is reduced, the LCD alternating frequency becomes high. Because of this, the charge or discharge current is increased in the LCD cells. 1 frame 1 frame Blank period 1 2 3 4 175 176 184 Blank period 1 2 3 4 175 176 184 1 2 Frame A/C waveform drive 176 raster-row N-raster-row A/C waveform drive 176 raster-row reverse 3 raster-row E O R =“1 ” Figure 48. Example of an AC signal under n-raster-row reversed AC drive 95 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary INTERLACE DRIVE S6D0110 supports the interlace drive to protect from the flicker. It splits one frame into n fields and drives. Determine the n fields (FLD bit stetting value) after confirming on the actual LCD display. Following table indicates n fields: the gate selecting position when it is 1 or 3. and the diagram below indicates the output waveform when the field interlace drive is active. G S = ”0 ” FLD1-0 setting value Field 01 11 - (1) G1 Ο Ο G2 Ο G3 Ο G4 Ο G5 Ο G6 Ο G7 Ο G8 Ο G9 Ο Gate (2) (3) Ο Ο Ο Ο Ο Ο Ο Ο ⇓ ⇓ G173 Ο G174 Ο G175 Ο G176 Ο G S = ”1 ” FLD1-0 setting value Field 01 11 - (1) G176 Ο Ο G175 Ο G174 Ο G173 Ο G172 Ο G171 Ο G170 Ο G169 Ο G168 Ο Gate (2) Ο Ο Ο Ο Ο Ο Ο Ο ⇓ Ο Ο Ο Ο ⇓ G4 Ο G3 Ο G2 Ο G1 Ο Ο Ο Ο Ο 1 frame Blank period Field Field Field Field (1) (2) (3) (1) AC polarity G1 G2 G3 G4 G5 G6 G3n+1 G3n+2 G3n+3 Figure 49. Interlace drive and output waveform 96 (3) S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary A/C TIMING Following diagram indicates the A/C timing on the each A/C drive method. After every 1 drawing, the A/C timing is occurred on the reversed frame AC drive. After the A/C timing, the blank (all gate output: Vgoff level) period described below is inserted. When it is on the interlace drive, blank period is inserted every A/C timing. When the reversed n-raster-row is driving, a blank period is inserted after all screens are drawn. Front and Back porch can be adjusted using FP3-0 and BP3-0 bits (R08h). In interlace drive mode, Blank period can be adjusted using BLP130 and BLP23-0 bit (R09h). Frame reverse AC drive n-raster-row reversed AC drive 3 field interlace drive Back porch Back porch Back porch A/C n-raster-row A/C Field 1 n-raster-row A/C n-raster-row A/C A/C Blank period 1 (BLP1) A/C Blank period 2 (BLP2) n-raster-row A/C n-raster-row A/C n-raster-row 1 frame period Field 2 1 frame period 1 frame period Frame 1 n-raster-row A/C A/C n-raster-row A/C n-raster-row Field 3 n-raster-row A/C timing A/C A/C Front porch Blank period = Back porch + Front Porch A/C Front porch Blank period = Back porch + Blank period 1 + Blank period 2 + Front porch Front porch Blank period = Back porch + Front Porch Figure 50. A/C timing 97 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary FRAME FREQUENCY ADJUSTING FUNCTION The S6D0110 has an on-chip frame-frequency adjustment function. The frame frequency can be adjusted by the instruction setting (DIV, RTN) during the LCD driver as the oscillation frequency is always same. If the oscillation frequency is set to high, animation or a static image can be displayed in suitable ways by changing the frame frequency. When a static image is displayed, the frame frequency can be set low and the low-power consumption mode can be entered. When high-speed screen switching for an animated display, etc. is required, the frame frequency can be set high. RELATIONSHIP BETWEEN LCD DRIVE DUTY AND FRAME FREQUENCY The relationships between the LCD drive duty and the frame frequency is calculated by the following expression. The frame frequency can be adjusted in the 1H period adjusting bit (RTN) and in the operation clock division bit (DIV) by the instruction. fOSC Frame Frequency = Clock cycles per raster-row x division ratio x (Line+B) [Hz] f OSC: R-C oscillation frequency Line: Number of raster-rows (NL bit) Clock cycles per raster-row: RTN bit Division ratio: DIV bit B: Blank period(Back porch + Front Porch) Figure 51. Formula for the frame frequency Example calculation Driver raster-row: 176 1H period: 16 clock (RTN3 to 0 = 0000) Operation clock division ratio: 1division B: Blank period (BP + FP): 8 fosc = 60Hz x (0+16) clock x 1 division x (176+B ) lines = 177 [kHz] In this case, the RC oscillation frequency becomes 177 kHz. The external resistance value of the RC oscillator must be adjusted to be 177 kHz. Note: When FLD1-0=”11”(interlace drive), B = BP + FP + BLP1 + BLP2 98 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary SCREEN-DIVISION DRIVING FUNCTION The S6D0110 can select and drive two screens at any position with the screen-driving position registers (R14 and R15). Any two screens required for display are selectively driven and reducing LCD-driving voltage and power consumption. For the 1s t division screen, start line (SS17 to 10) and end line (SE17 to 10) are specified by the 1st screen-driving position register (R14). For the 2nd division screen, start line (SS27 to 20) and end line (SE27 to 20) are specified by the 2nd screen-driving position register (R15). The 2nd screen control is effective when the SPT bit is 1. The total count of selection-driving lines for the 1s t and 2nd screens must correspond to the LCD-driving duty set value. G1 G7 Rm * 1st screen: 7-raster-row driving Non-display area G26 G42 OCT 14th 10:18am 2nd screen: 17 raster-row driving Non-display area • Driving raster-row: NL4-0 = 10101 (176 lines) • 1st screen setting: SS17-10 = 00H, SE17-10 = 06H • 2nd screen setting: SS27-20 = 19H, SE27-20 = 29H, SPT = 1 Figure 52. Driving on 2 screen 99 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary ST RESTRICTION ON THE 1 /2 ND SCREEN DRIVING POSITION REGISTER SETTINGS The following restrictions must be satisfied when setting the start line (SS17 to 10) and end line (SE17 to 10) of the 1st screen driving position register (R14) and the start line (SS27 to 20) and end line (SE27 to 20) of the 2nd screen driving position register (R15) for the S6D0110. Note that incorrect display may occur if the restrictions are not satisfied. Table 38. Restrictions on the 1st /2nd Screen Driving Position Register Setting 1st Screen Driving (SPT=0) Register setting Display operation Full screen display (SE17 to 10) – (SS17 to 10) = NL Normally displays (SE17 to 10) to (SS17 to 10) Partial display Normally displays (SE17 to 10) to (SS17 to 10) (SE17 to 10) – (SS17 to 10) < NL White display for all other times (RAM data is not related at all) (SE17 to 10) – (SS17 to 10) > NL Setting disabled NOTE 1: SS17 to 10 ≤ SE17 to 10 ≤ AFh NOTE 2: Setting SE27 to 20 and SS27 to 20 are invalid 2nd Screen Driving (SPT=1) Register setting ((SE17 to 10) – (SS17 to 10)) + ((SE27 to 20) – (SS27-20)) = NL ((SE17 to 10) – (SS17 to 10)) + ((SE27 to 20) – (SS27-20)) < NL Display operation Full screen display Normally displays (SE27 to 10) to (SS17 to 10) Partial display Normally displays (SE27 to 10) to (SS17 to 10) White display for all other times (RAM data is not related at all) ((SE17 to 10) – (SS17 to 10)) Setting disabled + ((SE27 to 20) – (SS27-20)) > NL NOTE 1: SS17 to 10 ≤ SE17 to 10 < SS27 to 20 ≤ SE27 to 20 ≤ AFh NOTE 2: (SE27 to 20) – (SS17 to 10) ≤ NL The driver output can’t be set for non-display area during the partial display. Determine based on specification of the panels. 100 PT1 PT0 0 0 1 1 0 1 0 1 Source output in non-display area Positive polarity Negative polarity V63 V0 V63 V0 VSS VSS Hi-Z Hi-Z Gate output in Non-display area Normal drive Vgoff Vgoff Vgoff S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Refer to the following flow to set up the partial display. Full screen display PT1-0 = 00 Set SS/SE bits Wait (more than 2 frames) Split screen drive set up flow PT1-0 = 01 or Set as need PT1-0 = 10 or PT1-0 = 11 Partial display on Setting flow for full screen driver Set SS/SE bits Full screen display Figure 53. Partial display set up flow 101 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary APPLICATION CIRCUIT The following figure indicates a schematic diagram of application circuit for S6D0110. C11C11+ C12C12+ C21+ C21C22+ C22C23+ C23C31+ C31C41+ C41- Notes) 1) All capacitor value : 1uF 2) Every pins descripted in this diagram have to be wired out externally. 3) "Space only" means only space that can arrange curcuit component on it must be ensured. (Only "space" is needed to arrange the described circuit component on it.) 4) VSSO & VSS pin have to be connected externally ( Refer to the following figure ) 5) VDD3O & VDD3 pin have to be connected externally ( Refer to the following figure ) VGH VCI3 VGL CGND AVSS Connect Externally VSSO VSS VSS VSS VSS VSS No.91 Internally connected No.96 VBS Connect VCI Space External Power VCI4 Only Externally VDD3O VDD3 VDD3 VDD3 No.97 Internally connected *Note 3) VDD3 RDVDD External Power VDD3 No.100 VDD VSS VGS VCOML VCOMR VREG1OUT VREG1 VREG2OUT VREG2 GVDD VCOMOUT Space Only * Note 3) Space Only VCOMH VCL VCI1 REGP REGN AVDD Space Only * Note 3) VCI2 VGOFFOUT VGOFF VGOFFH VGOFFL R = 2k Signal In OSC1 Rf = 100k OSC2 VSSO PREGB VDD3O G0 G1 G3 G5 CONTACT1 CONTACT2 RESETB1 VDD3O IM0/ID VSSO IM1 VDD3O IM2 VDD3O RESETB2 VSSO DB15~8 VSSO DB7~2 DB1/SDO DB0/SDI VSSO RD WR/SCL RS CS VSSO CL1 M FLM EQ DISPTMG TEST RESETB3 G173 G175 S1 S2 S3 S4 S389 S390 S391 S392 S393 S394 S395 S396 G177 G176 G174 G4 G2 S6D0110 Figure 54. Application Circuit 102 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table 39. Absolute Maximum Rating (VSS = 0V) Item Symbol Rating Unit Supply voltage VDD - 0.3 ~ + 5.0 V Supply voltage for step-up circuit Vci - 0.3 ~ + 5.0 V LCD Supply Voltage range |VGH – VGL| 30 V Input Voltage range Vin - 0.3 to VDD +0.5 V Operating temperature Topr -40 ~ +85 °C Storage temperature Tstg -55 ~ +110 °C Notes: 1. Absolute maximum rating is the limit value beyond which the IC may be broken. They do not assure operations. 2. Operating temperature is the range of device-operating temperature. They do not guarantee chip performance. 3. Absolute maximum rating is guaranteed when our company’s package used. 103 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary DC CHARACTERISTICS Table 40. DC Characteristics Characteristic MIN TYP MAX VDD 1.8 - 2.5 V *1 VDD3 2.3 - 3.3 V *1 VGH +7 - 20.0 V VGL -7 - -15.0 V VGOFF -5 - -15 V AVDD 3.5 5.5 V GVDD 3.0 5.0 V Input high voltage VIH 0.7VDD3 - VDD3 V *2 Input low voltage VIL 0 - 0.3VDD3 V *2 Output high voltage VOH IOH = -2.0mA VDD3-0.5 VDD3 V *3 Output low voltage VOL IOL = 2.0mA 0.0 - 0.5 V *3 Operating voltage LCD driving voltage Symbol CONDITION (VSS = 0V) Unit Note Input leakage current IIL VIN = VSS or VDD3 -1.0 - 1.0 µA *2 Output leakage current IOL VIN = VSS or VDD3 -3.0 - 3.0 µA *3 159 177 194 KHz *4 Frame freq. = 60 Hz Operating frequency fosc Internal reference power supply voltage VCI 2.5 - 3.3 V 1st step-up input voltage VCI1 1.7 - 2.75 V 95 99 - % 5.5 V - % 15 V - % 3.3 V - % Display line = 176 st 1 step-up output efficiency 2nd step-up input voltage AVDD ILOAD = TBD mA 3.4 VCI2 nd 2 step-up output efficiency VGH 3rd step-up input voltage VCI3 3rd step-up output efficiency VGL 4th step-up input voltage VCI4 ILOAD = TBD mA 95 99 6.8 ILOAD = TBD mA 95 99 2.5 th 4 step-up output 95 99 VCL ILOAD = TBD mA efficiency Notes : 1. VSS = 0V. 2. Applied pins; IM2-1, CSB, E, R/W, RS, DB0 to DB15, PREGB, RESETB1,2,3. 3. Applied pins; DB0 to DB15, CL1, M, FLM, EQ, DISPTMG. 4. Target frame frequency = 60 Hz, Display line = 176, Back porch = 3, Front port = 5 Internal RTN[3:0] register = “0000”, Internal DIV[1:0] register = “00” 104 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 41. DC Characteristics for LCD driver outputs Characteristic LCD gate driver output On resistance Symbol Ron CONDITION VGH –VGOFF=30.0V, VGH=18V, VGOFF=-12V, MIN (VDD = 1.8V, VDD3 = 3.0V, VSS = 0V) TYP MAX Unit Note - - 2 K *5 Vgo = VGH – 0.5V LCD source driver high-level output current (Gradation output) LCD source driver lowlevel output current (Gradation output) Output voltage deviation (Mean value) LCD source driver output voltage range LCD source driver highlevel output current (Binary output) LCD source driver lowlevel output current (Binary output) LCD source driver delay Current consumption during standby mode Current consumption during normal operation IHOG Vso = 4.5V, Vsx = 3.5V - - -50 A *6 ILOG Vso = 0.5V, Vsx = 1.5V 50 - - A *6 4.2V ≤ Vso - ±20 ±30 MV *6 0.8V < Vso < 4.2V - ±10 ±20 *6 ±20 ±30 MV MV GVDD+0.1 - GVDD-0.1 V ∆Vo Vso ≤ 0.8V Vso - *6 IHOB Vso = 5.0V, Vsx = 4.0V - - -100 A *6 ILOB Vso = 0.0V, Vsx = 1.0V 100 - - A *6 - - TBD S *9 - - - A *7 - TBD TBD A *8 - TBD TBD A *8 tSD Istby IVDD IVCI AVDD = 5.5V GVDD = 5.0V SAP = “001” Standby mode, Ta = 25 °C No load, Ta = 25 °C Notes : 5. 6. 7. 8. Vgo is the output voltage of analog output pins G0 to G177. Vsx is the voltage applied to analog output pins S1 to S396. Vso the output voltage of analog output pins S1 to S396 VDD3 = 3.0V, VDD = 2.0V, VCI = 2.7V, VBS = VSS and standby mode. VDD3 = 3.0V, VDD = 2.0V, VCI = 2.7V, VBS = VSS, fosc = 177 kHz(176 display line), Internal register, NL[4:0] = “10101”, RTN[3:0] = “0000”, DIV[1:0] = “00” Internal power registers, VC[2:0] = “011”, BT[2:0] = “010”, VRH[3:0] = “1100”, VRL[3:0] = “0110” VCM[4:0] = “10110”, VDV[4:0] = “10000” 105 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary AC CHARACTERISTICS Table 42. Parallel Write Interface Characteristics (68 Mode, HWM = 0) (VDD = 1.8V to 2.5V, TA = -30 to +85 oC) VDD3 = 1.8V to 2.5V VDD3 = 2.6V to 3.3V Min. Max. Min. tCYCW68 tCYCR68 600 800 - 250 500 tR , tF - 25 tWHW68 tWHR68 tWLW68 tWLR68 90 350 300 400 - RW, RS and CSB setup time tAS68 10 - 10 RW, RS and CSB hold time tAH68 5 - 2 Write data setup time tWDS68 60 - 60 Write data hold time tWDH68 15 - 2 Read data delay time tRDD68 - 200 - Read data hold time tRDH68 5 Characteristic Symbol Write Read Cycle time Pulse rise / fall time Write Read Write Read E pulse width high E pulse width low Unit Max. 25 40 250 70 200 - ns 200 5 Table 43. Parallel Write Interface Characteristics (68 Mode, HWM = 1) (VDD = 1.8V to 2.5V, TA = -30 to +85 oC) VDD3 = 1.8V to 2.5V VDD3 = 2.6V to 3.3V Min. Max. Min. tCYCW68 tCYCR68 200 800 - 100 500 tR , tF - 25 tWHW68 tWHR68 tWLW68 tWLR68 90 350 90 400 - RW, RS and CSB setup time tAS68 10 - 10 RW, RS and CSB hold time tAH68 5 - 2 Write data setup time tWDS68 60 - 60 Write data hold time tWDH68 15 - 2 Read data delay time tRDD68 Read data hold time tRDH68 Characteristic Cycle time Symbol Write Read Pulse rise / fall time E pulse width high E pulse width low 106 Write Read Write Read Unit - 25 40 250 40 200 200 5 Max. ns 200 5 S6D0110 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD Preliminary Table 44. Parallel Write Interface Characteristics (80 Mode, HWM = 0) (VDD = 1.8V to 2.5V, TA = -30 to +85 oC) VDD3 = 1.8V to 2.5V VDD3 = 2.6V to 3.3V Min. Max. Min. tCYCW80 tCYCR80 600 800 - 250 500 tR , tF - 25 tWLW80 tWLR80 tWHW80 tWHR80 90 350 300 400 - RW, RS and CSB setup time tAS80 10 - 10 RW, RS and CSB hold time tAH80 5 - 2 Write data setup time tWDS80 60 - 60 Write data hold time tWDH80 15 - 2 Read data delay time tRDD80 - 200 - Read data hold time tRDH80 5 Characteristic Symbol Write Read Cycle time Pulse rise / fall time Write Read Write Read Pulse width low Pulse width high Unit Max. 25 40 250 70 200 - ns 200 5 Table 45. Parallel Write Interface Characteristics (80 Mode, HWM = 1) (VDD = 1.8V to 2.5V, TA = -30 to +85 oC) VDD3 = 1.8V to 2.5V VDD3 = 2.6V to 3.3V Min. Max. Min. tCYCW80 tCYCR80 200 800 - 100 500 tR , tF - 25 tWLW80 tWLR80 tWHW80 tWHR80 90 350 90 400 - RW, RS and CSB setup time tAS80 10 - 10 RW, RS and CSB hold time tAH80 5 - 2 Write data setup time tWDS80 60 - 60 Write data hold time tWDH80 15 - 2 Read data delay time tRDD80 Read data hold time tRDH80 Characteristic Cycle time Symbol Write Read Pulse rise / fall time Pulse width low Pulse width high Write Read Write Read Unit - 25 40 250 40 200 200 5 Max. ns 200 5 107 132 RGB SOURCE & 176 GATE DRIVER WITH INTERNAL RAM FOR 65K COLORS TFT-LCD S6D0110 Preliminary Table 46. Clock Synchronized Serial Write Mode Characteristics (VDD = 1.8V to 2.5V, TA = -30 to +85 oC) Characteristic VDD3 = 1.8V to 2.5V VDD3 = 2.6V to 3.3V Min. Max. Min. Max. 0.1 20 us 20 ns Symbol Unit Serial clock cycle time tscyc 0.1 20 Serial clock rise / fall time tR , tF - 20 Pulse width high for write tSCHW 40 - 40 - ns Pulse width high for read tSCHR 230 - 230 - ns Pulse width low for write tSCLW 60 - 60 - ns Pulse width low for read tSCLR 230 - 230 - ns Chip Select setup time tCSS 20 - 20 - ns Chip Select hold time tCSH 60 - 60 - ns Serial input data setup time tSIDS 30 - 30 - ns Serial input data hold time tSIDH 30 - 30 - ns Serial output data delay time tSODD - 200 - 130 ns Serial output data hold time tSODH 5 - 5 - ns Table 46. Reset Timing Characteristics (VDD = 1.8V to 2.5V, TA = -30 to +85 oC) Characteristic Reset low pulse width 108 VDD3 = 1.8V to 2.5V VDD3 = 2.6V to 3.3V Min. Max. Min. Max. 1 - 1 - Symbol tRES Unit us