80CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B2104 INTRODUCTION The S6B2104 is a LCD driver IC, which is fabricated by low power CMOS high voltage process technology. This device consists of 80-bit bi-directional shift register, 80-bit data latch and 80 bit driver. FEATURES • Power supply voltage: +5V ± 10%, +3V ± 10% • Supply voltage for display: 6 to 28V (VDD-VEE) • Parallel data processing (4 bit) • Applicable LCD duty: 1/64 to 1/256 • Interface Drivers COM SEG (cascade) S6B0086 Other S6B2104 • High voltage CMOS process • 100 QFP or bare chip available 1 S6B2104 80CH SEGMENT DRIVER FOR DOT MATRIX LCD S1 S2 S3 S78 S79 S80 BLOCK DIAGRAM V1 V3 V4 VEE 80 bit 4- Level Driver M DISPOFFB CL1 80 bit Data Latch D0 D1 D2 D3 20 x 4 bit Bidirectional Register CL2 EIB 2 80 bit Level Shifter Shift CL Power Down Function SHL VDD VSS EOB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50 SC51 SC52 SC53 SC54 SC55 SC56 SC57 SC58 SC59 SC60 SC61 SC62 SC63 SC64 SC65 SC66 SC67 SC68 SC69 SC70 SC71 SC72 SC73 SC74 SC75 SC76 SC77 SC78 SC79 SC80 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SC30 SC29 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 SC18 SC17 SC16 SC15 SC14 SC13 SC12 SC11 SC10 S9 S8 S7 S6 S5 S4 S3 S2 S1 80CH SEGMENT DRIVER FOR DOT MATRIX LCD 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S6B2104 S6B2104 PIN CONFIGURATION 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 EIB CL1 NC CL2 D0 D1 D2 D3 VSS SHL VDD DISPOFFB M NC V1 V3 V4 VEE NC EOB 3 S6B2104 80CH SEGMENT DRIVER FOR DOT MATRIX LCD MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Operating voltage VDD -0.3 - 6.0 V Driver supply voltage VLCD 0 - 30 VIN -0.3 - VDD +0.3 Operating temperature TOPR -30 - +85 Storage temperature TSTG -55 - +150 Input voltage °C Voltage greater than above may result in damage to the circuit. VDD (V1) +V VDD-VEE V3 To LCD Panel S1 - S80 S6B2104 V4 VEE -V VSS 4 V1 > V3 > V4 > VEE V1 < VDD 80CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B2104 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 to 5.5V, VSS = 0V, Ta = -30 to +85°C, CL = 15pF) Characteristics Symbol Operating voltage VDD Driver supply voltage VLCD Input voltage (1) Output voltage (2) Condition VLCD = VDD - VEE Min Typ Max Unit 2.7 - 5.5 V 6 - 28 VIH - 0.8VDD - - VIL - 0 - 0.2VDD VOH IOH = -0.4mA VDD-0.4 - - VOL IOL = 0.4mA - - 0.4 Input leakage current 1 (1) IIL1 VIN = VDD to VSS -1 - 1 Input leakage current 2 (3) IIL2 VIN = VDD to VEE -25 - 25 On resistance (4) RON ION = 100µA - 2 4 kΩ Supply current ISTB fCL2 = 1MHz, VDD = 5.5V (5) - - 200 µA IDD fCL2 = 19.2kHz, VDD = 5.5V (6) - - 3 mA fM = 40Hz, VLCD = 26V VDD = 2.7V (6) - - 1 mA No Load VDD = 5.5V (7) - 150 500 µA IEE V µA NOTES: 1. Applied to CL1, CL2, EIB, EOB, D0 to D3, SHL, DISPOFFB, M pin. 2. EIB, EOB pin 3. V1, V3, V4 pin 4. VDD-VEE = 26V(VDD = 3V), VEE = 28V(VDD = 5V), V1 = VDD, V3 = VDD-2/10(VDD-VEE), V4 = VEE+2/10(VDD-VEE), S1 to S80 pin 5. Display data pattern: 0000, Current from VDD to VSS when the display data is not processing (SHL = VSS, D0 to D3 = VSS, DISPOFFB = VDD, M = VSS) 6. Display data pattern: 1010, Current from VDD to VSS when the display data is processing 7. Display data pattern: 1010, Current on VEE pin 5 S6B2104 80CH SEGMENT DRIVER FOR DOT MATRIX LCD AC Characteristics (VDD = +5V ± 10%, VSS = 0V, Ta = -30 to +85 °C, CL = 15pF) Characteristic Symbol Condition Min Typ Max Unit ns Clock cycle time tCYC Duty = 50% 125 - - Clock pulse width tW - 45 - - Clock rise/fall time tR/tF - - - 30 Data set-up time tDS - 30 - - Data hold time tDH - 30 - - Clock set-up time1 TCS1 - 80 - - Clock set-up time2 TCS2 - 10 - - Clock hold time tCH - 80 - - Propagation delay time tPHL EOB output - - 80 EIB output EIB, EOB set-up time tPSU 80 EOB input 30 - - EIB input 30 Min Typ Max Unit ns (VDD = +3V ± 10%, VSS = 0V, Ta = -30 to +85°C, CL = 15pF) Characteristic Symbol Condition Clock cycle time tCYC Duty = 50% 250 - - Clock pulse width tW - 95 - - Clock rise/fall time tR/tF - - - 30 Data set-up time tDS - 50 - - Data hold time tDH - 50 - - Clock set-up time1 TCS1 - 80 Clock set-up time2 tCS2 - 15 - - Clock hold time tCH - 120 - - Propagation delay time tPHL EOB output - - 155 EIB output EIB, EOB set-up time 6 tPSU 155 EOB input 65 EIB input 65 - - 80CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B2104 Timing Characteristics tw CL2 tF 0.8VDD tw 0.8VDD 0.2VDD 0.2VDD tDS D0 to D3 tw 0.8VDD tDH 0.2VDD tCS1 tCS2 CL1 tCH 0.8VDD tw 0.2VDD tR CL2 1 tF 2 19 0.2VDD 20 0.8VDD ~ ~ CL1 ~ ~ tPHL ~ ~ EOB, EIB (output) 0.2VDD tPUS ~ ~ EIB, EOB (input) 7 S6B2104 80CH SEGMENT DRIVER FOR DOT MATRIX LCD PIN DESCRIPTION Table 1. Pin Description Pin No VDD (40) I/O Name Power Operating voltage VSS (42) VEE (33) 8 Function Interface For logical circuit (+5V ± 10%, +3V ± 10%) 0V (GND) Power Negative supply voltage For LCD drive circuit Supply V1, V3, V4 (34-36) I LCD driver output voltage level Bias supply voltage terminals to drive the LCD. Bias voltage divided by the resistance is usually used as supply voltage source. (refer to note 1) Power S1-S80 (1-30, 51-100) O LCD driver output Display data output pin which corresponds to the respective latch contents. One of V1, V3, V4 and VEE is selected as a display driving voltage source according to the combination of the latched data level and M signal (refer to note 2) LCD CL2 (47) I Data shift clock Clock pulse input for the 4 bit parallel shift register. The data is shifted to 80 bit shift register at the falling edge of the clock pulse. The clock pulse, which was input when the enable bit (EIB/EOB) is not active condition, is invalid. Controller M (38) I Alternate signal for LCD driver output Alternate signal input pin for LCD driving. Normal frame inversion signal is input Controller CL1 (49) I Data latch clock The signal for latching the shift register contents is input to this terminal. CL1 pulse "H" level initializes power-down function block. Controller DISPOFFB (39) I Output level control (Display off) Control input pin for display data output level (S1S80). V1 level is output from S1-S80 terminal during "L" level input. LCD becomes non-selected by V1 level output from every output of segment drivers and every output of common drivers. Controller SHL (41) I Data shift control EOB and EIB can be used as either input terminal or output terminal according to the condition of SHL. The shifting direction of each data, D0-D3, the I/O condition of EOB and EIB, and the condition of SHL are described in the table below. (refer to note 3). VDD/VSS 80CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B2104 Table 1. Pin Description (Continued) Pin No I/O Nam e Function EOB,EIB I/O (31,50) Pin I/O EOB I Interface SHL Display data shiftdirection Description L D0: S1→S5… →S77 Enable input terminal of S6B2104. D1: S2→S6… →S78 EIB EIB D2: S3→S7… →S79 O I H D3: S4→S8… →S80 Enable output terminal of S6B2104. EIB is connected to next S6B2104's EOB when the S6B2104's are connected in series (cascade connection). D0: 80→S76… →S4 Enable input terminal of S6B2104. D1: 79→S75… →S3 EOB D2: 78→S74… →S2 O Enable output terminal of S6B2104. EOB is connected to next S6B2104's EIB when the S6B2104's are connected in series (cascade connection) EOB I L S1 S2 S3 S4 D D D D 0 1 2 3 Shift D D D D D D D D 0 1 2 3 0 1 2 3 D0 Shift Direction D1 D2 Last Data D3 EIB O EIB I H D D D D 0 1 2 3 Shift D D D D D D D D 0 1 2 3 0 1 2 3 Shift Direction First Data EOB First Data S73 S74 S75 S76 S77 S78 S79 S80 I S1 S2 S3 S4 D0-D3 (43-46) S73 S74 S75 S76 S77 S78 S79 S80 D3: 77→S73… →S1 D0 D1 D2 Last Data D3 O 9 S6B2104 80CH SEGMENT DRIVER FOR DOT MATRIX LCD Display data input Display data input pins for 4 bit parallel shift register and it is input synchronized with the clock pulse. The combination of D0-D3 level, M signal, display data output level and the display on the LCD panel is described on the table below. (DISPOFFB = H) D0-D3 M Display Data Output Level Display on the LCD L L V3 OFF H L V1 ON L H V4 OFF H H VEE ON Controller NOTES: 1. VDD C C C C C V1 R VDD V2 (to S6B0103) S1 - S80 R To LCD Panel V3 R V4 S6B2104 R V5 (to S6B0103) C VEE VSS V1, VEE Selected Level V3, V4 Nonselected Level n = 5 (1/64 duty) to 13 (1/256 duty) 2. X: 10 M Latched Data DISPOFFB Output level (S1- S80) L L H V3 L H H V1 H L H V4 H H H VEE X X L V1 Don’t care. 80CH SEGMENT DRIVER FOR DOT MATRIX LCD 3. S6B2104 - EOB and EIB pins works as input terminals. ENABLE F/F stops display data at "H" level input. ENABLE F/F starts display data at "L" level input. - EOB and EIB pins work as output terminals. These terminals are set to the "H" level immediately after ENABLE F/F is initialized by the load pulse. Upon completion of 80-bit serial/parallel conversion using the shift clock input from the CL2 terminal, these terminals are then set to the "L" level. - The operation of ENABLE F/F is terminated and held unchanged until the next load pulse is detected. (For cascade connection, refer to the application circuit drawing) POWER DOWN FUNCTION In order to reduce the power consumption, in case of cascade connection, S6B2104 has a "power down function". EIB EOB Enable input Enable output Enable L Disable H EOB of Nth driver is connected to EIB of (N+1)th driver S6B2104 CL1 19 20 1 2 ~ ~ 2 ~ ~ ~ ~ 1 19 20 19 20 20 CL2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1st EIB (input) 1st EOB (output) ~ ~ ~ ~ Shift CL2 ~ ~ ~ ~ ~ ~ ~ ~ 2nd EIB (input) ~ ~ ~ ~ 2nd EOB (output) 1 2 Shift CL2 ~ ~ ~ ~ ~ ~ SHL = H (EIB = Input, EOB = Output) First S6B2104’s EOB should be connected to second S6B2104’s EIB. . 11 S6B2104 80CH SEGMENT DRIVER FOR DOT MATRIX LCD Timing Chart- 1/200 Duty, 1/15 Bias 200 1 2 200 1 2 200 1 2 2 200 1 2 200 1 2 CL1 Latched Data M M CL1 D0 - D3 CL2 Latched Data 200 CL1 Latched Data L H L L H L H L M VDD (V1) V2 V3 V4 V5 VEE (V6) V1 = VDD V4 = VDD-8/10V 12 LCD V2 = VDD-1/10V V5 = VDD-9/10V LCD LCD V3 = VDD-2/10V V LCD = VDDVEE LCD L