Ordering number : EN4264A
Monolithic Digital IC
LB1824
Power Brushless Motor Driver
for OA Equipment
Overview
Package Dimensions
The LB1824 produces the direct PWM drive output
appropriate for the brushless motors used in office data
processing (OA) equipment, and integrates on a single
chip the speed control circuits, FG amplifier, and other
circuits required to form the drive circuit.
unit: mm
3147A-DIP28HS
[LB1824]
Features
•
•
•
•
•
•
•
•
•
•
Breakdown voltage: 30 V, output current: 2.5 A
Direct PWM drive output
Crystal oscillator circuit
Speed discriminator plus PLL speed control system
Forward/reverse switching circuit
Start/stop switching circuit
Current control circuit
Overheating protection circuit
Built-in FG amplifier
Lock detection output
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Output current
Symbol
Ratings
Unit
30
VM max
30
V
2.5
A
3
W
IO max
Allowable power dissipation
Conditions
VCC max
T ≤ 100 ms
Pd max1
The IC independently
Pd max2
With an arbitrary large heat sink
V
20
W
Operating temperature
Topr
–20 to +80
°C
Storage temperature
Tstg
–55 to +150
°C
Ratings
Unit
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Supply voltage range
VCC
9.5 to 28
Supply voltage range
VM
9 to 28
V
VFGS
0 to 8
V
FG Schmitt output, applied voltage
Fixed voltage output current
FG Schmitt output, output current
Lock detection output current
V
IO1
7 V output
0 to –20
mA
IO2
5 V output
0 to –20
mA
IO3
4 V output
0 to –15
mA
IFGS
0 to 5
mA
ILD
0 to 20
mA
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
93097HA (OT) / 52893TS A8-8630 No. 4264-1/9
LB1824
Electrical Characteristics at Ta = 25°C, VCC = VM = 24 V
Ratings
Parameter
ICC2
Output saturation voltage
Output leakage current
4 V fixed voltage output
Thermal shutdown operation
34
50
mA
8
11
mA
V
2.0
3.0
IO = 2A
2.7
4.2
V
100
µA
VH
IO = –10 mA
∆VH2
IO = –5 to –20 mA
Output voltage
VX
IO = –5 mA
Voltage variation
∆VX1
VCC = 9.5 to 28 V
Load variation
∆VX2
IO = –5 to –20 mA
Output voltage
VFG
IO = –5 mA
Voltage variation
∆VFG1
VCC = 9.5 to 28 V
Load variation
∆VFG2
IO = –5 to –15 mA
6.65
4.45
3.65
IHB
–4
VICM
1.5
Hall input sensitivity
7.0
7.35
V
50
200
mV
mV
40
200
4.80
5.15
V
50
200
mV
mV
5
200
4.0
4.35
V
40
200
mV
110
200
mV
–1
∆VIN
Input voltage low → high
VSLH
8
14
VSHL
VOH(CR)
2.8
3.1
3.4
Output low level voltage
VOL(CR)
0.8
1.1
1.4
Limiter
Thermal shutdown operating temperature
–7
R = 56 kΩ, C = 1000 pF
TSD
Hysteresis
∆TSD
Input offset voltage
VIO(FG)
Design target
0.4
0.5
150
180
IB(FG)
–1
VOH(FG)
IFG = –2 mA
Output low level voltage
VOL(FG)
IFG = 2 mA
100x gain
5.5
Open loop gain
f(FG) = 2 kHz
Output saturation voltage
VO(FGS)
IO(FGS) = 2 mA
Output leakage current
IL(FGS)
VO = 5 V
Output high level voltage
VOH(D)
Output low level voltage
IOL(D)
45
Lock detection
4.0
180
Forward/reverse pin
V
1.5
V
250
mV
2
kHz
dB
0.5
V
10
µA
4.3
V
1.1
V
512
Output high level voltage
VOH(P)
3.2
3.5
3.8
V
VOL(P)
1.2
1.5
1.8
V
Output low level voltage
VOL(LD)
0.15
0.5
ILD = 10 mA
Locking range
±6.25
IB(INT)
–0.4
Output high level voltage
VOH(INT)
3.7
Output low level voltage
VOL(INT)
Open loop gain
Operating frequency range
fOSC
VIH(S/S)
Input low level voltage
VIL(S/S)
RD(S/S)
30
VIH(F/R)
4.0
Input low level voltage
VIL(F/R)
Pull-down resistance
∆VIN
RD(F/R)
VX/2
MHz
5%
V
10
MHz
1.5
V
70
kΩ
1.5
V
70
kΩ
4.0
Input high level voltage
V
50
V
0.5
30
V
dB
1
Pull-down resistance
µA
V
1.2
1.6
–5%
Input high level voltage
Hysteresis
+0.4
4.3
0.8
V
%
60
Reference voltage
Start/stop pin
µA
51
0.8
Gain-bandwidth product
Crystal oscillator
+1
Output low level voltage
Input bias current
Integrator
mV
mV
0.1
Number of counts
PLL output
°C
+10
3
100
V
°C
6
1
V
Vp-p
0.6
50
–10
V
kHz
2.0
Output high level voltage
FG input sensitivity
mV
15
V(CR)
VCC –VM
mV
mV
Output high level voltage
Operating frequency range
Speed discriminator
24
Input voltage high → low
f(CR)
V
mVp-p
7
Next stage Schmitt width
FGS output
µA
5.1
60
Hysteresis
Oscillator frequency
Unit
IO = 1A
Load variation
Input bias current
FG amplifier
max
VOsat1
VCC = 9.5 to 28 V
Amplitude
Current control operation
typ
VOsat2
∆VH1
Common mode input voltage range
Oscillator
When stopped
Voltage variation
Input bias current
Hall amplifier
min
IOleak
Output voltage
5 V fixed voltage output
Conditions
ICC1
Current drain
7 V fixed voltage output
Symbol
50
V
No. 4264-2/9
LB1824
Allowable power dissipation, Pd max – W
Pd max – Ta
Ambient temperature Ta – °C
Pin Assignment
Equivalent Circuit Block Diagram
No. 4264-3/9
LB1824
Sample Application Circuit
AC Test Circuit Diagram
No. 4264-4/9
LB1824
Logic Table
F/R = Low
Parameter
Source → Sink
1
2
F/R = High
IN1
IN2
IN3
IN1
IN2
IN3
OUT3 → OUT2
H
H
L
OUT3 → OUT1
H
L
L
L
L
H
L
H
H
3
OUT2 → OUT3
L
L
4
OUT1 → OUT2
L
H
H
H
H
L
L
H
L
H
5
OUT2 → OUT1
H
L
6
OUT1 → OUT3
L
H
H
L
H
L
H
H
L
L
Note: ‘H’ for an input indicates the state where IN+ > IN–.
H: High
L: Low
The formula below gives the relationship between the crystal oscillator frequency (fOSC) and the FG frequency (fFG).
fFG (servo) = fOSC/(the ECL divider factor (16) × the number of counts)
= fOSC/8192
(External crystal oscillator circuit)
External Constants (reference values)
C1 (pF)
C2 (pF)
R (kΩ)
3 to 4
X’tal (MHz)
39
82
0.82
4 to 5
39
82
1.0
5 to 7
39
47
1.5
7 to 10
39
27
2.0
Note that the crystal used should have a ratio between the fundamental
wave fO impedance and 3fO impedance of 1:5 or greater.
Pin Functions
Pin name
IN1+, IN1–
IN2+, IN2–
IN3+, IN3–
Pin No.
20, 19
18, 17
16, 15
Function
OUT1 Hall input pin
OUT2 Hall input pin
OUT3 Hall input pin
OUT1
8
OUT2
9
Output pin 1
Output pin 2
OUT3
10
Output pin 3
VCC
3
Pin for the power supply applied to all blocks other than the output block
VM
14
Output block power supply pin. Also used for output current detection: connecting a resistor
(Rf) between this pin and VCC allows the output current to be detected as a voltage.
GND1
22
Ground for all blocks other than the output block
GND2
11
Output block ground
CR
7
Pin for setting the PWM oscillator frequency
INT IN
25
Integrator input pin
INT OUT
26
Integrator output pin (speed control pin)
D OUT
24
Speed discriminator output pin: overspeed → high
P OUT
27
PLL output pin
LD
23
Lock detection pin. Open collector output. Goes low when the motor speed is within the lock
range (±6.25%).
FG IN+
FG IN–
4
5
FG pulse input pin (4 V power supply pin)
FG OUT
6
FG amplifier output pin
FGS OUT
28
FG amplifier output pin (post-schmitt). Open collector output.
X’tal
21
Crystal oscillator pin. Connect the crystal oscillator to this pin.
5V
1
5 V power supply pin
7V
2
7 V power supply pin
S/S
13
Start/stop control pin
Start → low, stop → high
F/R
12
Forward/reverse control pin
Forward → low, reverse → high
No. 4264-5/9
LB1824
LB1824 Functional Description (including external components)
1.Speed control circuit
The LB1824 uses a combination of a speed discriminator circuit and a PLL circuit for speed control. The speed
discriminator circuit outputs an error signal once every two FG periods using a charge pump method. The PLL circuit
outputs a phase error signal once every FG period also using a charge pump method. As compared with earlier speed
control methods that used only a speed discriminator circuit, the combination of both a PLL circuit as well as a speed
discriminator circuit employed in the LB1824 results in improved suppression of speed variations in cases where
motors with large load variations are used. Since the FG servo frequency determined as shown in the formula below,
the motor speed is set by the FG pulse count and the crystal oscillator frequency.
fFG(servo) = fOSC/8192
fOSC = crystal oscillator frequency
2.Direct PWM drive
The LB1824 adopts a direct PWM drive method in order to reduce the power loss at the output. The output transistor is
always saturated when on, and it adjusts the motor drive power by varying the duty that the output is on. Since the
output switching is performed by the lower side transistor, Schottky diodes (D1, D2 and D3) must be attached between
OUT and VCC. (This is because if diodes with a short reverse recovery time are not used, through current will flow at
the instant that the lower side transistor turns on.) Normal forward current diodes can be used for the diodes between
OUT and GND.
3.Current control circuit
The current control circuit performs its control operation with a current determined by I = 0.5/Rf. (This limits the peak
current.) The control operation functions to reduce the on duty and thus suppress the current. No phase compensation
capacitor is required.
4. Speed locking range
The speed locking range is within ±6.25% of the set speed, and when the motor speed enters the locking range the
LD pin goes low (open collector output). When the motor speed is outside the locking range, the motor drive output
on duty is changed according to the speed error, thus implementing the control required to return the motor speed to
within the locking range.
5. PWM frequency
The PWM frequency is determined by the resistor R3 and the capacitor C6 that are attached to the CR pin.
• When R3 is connected to the 4 V fixed voltage power supply:
fPWM ≈ 1/(1.2 × C × R)
• When R3 is connected to the 7 V fixed voltage power supply:
fPWM ≈ 1/(0.5 × C × R)
Do not use a resistor of less than 30 kΩ for R3. A PWM frequency of about 15 kHz is desirable. If the PWM
frequency is too low, the motor could oscillate at the PWM frequency during motor constraint and become noisy
since the oscillation will be in the audible frequency range. On the other hand, if the PWM frequency is too high, the
output transistor switching time loss will increase.
6. Ground leading
GND1 (pin 22):
GND2 (pin 11):
ground for blocks other than the output block
output block ground
Connect D4, D5 and D6 to GND2. All other external components should be connected to GND1. The GND1 and
GND2 leads should be grounded at a single point at the connector. Since GND2 carries a large current, its lead
should be as short as possible.
No. 4264-6/9
LB1824
7. Output parasitic effect
Parasitism occurs when the voltage on an output pin falls more than –0.7 V below GND1 and GND2. (The –0.7 V
figure is reduced by the temperature characteristics.) Also, do not let the voltage on the output pins exceed VCC by
more than 1 V. When parasitism occurs, first speed control will be lost intermittently, and then, if it becomes larger,
the output transistors can be damaged. D1, D2 and D3 are used to prevent through currents, and Schottky diodes with
a low Vf should be used. Therefore the potential difference between the output pin and VCC will not be a serious
issue. Although normal forward current diodes can be used for D4, D5 and D6, care must be taken to keep the ground
leads short, as mentioned in item 6 above, to avoid parasitism.
8. External interface pins
• LD pin
Output type: open collector
Breakdown voltage: a maximum current voltage of 30 V
Saturation voltage variance reference value (at ILD = 10 mA)
0.10 V to 0.15 V
• FGS pin
Output type: open collector
Breakdown voltage: a maximum current voltage of 30 V
Saturation voltage variance reference value (at IFGS = 2 mA)
0.12 V to 0.18 V
FGS is the FG amplifier output converted to pulses by a hysteresis comparator (for high speed monitoring).
• Start/stop pin
Input type: PNP transistor base with a 50 kΩ pull-down resistor to ground
Threshold level (typical): about 2.6 V
Turns off the 4, 5 and 7 V fixed voltage power supplies in steps.
• F/R pin
Input type: PNP transistor base with a 50 kΩ pull-down resistor to ground
Threshold level (typical): about 2.2 V (high → low), about 2.7 V (low → high)
With a hysteresis of about 0.5 V.
F/R switching must be performed when stopped.Continued from preceding page.
9. Fixed voltage power supply temperature characteristics
• 4 V power supply: about –0.5 mV/°C (typical)
• 5 V power supply: about –0.6 mV/°C (typical)
• 7 V power supply: about –2.5 mV/°C (typical)
10. FG amplifier
The FG amplifier gain is set by R1 and R2 to be a gain of G = R2/R1. C4 and C5 determine the FG amplifier’s
frequency characteristics. (R1 and C4 form a high pass filter, and R2 and C5 form a low pass filter.) Since a Schmitt
comparator is connected following the FG amplifier, the FG amplifier’s output must be set to be over 250 mVp-p by
R1, R2, C4 and C5. (It is desirable that the FG output be between 1 to 3 Vp-p during normal motor rotation.)
11. External capacitors
• C3
C3 is required for FGIN+ pin fixed voltage power supply stabilization and for IC internal logic initial reset pulse
generation. Although a low capacitance is acceptable for the power supply stabilization function, a relatively large
capacitance (about 4.7 µF) is required for reset pulse generation. The reset pulse is generated when the FGIN+ pin
goes from 0 V to about 1.3 V. If the reset does not occur, it is possible that LD could go on briefly at start time. If
this phenomenon is not a problem, a value of 0.1 µF can be used for C3. After C3 has been charged to 4 V,
when VCC is turned off (or in stop mode) the charge on C3 is dissipated through an IC internal load resistance of
about 10 kΩ that is connected to ground.
No. 4264-7/9
LB1824
• C1 and C2
C1 and C2 are required for fixed voltage power supply stabilization. Since this IC adopts a direct PWM method
and a large current is switched at the output, noise is generated extremely easily. Accordingly, adequate
stabilization is required on the power supplies so that noise does not cause incorrect circuit operation.
The connections between C1, C2 and C3 and ground should be kept as short as possible. Special care should be
exercised with respect to C1, since its characteristics are easily influenced by grounding problems.
12. External resistors
• R4 and R5
R4 and R5 are used to apply a high level to the F/R pin. Since there is a pull-down resistance of about 50 kΩ on
the F/R input pin it goes low when open. A high level input to the F/R pin should be at least 4.0 V and not more
than 6.3 V.
• R15
R15 is used to apply a high level to the S/S pin. Since there is a pull-down resistance of about 50 kΩ on the S/S
input it goes low when open. (In the start state a high level input to the S/S pin should be at least 4.0 V and not
more than 6.3 V.) As is the case with the F/R pin, the resistance is divided into 2 resistors, and while this scheme
is resistant to noise (since the input impedance can be lowered), if noise is not a
problem the high level can be set by connecting a single resistor such as R15. (A value of 180 kΩ is
recommended.)
If the initial rise in VCC is slow (under about 10 V/ms) the motor may turn to some extent (in stop mode) when
VCC is first applied. This is because the S/S input voltage is resistor divided, and when VCC is under 12 V, the
input voltage will be under 2.6 V (the start input level). If the rise slope cannot be increased and this phenomenon
is a problem, it can be handled by connecting a capacitor between VCC and S/S.
13. Through currents due to the direct PWM method
In the direct PWM method through currents flow in the outputs due to the switching, e.g., when used in a discrete
structure or in LB1822 applications. This is due to the output transistor’s delay and parasitic capacitance. Previously,
an external capacitor was used to handle this kind of situation. However, the LB1824 provides internal circuit
measures to handle this problem, and no measures based on external components are required. Although an overshoot
with a duration of under 10 ns will appear on the RF voltage waveform during switching, this will not be a problem.
14. Oscillator
A crystal oscillator is normally used with the LB1824. If the speed control conditions are not critical, a ceramic
oscillator could be used. To avoid problems always consult the oscillator’s manufacturer concerning the oscillator
itself and the external resistances and capacitances used.
15. IC internal power dissipation calculation example (calculation for a VCC of 24 V and typical ratings)
• Power dissipation due to the power supply current (ICC)
At start time:
P1 = VCC × ICC1 = 24 × 34 m = 0.82 W
At stop time:
P2 = VCC × ICC2 = 24 × 8 m = 0.19 W
• Power dissipation when a –10 mA load current is taken from the 7 V fixed voltage output
P3 = (VCC – 7) × 10 m = 17 × 10 m = 0.17 W
• Power dissipation due to the output drive current (for an output on duty of 100%)
P4 = {(VCC – 1)2/8 k}+{(VCC – 2)2/10 k}
= (232/8 k) + (222/10 k) = 0.12 W
• Power dissipation in the output transistor (For IO = 2 A and an output on duty of 100%)
P5 = VOsat2 × IO = 2.7 × 2 = 5.4 W
Therefore the IC overall power dissipation is:
At stop time:
No. 4264-8/9
LB1824
P = P2 = 0.19 W
At start time:
P = P1 + P3 + P4 + P5 = 6.51 W
(for an output on duty of 100%)
16. Techniques for measuring the IC temperature increase
• Measurement with a thermocouple
When using a thermocouple to measure the IC temperature, the thermocouple should be attached to a fin. While
this measurement technique is simple, it is subject to large measurement errors if the IC is not in a stable heat
generation state.
• Measurement using the characteristics of an IC internal diode
We recommend using the parasitic diode between INT.IN and GND internal to the IC. (According to our data, ID
= 1 mA with about
1.8 mV/°C) Remove the external resistor when making the measurements.
17. Servo constants
When calculating the servo constants, they will be heavily dependent on the motor actually used. Since experience is
generally required, these constants should be determined by the motor manufacturer. We can provide the IC
characteristics data required for the servo constants calculations as well as frequency characteristics simulation data
for the filter constants set by the motor manufacturer.
If the resistor connected between DOUT and INT.IN (R10) is too small, C8 and C9 are too large, and R10 is too
large, speed errors will be likely to occur due to the speed discriminator cutoff current and the integrator input
current. Therefore, a 10 to 100 kΩ resistor should be used. If the resistor connected between POUT and INT.IN (R8)
is too small, the PLL system influence will become too large and the in-phase pull-in to locking will get worse.
Therefore, do not make this value too small. (We recommend 1 MΩ when R10 is 75 kΩ.) First set the constants just
for the speed discriminator system (R9, R10, C8 and C9) and then set the R8 value for the PLL system.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 1997. Specifications and information herein are subject to
change without notice.
No. 4264-9/9