SANYO LB1923M

Ordering number : ENN6067A
Monolithic Digital IC
LB1923M
Power Brushless Motor Pre-Driver IC
for OA Equipment
The LB1923M is a pre-driver IC that supports direct
PWM drive and is appropriate for the power brushless
motors used in office automation equipment. A motor
drive circuit with the desired output capability (voltage
and current characteristics) can be constructed by
attaching a driver array at the IC output. The LB1923M
includes on chip a speed control circuit that allows the
motor speed to be varied using an external clock.
including lock protection, current limiter, and
thermal shutdown protection circuits.
Package Dimensions
unit: mm
3148A-QFP44MA
[LB1923M]
13.2
10.0
1.0
Overview
10.0
Direct PWM drive output
Speed discriminator + PLL speed control circuit
FG and integrating amplifiers
Forward/reverse switching circuit
Braking circuit (short braking)
Speed lock detection output
Full complement of on-chip protection circuits,
44
1
0.8
0.2
0.35
(1.0)
2.8max
(2.5)
•
•
•
•
•
•
•
13.2
Features
0.1
Specifications
SANYO: QIP44MA
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Maximum supply voltage
VCC max
Maximum input current
IREG max
Output current
IO max
Allowable power dissipation
Pd max
Conditions
Ratings
VREG pin
UL, VL, and WL outputs
Unit
9
V
10
mA
30
mA
0.9
W
Operating temperature
Topr
–20 to +80
°C
Storage temperature
Tstg
–55 to +150
°C
Ratings
Unit
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Supply voltage
VCC
Input current range
IREG
FG Schmitt output applied voltage
VFGS
0 to 8
V
FG Schmitt output current
IFGS
0 to 5
mA
ILD
0 to 20
mA
Lock detection output current
4.4 to 7.0
VREG pin (7 V)
1 to 5
V
mA
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
42003AS (OT) / 63099TH (OT) No. 6067-1/17
LB1923M
Pd max — Ta
Allowable power dissipation, Pdmax – W
1.2
1.0
0.9
0.8
0.6
0.504
0.4
0.2
0
–20
0
20
40
60
80
100
120
Ambient temperature, Ta – °C
Electrical Characteristics at Ta = 25°C, VCC = 6.3 V
Parameter
Symbol
Conditions
Ratings
min
typ
ICC1
Current drain
Output saturation voltage
Output current
max
Unit
42
60
mA
ICC2
In stop mode
10
20
mA
ICC3
VCC = 5 V
38
55
mA
ICC4
VCC = 5 V, In stop mode
8
18
mA
0.2
0.7
V
–16
–12
mA
VO (sat)
IO
UL, VL, WL output, IO = 20 mA
UH, VH, WH output, VOUT = 1.4 V
–20
Output leakage current
IO leak
UL, VL, WL output
100
µA
Output off voltage
VO off
UH, VH, WH output
0.5
V
[Hall Amplifier]
Input bias current
IHB(HA)
–4
VICM
1.5
Hall input sensitivity
∆VIN(HA)
60
Hysteresis
Common-mode input voltage range
–1
µA
VCC – 1.5
V
mVp-p
∆VIN(HA)
17
32
60
mV
Input voltage low → high
VSLH
8
16
30
mV
Input voltage high → low
VSHL
–30
–16
–8
mV
V
[CR Oscillator]
Output high-level voltage
Output low-level voltage
Oscillator frequency
Amplitude
VOH(CR)1
3.1
3.4
3.7
VOH(CR)2 VCC = 5 V
2.4
2.7
3.0
V
VOL(CR)1
1.5
1.8
2.1
V
1.1
1.4
1.7
VOL(CR)2
f (CR)
VCC = 5 V
R = 75 kΩ, C = 1500 pF
V(CR)1
V(CR)2
19
V
kHz
1.4
1.6
1.8
Vp-p
VCC = 5 V
1.1
1.3
1.5
Vp-p
3.2
3.5
3.8
V
VCC = 5 V
2.5
2.8
3.1
V
0.8
1.1
1.4
V
VCC = 5 V
0.6
0.9
1.2
V
µA
[CROCK Oscillator]
Output high-level voltage
Output low-level voltage
VOH(RK)1
VOH(RK)2
VOL(RK)1
VOL(RK)2
External capacitor charge current
ICHG1
–17
–13
–9
External capacitor discharge current
ICHG2
9
13
17
Oscillator frequency
f (RK)
Amplitude
C = 0.068 µF
V(RK)1
V(RK)2
VCC = 5 V
35
µA
Hz
2.2
2.4
2.6
Vp-p
1.7
1.9
2.1
Vp-p
Continued on next page.
No. 6067-2/17
LB1923M
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
[VCO Oscillator]
Pin C output high-level voltage
Pin C output low-level voltage
VOH(C)1
VOH(C)2
4.1
4.3
4.6
V
VCC = 5 V
3.2
3.4
3.6
V
3.6
3.9
4.1
V
VCC = 5 V
2.8
3.0
3.2
V
VOL(C)1
VOL(C)2
Oscillator frequency
f (C)
1.0
MHz
Amplitude
V(C)
0.2
0.4
0.6
Vp-p
VRF
0.47
0.52
0.57
V
150
180
°C
30
°C
[Current Limiter Operation]
Limiter
[Thermal Shutdown Operation]
Thermal shutdown operating temperature
Hysteresis
TSD
Design target value*
∆TSD
Design target value*
[VREG Pin]
VREG pin voltage
VREG
6.7
VIO(FG)
IB(FG)
7.1
7.4
V
–10
+10
mV
–1
+1
µA
[FG Amplifier]
Input offset voltage
Input bias current
Output high-level voltage
VOH(FG)
Output low-level voltage
VOL(FG)
FG input sensitivity
VCC – 1.5
VCC – 1
1
Gain: 100×
Schmitt amplitude for the next stage
3
100
f (FG) = 2 kHz
45
V
mV
180
Operating frequency range
Open-loop gain
V
1.5
250
mV
16
kHz
51
dB
[FGS Output]
Output saturation voltage
VO(FGS)
IO(FGS) = 2 mA
Output leakage current
IL(FGS)
VO = VCC
0.1
0.5
V
10
µA
[Speed Discriminator Output]
Output high-level voltage
VOH(D)
Output low-level voltage
VOL(D)
VCC – 1.0
VCC – 0.7
0.4
V
1.1
V
[Speed Control PLL Output]
Output high-level voltage
Output low-level voltage
VOH(P)1
VOH(P)2
4.05
4.35
4.65
V
VCC = 5 V
3.25
3.55
3.83
V
1.85
2.15
2.45
V
VCC = 5 V
1.25
1.55
1.85
V
0.4
11
V
0.1
0.5
V
10
µA
+6.25
%
VOL(P)1
VOL(P)2
[VCO PLL Output]
Output high-level voltage
VOH(VCO)
Output low-level voltage
VOL(VCO)
5.3
5.6
V
[Lock Detection]
Output saturation voltage
Output leakage current
VOL(LD)
IL(LD)
ILD = 10 mA
VO = VCC
Lock range
–6.25
[Integrator]
Input offset voltage
Input bias current
VIO(INT)
–10
+10
mV
IB(INT)
–0.4
+0.4
µA
Output high-level voltage
VOH(INT)
Output low-level voltage
VOL(INT)
VCC – 1.2
0.8
Open-loop gain
V
1.2
60
Gain-bandwidth product
Reference voltage
VCC – 0.8
1.6
VB(INT)
–5%
V
dB
VCC/2
MHz
5%
V
+0.4
µA
[Filter Amplifier]
Input bias current
IB(FIL)
Output high-level voltage
VOH(FIL)
Output low-level voltage
VOL(FIL)
Reference voltage
–0.4
VCC – 1.2
VB(FIL)1
VB(FIL)2
Note: * Design target value. These items are not tested.
VCC = 5 V
VCC – 0.8
V
0.8
1.2
V
–5%
2.0
+5%
V
1.5
1.6
1.7
V
Continued on next page.
No. 6067-3/17
LB1923M
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
[S/S Pin]
Output high-level voltage
VOH(S/S)
4.0
VCC
V
Output low-level voltage
VOL(S/S)
0
1.5
V
∆VIN(S/S)1
0.35
0.45
0.55
V
∆VIN(S/S)2 VCC = 5 V
0.24
0.34
0.44
V
RU(S/S)
45
63
85
Input high-level voltage
VIH(F/R)
4.0
VCC
V
Input low-level voltage
VIL(F/R)
0
1.5
V
Hysteresis
Pull-up resistance
kΩ
[F/R Pin]
∆VIN(F/R)1
0.35
0.45
0.55
V
∆VIN(F/R)2 VCC = 5 V
0.24
0.34
0.44
V
RU(F/R)
45
63
85
Input high-level voltage
VIH(BR)
4.0
VCC
Input low-level voltage
VIL(BR)
0
1.5
V
V
Hysteresis
Pull-up resistance
kΩ
[BR Pin]
Hysteresis
Pull-up resistance
∆VIN(BR)1
0.35
0.45
0.55
∆VIN(BR)2 VCC = 5 V
0.24
0.34
0.44
45
63
85
RU(BR)
V
V
kΩ
[CLK Pin]
Input high-level voltage
VIH(CLK)
Design target value*
4.0
VCC
Input low-level voltage
VIL(CLK)
Design target value*
0
1.5
V
∆VIN(CLK)1 Design target value*
0.35
0.45
0.55
V
∆VIN(CLK)2 VCC = 5 V, Design target value*
0.24
0.34
0.44
45
63
85
kΩ
16
kHz
Hysteresis
Pull-up resistance
RU(CLK)
Input frequency
f (CLK)
V
V
[N1 Pin]
Input high-level voltage
VIH(N1)
4.0
VCC
Input low-level voltage
VIL(N1)
0
1.5
V
V
Hysteresis
∆VIN(N1)1
0.35
0.45
0.55
∆VIN(N1)2 VCC = 5 V
V
0.24
0.34
0.44
RU(N1)
45
63
85
Input high-level voltage
VIH(N2)
4.0
VCC
Input low-level voltage
VIL(N2)
0
1.5
V
V
Pull-up resistance
V
kΩ
[N2 Pin]
Hysteresis
Pull-up resistance
∆VIN(N2)1
0.35
0.45
0.55
∆VIN(N2)2 VCC = 5 V
0.24
0.34
0.44
45
63
85
RU(N2)
V
V
kΩ
[Low Voltage Protection]
Operating voltage
VSDL
3.75
V
Release voltage
VSDH
4.0
V
Hysteresis
∆VSD
0.15
0.25
0.35
V
Note: * Design target value. These items are not tested.
Speed Discriminator Counts
N1
N2
High or open
High or open
Number of counts
64
High or open
L
256
L
High or open
128
L
L
512
No. 6067-4/17
LB1923M
Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN–.)
F/R=L
Item
F/R=H
Output
IN1
IN2
IN3
IN1
IN2
IN3
Source
Sink
1
H
L
H
L
H
L
VH
UL
2
H
L
L
L
H
H
WH
UL
3
H
H
L
L
L
H
WH
VL
4
L
H
L
H
L
H
UH
VL
5
L
H
H
H
L
L
UH
WL
6
L
L
H
H
H
L
VH
WL
S/S Pin
BRK Pin
High or open
Stop
High or open
Brake
L
Start
L
Released
VREG
VCC
WH
WL
VH
VL
UH
UL
RF
IN3–
IN3+
Pin Assignment
33
32
31
30
29
28
27
26
25
24
23
CR 34
22 IN2–
CROCK 35
21 IN2+
R 36
20 IN1–
C 37
19 IN1+
(frame) GND 38
18 GND (frame)
LB1923M
(frame) GND 39
17 GND (frame)
(frame) GND 40
16 GND (frame)
FILO 41
15 FGIN+
FILI 42
14 FGIN–
INTREF 43
13 FGOUT
TOC 44
1
2
3
4
5
6
7
8
9
10
11
INTOUT
INTIN
DOUT
POUT
LD
BR
F/R
CLK
S/S
N1
N2
12 FGSOUT
Top view
A11831
No. 6067-5/17
LB1923M
Pin Functions
Pin
Pin No.
IN1+, IN1–
IN2+, IN2–
IN3+, IN3–
19, 20
21, 22
23, 24
Function
UH
VH
WH
27
29
31
UL
VL
WL
26
28
30
These are open collector sink outputs.
Hall inputs for the phases
The logic high level corresponds to the state VIN+ > VIN–.
Outputs. These are fixed-current source outputs.
The duty is controlled by the output pin PWM.
VCC
32
A capacitor must be inserted between this pin and ground to prevent noise entering the circuit.
VREG
33
7-V shunt regulator output
GND
16 to 18
38 to 40
CR
34
Used to set the PWM circuit oscillator frequency.
CROCK
35
Motor lock protection circuit. Reference signal oscillator connection. Used by the circuit that prevents incorrect
operation if the clock line is disconnected.
A capacitor must be inserted between this pin and ground.
R
36
VCO circuit. This pin sets the charge and discharge current. A resistor must be inserted between this pin and ground.
C
37
VCO oscillator connection. A capacitor must be inserted between this pin and ground. Select a value for that capacitor
such that the C pin oscillator frequency does not exceed 1 MHz.
Ground
FILI
42
Inverting input to the VCO filter amplifier. This pin is connected to the VCO PLL through an (IC internal) 10-kW resistor.
FILO
41
VCO filter amplifier output. This pin is connected to the VCO circuit internally.
DOUT
3
Speed discriminator output. A low level is output when the motor is over speed.
ROUT
4
PLL circuit output. Outputs the result of the phase comparison between 1/2fCLK and 1/2fFG.
LD
5
Lock detection output. This is an open collector output.
This pin outputs a low level when the motor speed is within the locked range (±6.25%).
INTREF
43
Integrating amplifier noninverting input (the 1/2 VCC potential)
INTIN
2
Integrating amplifier inverting input
INTOUT
1
Integrating amplifier output
TOC
44
Torque command input. Normally, this pin is connected to the INTOUT pin. Lowering the TOC pin potential increases
the torque by changing the PWM signal duty for the UL, VL, and WL outputs.
FGIN+
FGIN–
15
FG amplifier noninverting input (the 1/2 VCC potential). A capacitor must be inserted between this pin and ground.
14
FG amplifier inverting input
FGOUT
13
FG amplifier output
FGSOUT
12
FG amplifier (post-Schmitt) output. This is an open collector output.
RF
25
Output current detection. A resistor must be inserted between this pin and ground.
This resistor sets the maximum output current IOUT to be 0.5/Rf.
S/S
9
Start/stop control input. Apply a low level for start, and either a high level or an open (high-impedance) state for start.
F/R
7
Forward/reverse control input. Apply a low level for forward, and either a high level or an open (high-impedance) state
for reverse.
BR
6
Braking control input (short braking operation). Apply a low level for start, and either a high level or an open (highimpedance) state to brake the motor.
CLK
8
External clock signal input. 10 kHz max.
N1
10
N2
11
Speed discriminator count value selection inputs
No. 6067-6/17
+
–
VREG
VREG
FILI
CLK
+
–
CLK
FGIN+
FGIN–
FGO
+
–
FILO
C
R
VCO
VCO
system PLL
FG
RST
FG
FILTER
FGS
N1
N1
1/N
LD
LD
N2
N2
Speed control
system PLL
Speed
discriminator
DOUT
GND
INT
IN
CR
CR
OSC
1.3VREF
VCC
LVSD
INT
POUT REF
+
–
RF
CURR
LIM
COMP
INT
OUT
BR
BR
TSD
TOC
S/S
S/S
PRI DRIVER
LOGIC
HALL
HYS
AMP
ROCK
OSC
F/R
FR
UL VL WL UH VH WH
LOGIC
VCC
IN3–
IN3+
IN2–
IN2+
IN1–
IN1+
A11833
CROCK
LB1923M
Internal Equivalent Circuit Block Diagram
No. 6067-7/17
LB1923M
Sample Application Circuit
24V
+
+
33
32
31
30
28
27
26
25
24
23
34
22
35
21
36
20
37
19
38
18
LB1923M
39
+
29
17
40
16
41
15
42
14
43
13
44
12
1
2
3
4
5
6
LD
BR
7
8
9
F/R CLK S/S
10
11
FGS
A11832
No. 6067-8/17
LB1923M
IC Operation Description
1. Speed Control Circuit
This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed
discriminator and the PLL circuit output (using a charge pump technique) an error signal once every two FG periods.
As compared to the earlier technique in which only a speed discriminator circuit was used, the combination of a
speed discriminator and a PLL circuit allows variations in motor speed to be better suppressed when a motor that has
large load variations is used. The FG servo frequency is controlled to be the same frequency as the clock signal input
to the CLK pin. This means that the motor speed can be changed by changing the clock frequency.
2. VCO Circuit
The LB1821M includes an on-chip VCO circuit to generate the reference signal for the speed discriminator circuit.
The reference signal frequency is determined by the following formula.
fVCO = fCLK × number of counts
fVCO: Reference signal frequency
fCLK: Frequency of the externally input clock signal
The range over which the reference signal can be varied is determined by the resistor and capacitor connected to the
R pin (pin 36) and the C pin (pin 37) and by the VCO loop filter constants (the external constants connected to pins
41 and 42).
(Reference Values)
Supply voltage
R (kΩ)
VCC = 5 V
4.7
C (pF)
390
VCC = 6.3 V
4.7
820
The value of R must not be less than 2.7 kΩ.
Applications can handle a wider range of speed variations than would be possible if a fixed number of counts was
used by changing the number of discriminator counts (which is related to the divisor in the VCO circuit). The number
of counts can be switched between 64, 128, 256, and 512 by setting the N1 (pin 10) and N2 (pin 11) pins.
3. Output Drive Circuit
To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are
external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with
which the output is on. Since the (external) output switching is handled by the upper side output transistors, a
Schottky diode or similar device must be connected between the output (OUT) and ground. This is because a through
current will flows at the instant the upper side output transistors turn on if a diode with a short reverse recovery time
is not used. A rectifying diode can be used between OUT and VCC. Transistors that have no parasitic diodes must be
used for the lower side output transistors. If these transistors have parasitic diode components, then through currents
will occur due to the reverse recovery time of the parasitic diodes despite the inclusion of the external Schottky
diodes.
4. Current Limiter Circuit
The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.52 V (typical), Rf: current
detection resistor). The current limitation operation consists of reducing the output duty to suppress the current.
5. Speed Lock Range
The speed lock range is ±6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open
collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to
the speed error to control the motor speed to be within the lock range.
6. Notes on the PWM Frequency
The PWM frequency is determined by the resistor and capacitor connected to the CR pin.
fPWM ≈ 1/(0.48 × C × R)
A PWM frequency of between 15 and 25 kHz is desirable. If the PWM frequency is too low, the motor may resonate
at the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result
in audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. The external
resistor must not have a value under 30 kΩ.
No. 6067-9/17
LB1923M
7. Hall Input Signals
Input signals with an amplitude greater than the hysteresis (60 mV, maximum) are required for the Hall inputs. An
input amplitude of 100 mV or greater is desirable, taking noise and other considerations into account. The Hall input
DC voltage must be set to fall within the common-mode input voltage range specifications.
8. Forward/Reverse (F/R) Switching
The F/R pin can be used to switch the motor direction. The direction can be switched with the F/R pin even if the
motor is turning. The IC circuit is designed to compensate for the through currents that occur when the direction is
switched. However, caution is required with respect to increases in the VCC voltage (due to motor current returning to
the power system instantaneously) during direction switching. If this is a problem, try increasing the capacitance of
the capacitor connected between the power supply and ground.
9. Brake Switching
The LB1923M implements a short braking technique in which the upper side transistors (the external transistors) for
all phases are turned on. (The lower side transistors for all phases are turned off.) This means that the output current
during braking does not pass through the Rf (the current detection resistor) and therefore that the current limiter does
not function. Thus caution is required. During braking, the upper side transistors operate at a 100% duty, regardless
of the motor speed. The braking function can be operated and released in the start state. Thus motor start and stop
control can be performed from the brake pin with the S/S pin at the low level, i.e., with the system in the start state. If
the startup time is a problem, the motor can be started with a shorter startup time by using the brake pin for motor
start/stop control than it can with the S/S pin. (This is because the stop state is a power saving state, and restarting
from this state requires waiting the time required for the VCO circuit to stabilize.)
10. Constraint Protection Circuit
The LB1923M includes an on-chip constraint protection circuit to protect the IC and the motor in motor constraint
mode. If the LD output remains high (indicating the locked state) for a fixed period in the start state, the upper side
(external) transistors are turned off. This time is set by the capacitance of the capacitor attached to the CROCK pin. A
time of a few seconds can be set with a capacitance of under 0.1 µF.
<Set time (s)> ≈ 44 × C (µF)
To release the constraint protection state, the LB1923M must be set to either the stop state or the brake state, or
power must be reapplied. The CROCK pin must be connected to ground if the constraint protection circuit is not
used. However, note that the clock disconnection protection circuit described later cannot be used in this case.
11. Clock Disconnection Protection Circuit
If clock input stops with the LB1923M in the start state, this protection circuit operates and turns off the (external)
upper side output transistors. If the clock is reapplied, the IC resumes operation.
12. Low-Voltage Protection Circuit
The LB1923M includes a low-voltage protection circuit to protect against incorrect operation when power is first
applied or if the power-supply voltage (VCC) falls. The (external) upper side output transistors are turned off if VCC
falls under about 3.75 volts, and this function is cleared at about 4.0 volts.
13. Power Supply Stabilization
Since this IC is used in applications that draw large output currents, the power-supply line is subject to fluctuations.
Therefore, capacitors with capacitances adequate to stabilize the power-supply voltage must be connected between
the VCC pin and ground. If diodes are inserted in the power-supply line to prevent IC destruction due to reverse
power supply connection, since this makes the power-supply voltage even more subject to fluctuations, even larger
capacitors will be required.
14. Ground Lines
The signal system ground and the output system ground must be separated and a single ground point must be taken at
the connector. Since the output system ground carries large currents, this ground line must be made as short as
possible.
Output system ground ... Ground for Rf and the output diodes
Signal system ground ... Ground for the IC and the IC external components
No. 6067-10/17
LB1923M
15. VREG Pin
If a motor drive system is formed from a single power supply, the VREG pin (pin 33) can be used to create the powersupply voltage (about 6.3 V) for this IC. The VREG pin is a shunt regulator and generates a voltage of about 7 volts by
passing a current through an external resistor. A stable voltage can be generated by setting the current to value in the
range 1 to 7 mA. The external transistors must have current capacities of at least 80 mA (to cover the ICC + Hall bias
current + output current <source> requirements) and they must have voltage handling capacities in excess of the
motor power-supply voltage. Since the heat generated by these transistor may be a problem, heat sinks may be
required depending on the packages used. If the IC power-supply voltage (4.4 to 7.0 V) is provided from an external
circuit, apply that voltage directly to the VCC pin(pin 32). In that case, the VREG pin must either be left open or
connected to ground.
16. FG Amplifier
Normally, the FG amplifier is used to construct a filter amplifier such as that shown in the application circuit to reject
noise. Since a Schmitt comparator is connected after the FG amplifier, applications must set the amplification so that
the amplifier output amplitude is at least 250 mV p-p. (However, a setting that results in an amplitude of 1 to 3 V p-p
during steady-state rotation is desirable.) The capacitor connected between the FGIN+ pin (pin 15) and ground is
required for bias voltage stabilization and to generate the initial reset pulse for the internal logic. The reset pulse is
generated in the time it takes for the FGIN+ pin to go from 0 to about 1.3 V.
17. Integrating Amplifier
The integrating amplifier integrates the speed error pulses and the phase error pulses and converts them to a speed
command voltage. At the same time it also sets the control loop gain and frequency characteristics using external
components. The integrating amplifier output (pin 1) is normally connected to the TOC pin (pin 44) by an external
line. Separating the integrating amplifier output and the PWM control circuit allows applications to switch the
integrating amplifier constants using an external operational amplifier, analog switch, or other circuit. This is useful
in applications that require integration constant switching due to a wide range of variability in the motor speeds that
must be provided.
18. VCO Filter Amplifier
The VCO filter amplifier converts the VCO system PLL output to the VCO voltage. The amplifier input resistor
(about 10 kΩ) is built in. Therefore, the gain and the frequency characteristics are set by the feedback resistor and the
feedback capacitor. Since the range of frequency variation supported becomes narrower as the gain is reduced, it is
desirable to set the gain of this amplifier to be 1 or higher.
19. Startup Techniques
If the motor is started and stopped repeatedly over a short period, the charge accumulated on the integrating
amplifier’s external capacitor may become a problem. (This can result in abnormal speed overshooting at startup and
other problems.) The circuit shown below can be effective at resolving this problem.
Integrating amplifier related external circuit
Added circuit
S/Ssignal
–
+
A11834
No. 6067-11/17
LB1923M
Pin Functions
Pin No.
Pin
Functions
Equivalent circuit
VCC
1
INTOUT
Integrating amplifier output (speed control)
1
20 kΩ
VCC
2
INTIN
Integrating amplifier inverting input
30 kΩ
43
43
INTREF
Integrating amplifier noninverting input
(a potential of 1/2 VCC)
200 Ω
200 Ω
2
30 kΩ
VCC
3
DOUT
Speed discriminator output
Acceleration → high, deceleration → low
3
VCC
4
POUT
Speed control system PLL output
Outputs the phase comparison result for
1/2 fCLK and 1/2 fFG.
4
VCC
5
LD
Speed lock detection output
Goes low when the motor speed is within the speed lock
range (±6.25%).
5
Continued on next page.
No. 6067-12/17
LB1923M
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
VCC
6
BR
Brake control (short braking operation)
Low: 0 to 1.5 V
High: 4.0 V to VCC
Goes high when left open.
High or open for brake mode operation.
The hysteresis is about 0.45 V.
63 kΩ
200 Ω
6
VCC
7
F/R
Forward/reverse control
Low: 0 to 1.5 V
High: 4.0 V to VCC
An open state functions as a high-level input.
Low for forward.
The hysteresis is about 0.45 V.
63 kΩ
200 Ω
7
VCC
8
CLK
External clock signal input
Low: 0 to 1.5 V
High: 4.0 V to VCC
An open state functions as a high-level input.
The hysteresis is about 0.45 V.
f = 10 kHz, maximum
63 kΩ
200 Ω
8
VCC
9
S/S
Start/stop control
Low: 0 to 1.5 V
High: 4.0 V to VREG
An open state functions as a high-level input.
Low for start.
The hysteresis is about 0.45 V.
63 kΩ
200 Ω
9
VCC
10
N1
Speed discriminator count switching
Low: 0 to 1.5 V
High: 4.0 V to VCC
An open state functions as a high-level input.
The hysteresis is about 0.45 V.
63 kΩ
200 Ω
10
Continued on next page.
No. 6067-13/17
LB1923M
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
VCC
11
N2
Speed discriminator count switching
Low: 0 to 1.5 V
High: 4.0 V to VCC
An open state functions as a high-level input.
The hysteresis is about 0.45 V.
63 kΩ
200 Ω
11
VCC
12
FGSOUT
12
FG amplifier output (after the Schmitt circuit)
This is an open collector output.
VCC
13
FGOUT
FG amplifier output
This pin is connected to the FG Schmitt comparator circuit
internally in the IC.
13
FG Schmitt comparator
VCC
20 kΩ
14
15
FGIN–
FGIN+
FG amplifier inputs
An initial reset is applied to the logic circuit block by
connecting a capacitor (of about 0.1 µF) between the FGIN+
pin and ground.
FG reset circuit
15
200 Ω
200 Ω
14
20 kΩ
16 to 18
38 to 40
GND
Ground connections
These pins are all connected internally to the frame.
Continued on next page.
No. 6067-14/17
LB1923M
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
VCC
19
20
21
22
23
24
IN1+
IN1–
IN2+
IN2–
IN3+
IN3–
Hall inputs
High is defined as IN+ > IN–, and low as the opposite.
An amplitude of 100 mV p-p (differential) or more is
desirable in the Hall signals. Connect capacitors between
the IN + and IN – pins if noise on the Hall signals causes
problems.
20 22 24
200 Ω
200 Ω
19 21 23
VCC
25
RF
Output current detection
Connect a resistor between this pin and ground.
The output limitation maximum current, IOUT, is set to be
0.52/Rf by this resistor.
200 Ω
25
VCC
26
28
30
UL
VL
WL
26 28 30
This IC implements duty control using output signal PWM.
These are open collector sink outputs.
VCC
27
29
31
UH
VH
WH
Outputs (Fixed current source outputs)
27 29 31
2 kΩ
32
VCC
Power-supply voltage
Connect a capacitor between this pin and ground for power
supply stabilization.
Continued on next page.
No. 6067-15/17
LB1923M
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
200 Ω
33
VREG
33
7-V shunt regulator output
VCC
34
CR
PWM oscillator frequency setting
200 Ω
34
1 kΩ
VCC
35
CROCK
Sets the operating time for the lock protection circuit. A
protection operating time of about 2.1 seconds can be set
by connecting a capacitor (of about 0.047 µF) between this
pin and ground.
200 Ω
35
VCC
36
R
Setting for the charge current used for the VCO circuit C pin
Connect a resistor between this pin and ground. The value
of that resistor must not be lower than 2.7 kΩ.
200 Ω
36
VCC
37
C
VCO oscillator connection. This pin sets the VCO
frequency.
Connect a capacitor between this pin and ground.
Set the value of the capacitor so that the oscillator
frequency does not exceed 1 MHz.
200 Ω
37
Continued on next page.
No. 6067-16/17
LB1923M
Continued from preceding page.
Pin No.
Pin
Functions
Equivalent circuit
VCC
200 Ω
41
FILO
VCO filter amplifier output
This pin is connected to the VCO circuit internally in the IC.
VCO
input
41
VCC
43 kΩ
10 kΩ
42
FILI
VCO filter amplifier inverting input
This pin is connected through a 10-kΩ resistor internally in
the IC to the VCO system PLL output.
200 Ω
VCO PLL
output
42
20 kΩ
VCC
44
TOC
Torque command input
This pin is normally connected to the INT.OUT pin.
When the TOC voltage falls, the PWM duty is increased.
Do not apply a voltage in excess of VCC - 0.5 V. (An input
from a normal operational amplifier is desirable.)
CR
oscillation
signals
200 Ω
44
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
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No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of April, 2003. Specifications and information herein are subject to
change without notice.
PS No. 6067-17/17