Ordering number : EN*5965
CMOS IC
LC74792, 74792JM
VPS / PDC Slicer IC
Preliminary
Overview
Package Dimensions
The LC74792/JM is a CMOS IC that provides PDC, VPS,
and UDT data acquisition functions. The LC74792/JM
supports microprocessor control of its operating modes
and microprocessor read out of data acquired in any of its
operating modes.
unit: mm
3067-DIP24S
[LC74792]
24
13
1
12
0.81
1.78
0.48
3.25
3.9max
3.3
21.2
0.51min
0.95
SANYO: DIP24S
unit: mm
3112-MFP24S
[LC74792JM]
5.4
6.35
7.6
13
24
12
1.8max
1
0.15
0.1
1.5
12.6
0.625
• VPS data acquisition (5 or 11 to 15 bytes)
VPS: Video Program System
• PDC (8/30/2) data acquisition (13 to 25 bytes)
PDC: Program Delivery Control
• UDT (8/30/1) data acquisition (13 to 25 bytes)
UDT: Unified Date and Time
• Header (X/00) data acquisition (14 to 45 bytes)
• Status display (8/30/1, 8/30/2) data acquisition (26 to
45 bytes)
• Automatic VPS/PDC discrimination mode
• Built-in AFC and sync separator circuits
• Synchronization discrimination circuit
0.25
7.62
6.4
Features
0.35
1.0 0.8
SANYO: MFP24S
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40299RM (OT) No. 5965-1/25
LC74792, 74792JM
Pin Assignment
No. 5965-2/25
LC74792, 74792JM
Pin Functions
Pin No.
Pin
1
VSS1
2
XtalIN
3
XtalOUT
4
CTRL1
Function
Description
Ground
Digital system ground
Crystal oscillator connections
Connections for the crystal element and capacitors that form the crystal oscillator. Also
used for external clock input (fsc, 2fsc, or 4fsc).
Crystal element switching
Switches between external clock input mode and crystal oscillator mode. Set this pin low
for crystal oscillator, and high for external clock input.
5
CS
Enable input pin
Enable input pin (hysteresis input)
6
SIO
Data input/output pin
Data input/output pin (hysteresis input)
7
SCLK
Clock input pin
Clock input pin (hysteresis input)
8
SYNCJDG
External synchronizing signal
discrimination output
External synchronizing signal presence/absence discrimination status output.
A high level is output when synchronizing signals are present.
This pin outputs the crystal oscillator clock when the RST pin is low.
(This reset state output can be disabled with command input.)
9
Hout
Horizontal synchronizing signal output
Horizontal synchronizing signal output
10
VSS2
Ground
Ground. (VCO circuit ground)
11
CPOUT
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
12
VCOIN
Oscillator control voltage input
VCO oscillation control voltage input
13
VCOR
Oscillator range adjustment
VCO oscillation range adjustment resistor connection
14
DAV
Data acquisition output
Outputs a low level when PDC/VPS data has been discriminated
15
VDD2
Power supply (+5 V)
Power supply (+5 V) (VCO system power supply)
16
SYNIN
Sync separator circuit input
Internal sync separator circuit video signal input
17
SEPC
Slice level output
Slice level verification
18
SEPOUT
Composite synchronizing signal output
Internal sync separator circuit composite synchronizing signal output
19
SEPIN
Vertical synchronizing signal input
Inputs the vertical synchronizing signal by integrating the SEPOUT pin output signal.
Applications must connect the SEPOUT pin to this pin through an integration circuit. If
unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.)
20
Vout
Vertical synchronizing signal output
Vertical synchronizing signal output
This pin outputs the VCO clock when the RST pin is low.
(This reset state output can be disabled with command input.)
21
CTRL2
SEPIN input control
Controls whether or not the VSYNC vertical synchronizing signal is input to the SEPIN
input.
When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.)
When high: The VSYNC signal is input.
22
CDLR
Clock phase adjustment
Connection for the clock phase adjustment resistor
23
RST
Reset input
System reset input.
A pull-up resistor is built in. (This input has hysteresis characteristics.)
24
VDD1
Power supply (+5 V)
Power supply. (+5 V: digital system power supply)
No. 5965-3/25
LC74792, 74792JM
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
VDD max
Input voltage
VIN
Output voltage
VOUT
Allowable power dissipation
Pd max
Conditions
Ratings
VDD1 and VDD2
Unit
VSS – 0.3 to VSS + 7.0
V
All input pins
VSS – 0.3 to VDD1 + 0.3
V
SIO, SYNCJDG, SEPOUT, DAV, HOUT, and VOUT
VSS – 0.3 to VDD1 + 0.3
Ta = 25°C
350
V
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
Ratings
Conditions
min
typ
Unit
max
VDD1
VDD1 and VDD2
5.5
V
VIH1
CS, SIO and SCLK
0.8 VDD1
5.5
V
VIH2
RST
0.8 VDD1
VDD1 + 0.3
V
VIH3
CTRL1 and CTRL2
0.7 VDD1
VDD1 + 0.3
V
VIL1
RST, CS, SIO and SCLK
VSS – 0.3
0.2 VDD1
V
VIL2
CTRL1 and CTRL2
VSS – 0.3
0.3 VDD1
Pull-up resistance
RPU
RST
Composite video signal input voltage
VIN1
SYNIN
VIN2
XtalIN (in external clock input mode)
fin = fsc, 2fsc, or 4fsc
High-level input voltage
Low-level input voltage
Input voltage
Oscillator frequency
4.5
5.0
V
25
50
90
kΩ
VDD1 = 5 V
1.5
2.0
2.5
Vp-p
VDD1 = 5 V
0.10
5.0
Vp-p
FOSC1
The XtalIN and XtalOUT oscillator pins (4fsc: PAL)
17.734
MHz
FOSC2
The XtalIN and XtalOUT oscillator pins (2fsc: PAL)
8.867
MHz
FOSC3
The XtalIN and XtalOUT oscillator pins (fsc: PAL)
4.433
MHz
Note that adequate measure must be taken to prevent noise from entering the XtalIN pin when it is used in clock input mode.
No. 5965-4/25
LC74792, 74792JM
Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.
Parameter
Output off leakage current
High-level output voltage
Symbol
Conditions
Ratings
min
typ
Unit
max
Ileak2
DAV and SIO
VOH1
SEPOUT, CPOUT, SYNCJDG,
HOUT, and VOUT
VDD1 = 4.5 V,
IOH = –1.0 mA
VOL1
SEPOUT, CPOUT, SYNCJDG,
DAV, HOUT, and VOUT
VDD1 = 4.5 V
IOL = 1.0 mA
1.0
V
VOL2
SIO
VDD1 = 5.0 V
IOL = 3.0 mA
0.4
V
1
µA
Low-level output voltage
1
IIH
RST, SIO, SCLK, CTRL1, CTRL2,
VIN = VDD1
VCOIN
IIL
SIO, SCLK, CTRL1, CTRL2,
VCOIN
VIN = VSS1
VDD1 and VDD2
With all outputs open
and a 17.734 MHz
crystal
Input current
Operating current drain
Applicable pins
IDD1
3.5
µA
V
–1
µA
40
mA
Timing Characteristics
[Write] (Refer to Figure 1) at Ta = –30 to +70°C, VDD1 = 5±0.5 V
Parameter
Minimum input pulse width
Data setup time
Data setup time
1-word write time
Symbol
tw (sclk)
Conditions
SCLK
Ratings
min
typ
max
Unit
200
ns
1
µs
CS
200
ns
tsu (sin)
SIN
200
ns
th (cs)
CS
2
µs
tw (cs)
CS pin (while CS = "H")
tsu (cs)
th (sin)
SIN
200
ns
tword
8-bit data write time
4.2
µs
twt
RAM data write time
1
µs
[Read] (Refer to Figure 2) (in case of N-ch open-drain type) at Ta = –30 to +70°C, VDD1 = 5±0.5 V
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
tCKCY
SCLK
2
µs
tCKL
SCLK
1
µs
tCKH
SCLK
1
µs
Data setup time
tICK
SCLK
10
µs
Output delay time
tCKO
SIO
Minimum input pulse width
0.5
µs
Note: In case of CMOS output type, depends on OSD timing.
No. 5965-5/25
LC74792, 74792JM
Figure 1 Serial Data Input Timing
(Test load)
Figure 2 Serial Data Input Timing (in case of N-ch open-drain type)
No. 5965-6/25
Sync separator and data
separator circuit
Interface
AFC circuit (VCO)
Data acquisition circuit
System Block Diagram
Synchronization
recognition circuit
Vertical
separator
circuit
Data latch
circuit
Timing generator
LC74792, 74792JM
No. 5965-7/25
LC74792, 74792JM
Control Commands
The control commands have an 8-bit serial input format. Commands consist of a command identification code in the first
byte and data in the following bytes.
Command 00: Data read mode set command
Command 0: Clock control command
Command 1: VPS/PDC control command 1
Command 2: VPS/PDC control command 2
Command 3: Synchronizing signal detection command 1
Command 4: Synchronizing signal detection command 2
Command 5: Output control command 1
Command 6: Output control command 2
Command 7: VPS/PDC control command 3
Command 8: VPS/PDC control command 4
Command 9: VPS/PDC control command 5
Command 10: VPS/PDC control command 6
Display Control Commands: 3-wire type
First byte
Command
Command ID code
Second byte
Data
Data
7
6
5
4
3
2
1
0
7
6
5
4
COMMAND00 read mode
1
0
0
0
0
0
0
0
Data read
3
2
1
0
COMMAND0 (Clock control)
1
1
1
1
0
0
0
0
0
FS
FS2
FS3
O
TST
MOD
O
SYS
RST
COMMAND1 (VPS/PDC control 1)
1
1
1
1
0
0
0
1
0
CPA
2
CPA
1
CPA
0
VPM
3
VPM
2
VPM
1
VPM
0
COMMAND2 (VPS/PDC control 2)
1
1
1
1
0
0
1
0
0
VMW VMW HBS
SE2 SEL
2
HBS
1
BMS
EMS
DCE
COMMAND3 (Synchronizing signal detection 1)
1
1
1
1
0
0
1
1
0
RN
2
RN
1
RN
0
SN
3
SN
2
SN
1
SN
0
COMMAND4 (Synchronizing signal detection 2)
1
1
1
1
0
1
0
0
0
0
RNE
0
SJN
3
SJN
2
SJN
1
SJC
1
SJC
0
COMMAND5 (Output control 1)
1
1
1
1
0
1
0
1
0
SP0
2
SP0
1
SP0
0
SJ0
1
SJ0
0
VNP
SEL
VSP
SEL
COMMAND6 (Output control 2)
1
1
1
1
0
1
1
0
0
0
NP1
NP0
VI0
SET
HI0
SET
V0T
KST
H0T
KST
COMMAND7 (VPS/PDC control 3)
1
1
1
1
0
1
1
1
0
0
ECV
15
ECV
14
ECV
13
ECV
12
ECV
11
ECV
5
COMMAND8 (VPS/PDC control 4)
1
1
1
1
1
0
0
0
0
ECP
19
ECP
18
ECP
17
ECP
16
ECP
15
ECP
14
ECP
13
COMMAND9 (VPS/PDC control 5)
1
1
1
1
1
0
0
1
0
0
ECP
25
ECP
24
ECP
23
ECP
22
ECP
21
ECP
20
COMMAND10 (VPS/PDC control 6)
1
1
1
1
1
0
1
0
0
HXA
LL2
LKA
SLC
MSK KMW
H1
SLH
3
SLH
2
SLH
1
Once written, the first byte command identification code is retained until the next first byte is written.
Data is written in second byte only continuous mode. (Automatic increment)
If COMMAND00 read mode is written, the read mode becomes fixed. The read mode is cancelled with CS "H".
No. 5965-8/25
LC74792, 74792JM
Command 00 (Data read mode set command)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
0
Command 00 identification code.
5
—
0
Clock settings.
4
—
0
Status
3
—
0
2
—
0
1
—
0
0
—
0
Notes
Function
• Second byte
Contents
DA 0 to 7
Register
7
—
—
6
—
—
5
—
—
4
—
—
3
—
—
2
—
—
1
—
—
0
—
—
Status
Notes
Function
Data read out
Command 0 (Clock Settings Command)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 0 identification code.
5
—
1
Clock settings.
4
—
1
Status
3
—
0
2
—
0
1
—
0
0
—
0
Notes
Function
• Second byte
DA 0 to 7
Register
7
—
6
5
FS
FS2
4
FS3
3
—
2
TSTMOD
1
—
0
SYSRST
Contents
Status
0
Notes
Function
Second byte identification bit
0
1
0
1
0
1
FS
FS2
FS3
Setting
0
0
0
2FSC
1
0
0
4FSC (CDLR can be deleted)
0
1
1
FSC
0
0
1
2FSC (CDLR can be deleted)
Setting for the frequency input to the
XtalIN pin (pin 2).
CDLR can be deleted: The resistor
connected to the CDLR pin may be
removed.
0
0
Normal operating mode
1
Test mode
This bit must be set to 0.
0
0
1
All registers are reset
No. 5965-9/25
LC74792, 74792JM
Command 1 (VPS/PDC control command 1)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 1 identification code.
5
—
1
VPS/PDC control settings 1.
4
—
1
Status
3
—
0
2
—
0
1
—
0
0
—
1
Notes
Function
• Second byte
DA 0 to 7
Register
7
—
6
CPA2
Contents
Status
0
0
1
0
5
CPA1
1
0
4
CPA0
Notes
Function
Second byte identification bit
CPA2
CPA1
CPA0
Clock
0
0
0
NO1
0
0
1
NO2
0
1
0
NO3
0
1
1
NO4
1
0
0
NO5
1
0
1
NO6
1
1
0
NO7
1
1
1
NO8
Data acquisition clock selection.
The clock can be shifted relative to
the data in units of 8 clock cycles.
1
0
3
VPM3
1
0
2
VPM2
1
0
1
VPM1
1
0
0
VPM0
M3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
M2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Operating mode
VPS
8/30/2 (PDC)
PDC and VPS automatic recognition 1
8/30/1 (UDT)
Header time 1
Header time 2
Header time 3
Header time 4
Status display 1
Status display 2
Status display 3
Status display 4
PAL PULSE
PDC and VPS automatic recognition 2
PDC and VPS automatic recognition 3
PDC and VPS automatic recognition 4
Slicer operating mode selection
1
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-10/25
LC74792, 74792JM
Command 2 (VPS/PDC control command 2)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 2 identification code.
5
—
1
VPS/PDC control settings 2.
4
—
1
Status
3
—
0
2
—
0
1
—
1
0
—
0
Function
Notes
• Second byte
DA 0 to 7
Register
7
—
6
VMWSE2
5
VMWSEL
4
HBS2
3
HBS1
2
1
0
Contents
Status
0
Second byte identification bit
0
From the vertical mask period start return period
1
From 10H before the vertical mask period start return period
0
The vertical mask period is the return period
1
The vertical mask period is 9H
0
Clock run discrimination 1 (2 times)
1
Clock run discrimination 2 (4 times)
0
Framing code discrimination 1
1
Framing code discrimination 2 (A single bad bit is ignored)
0
Error check enabled (The error check can be turned on or off on
per-byte basis.)
1
Error check disabled (Applications can select whether data with errors
is held or written for each byte.)
0
Data hold
1
Data write (Error bits are set to 0 in VPS mode)
0
Error check turned on for unused bytes
VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12
Header 1: bytes 14 to 37, 2: 14 to 29, 3 14 to 21.
Status 1 (3): bytes 7 to 25, status 2 (4) bytes 7 to 35.
1
Error check turned off for unused bytes
VPS: bytes 3, 4, and 6 to 10, PDC: bytes 7 to 12
Header 1: bytes 14 to 37, 2: 14 to 29, 3 14 to 21.
Status 1 (3): bytes 7 to 25, status 2 (4) bytes 7 to 35.
BMS
EMS
Function
DCE
Notes
CPOUT pin (pin 11) vertical mask
period switching 2
CPOUT pin (pin 11) vertical mask
period switching
Clock run discrimination circuit setting
Framing code discrimination selection
When set to 0: If there are no errors in bytes
for which the error check is turned on, those
bytes will be written to P-S (COM7-9).
When set to 1: Data is written to P-S
regardless of whether or not errors occurred.
When error checking is enabled, specifies the
processing when an error occurs in a byte for
which error checking was turned off
Error check setting for unused data
bytes
Biphase (VPS),
Hamming (PDC),
Odd parity (header)
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-11/25
LC74792, 74792JM
Command 3 (Synchronizing signal detection command 1)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 3 identification code.
5
—
1
Synchronizing signal detection settings 1.
4
—
1
Status
3
—
0
2
—
0
1
—
1
0
—
1
Notes
Function
• Second byte
DA 0 to 7
Register
7
—
6
RN2
5
RN1
4
RN0
3
SN3
2
SN2
1
SN1
0
SN0
Contents
Status
0
Notes
Function
Second byte identification bit
0
1
RN2
RN1
RN0
Number of HSYNC detections
0
0
0
0 (32)
0
0
1
4 (64)
0
1
0
8 (128)
1
0
0
16 (256)
0
1
0
1
External synchronizing signal detection
control.
Signal absent → present discrimination.
Sets the sampling period during which SYNC
is continuously detected in the horizontal
synchronizing signal period (1H).
Values in parentheses apply when RNE0
(COM4) is set to 1.
0
1
SN3
SN2
SN1
SNO
Number of HSYNC detections
0
0
0
0
0
No detection performed
32
1
0
0
0
1
0
0
0
1
0
64
1
0
1
0
0
128
0
1
0
0
0
256
External synchronizing signal
detection control.
Signal present → absent
discrimination.
Sets the sampling period during which
SYNC cannot be detected
consecutively in the horizontal
synchronizing signal period (1H).
1
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-12/25
LC74792, 74792JM
Command 4 (Synchronizing signal detection command 2)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 4 identification code.
5
—
1
Synchronizing signal detection settings 2.
4
—
1
Status
3
—
0
2
—
1
1
—
0
0
—
0
Notes
Function
• Second byte
Contents
DA 0 to 7
Register
7
—
0
6
—
0
5
RNE0
4
SJNS3
Status
Synchronization signal discrimination absent → preset: Normal values
1
Synchronization signal discrimination absent → preset: Values in parentheses
1
0
SJNS2
1
0
2
Second byte identification bit
0
0
3
Notes
Function
SJNS1
SJNS3
0
0
0
0
1
1
1
1
SJNS2
0
0
1
1
0
0
1
1
SJCS1
0
0
1
SJCS0
0
1
0
SJNS1
0
1
0
1
0
1
0
1
Count
None
4
8
16
32
64
128
256
Changes the values used for
synchronizing signal discrimination in
the absent → preset direction (COM3).
Setting for the noise exclusion circuit
used for synchronizing signal
discrimination in the absent → preset
direction.
If the number of H signal inputs during
a 1H period is greater than or equal to
the value listed in the table, the IC
determines that the signal is absent.
1
0
1
SJCS1
1
0
0
SJCS0
PAL
677 ns (1/3)
903 ns (1/4)
450 ns (1/2)
NTSC
558 ns (1/2)
838 ns (1/3)
1117 ns (1/4)
Synchronization discrimination.
HSYNI signal switching clock
selection.
1
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-13/25
LC74792, 74792JM
Command 5 (Output control command 1)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 5 identification code.
5
—
1
Output control settings 1
4
—
1
Status
3
—
0
2
—
1
1
—
0
0
—
1
Notes
Function
• Second byte
DA 0 to 7
Register
7
—
6
SPO2
Contents
Status
0
0
1
0
5
SPO1
1
0
4
SPO0
1
0
3
SJO1
1
0
2
SJO0
Notes
Function
Second byte identification bit
SPO2
0
0
0
0
1
1
1
1
SPO1
0
0
1
1
0
0
1
1
SJO1
0
0
1
1
SJO0
0
1
0
1
SPO0
0
1
0
1
0
1
0
1
SEPout pin
CSYNC
Slice data amplitude
O/E
CLK (acquisition)
VCO 1/1
VCO 1/2
VCO 1/3
VCO 1/4
SYNCJDG pin
SYNCJDG
LOCK
SYNCdet
DXout (Sliced data)
SEPOUT (pin 18) output switching
SYNCJDG (pin 8) output switching
1
1
VNPSEL
0
VSPSEL
0
Vertical signal falling edge detection
1
Vertical signal rising edge detection
0
VSEP: About 8.9 µs (NTSC)
1
VSEP: About 17.8 µs (NTSC)
Vertical signal acquisition polarity switching.
Only valid when internal vertical separation
used.
Internal vertical separation time switching
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-14/25
LC74792, 74792JM
Command 6 (Output control command 2)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 6 identification code.
5
—
1
Output control settings 2.
4
—
1
Status
3
—
0
2
—
1
1
—
1
0
—
0
Notes
Function
• Second byte
Contents
DA 0 to 7
Register
7
—
0
6
—
0
5
NP1
4
NP0
3
VIOSET
2
HIOSET
1
VOTKST
0
HOTKST
Status
Notes
Function
Second byte identification bit
0
PAL
1
NTSC
0
625
1
525
0
VSYNC signal output
1
Set up as a general-purpose port
0
HSYNC signal output
1
Set up as a general-purpose port
0
Negative polarity
(Lo)
1
Positive polarity
(Hi)
0
Negative polarity
(Lo)
1
Positive polarity
(Hi)
Number of scan lines
VOUT mode setting
HOUT mode setting
VOUT polarity selection.
Level in parentheses applies when set
up as a general-purpose port.
HOUT polarity selection.
Level in parentheses applies when set
up as a general-purpose port.
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-15/25
LC74792, 74792JM
Command 7 (VPS/PDC control command 3)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 7 identification code.
5
—
1
VPS/PDC control settings 3.
4
—
1
Status
3
—
0
2
—
1
1
—
1
0
—
1
Function
Notes
• Second byte
Contents
DA 0 to 7
Register
7
—
0
6
—
0
5
ECV15
4
ECV14
3
2
1
0
ECV13
ECV12
ECV11
ECV5
Status
Function
Notes
Second byte identification bit
0
Byte 15 biphase error check: on (data retained)
1
Byte 15 biphase error check: off (data written)
0
Byte 14 biphase error check: on (data retained)
1
Byte 14 biphase error check: off (data written)
0
Byte 13 biphase error check: on (data retained)
1
Byte 13 biphase error check: off (data written)
0
Byte 12 biphase error check: on (data retained)
1
Byte 12 biphase error check: off (data written)
0
Byte 11 biphase error check: on (data retained)
1
Byte 11 biphase error check: off (data written)
0
Byte 5 biphase error check: on (data retained)
1
Byte 5 biphase error check: off (data written)
VPS data specification when BMS is 0.
Items in parentheses are the
specification when BMS is 1.
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-16/25
LC74792, 74792JM
Command 8 (VPS/PDC control command 4)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 8 identification code.
5
—
1
VPS/PDC control settings 4.
4
—
1
Status
3
—
1
2
—
0
1
—
0
0
—
0
Function
Notes
• Second byte
DA 0 to 7
Register
7
—
Contents
Status
0
0
6
ECP19
1
0
5
ECP18
1
0
4
ECP17
1
0
3
ECP16
1
0
2
ECP15
1
0
1
ECP14
1
0
0
ECP13
1
Function
Notes
Second byte identification bit
Byte 19 Hamming error check on (Data retained)
{Bytes 44, 28, 36, 20,
32, 42, 32, 42}
Byte 19 Hamming error check off (Data written)
{Bytes 44, 28, 36, 20,
32, 42, 32, 42}
PDC data specification when BMS is 0.
Items in parentheses are the specification when
BMS is 1.
Items in curly braces are the bytes for which the
odd parity check is turned on or off for headers
1, 2, 3, and 4, and for status 1, 2, 3, and 4.
Byte 18 Hamming error check on (Data retained)
{Bytes 43, 27, 35, 19,
31, 41, 31, 41}
Byte 18 Hamming error check off (Data written)
{Bytes 43, 27, 35, 19,
31, 41, 31, 41}
Byte 17 Hamming error check on (Data retained)
{Bytes 42, 26, 34, 18,
30, 40, 30, 40}
Byte 17 Hamming error check off (Data written)
{Bytes 42, 26, 34, 18,
30, 40, 30, 40}
Byte 16 Hamming error check on (Data retained)
{Bytes 41, 25, 33, 17,
29, 39, 29, 39}
Byte 16 Hamming error check off (Data written)
{Bytes 41, 25, 33, 17,
29, 39, 29, 39}
Byte 15 Hamming error check on (Data retained)
{Bytes 40, 24, 32, 16,
28, 38, 28, 38}
Byte 15 Hamming error check off (Data written)
{Bytes 40, 24, 32, 16,
28, 38, 28, 38}
Byte 14 Hamming error check on (Data retained)
{Bytes 39, 23, 31, 15,
27, 37, 27, 37}
Byte 14 Hamming error check off (Data written)
{Bytes 39, 23, 31, 15,
27, 37, 27, 37}
Byte 13 Hamming error check on (Data retained)
{Bytes 38, 22, 30, 14,
26, 36, 26, 36}
Byte 13 Hamming error check off (Data written)
{Bytes 38, 22, 30, 14,
26, 36, 26, 36}
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-17/25
LC74792, 74792JM
Command 9 (VPS/PDC control command 5)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command 9 identification code.
5
—
1
VPS/PDC control settings 5.
4
—
1
Status
3
—
1
2
—
0
1
—
0
0
—
1
Function
Notes
• Second byte
Contents
DA 0 to 7
Register
7
—
0
6
—
0
5
4
3
Status
Byte 25 Hamming error check on (Data retained)
1
Byte 25 Hamming error check off (Data written)
0
Byte 24 Hamming error check on (Data retained)
1
Byte 24 Hamming error check off (Data written)
0
Byte 23 Hamming error check on (Data retained)
1
Byte 23 Hamming error check off (Data written)
ECP25
ECP24
ECP23
ECP22
1
0
1
ECP21
1
0
0
ECP20
1
Notes
Second byte identification bit
0
0
2
Function
PDC data specification when BMS is 0.
Items in parentheses are the
specification when BMS is 1.
Items in curly braces are the bytes for
which the odd parity check is turned on
or off for headers 1, 2, 3, and 4, and for
status 1, 2, 3, and 4.
Byte 22 Hamming error check on (Data retained)
{Bytes , , , ,
35, 45, 35, 45}
Byte 22 Hamming error check off (Data written)
{Bytes , , , ,
35, 45, 35, 45}
Byte 21 Hamming error check on (Data retained)
{Bytes , , , ,
34, 44, 34, 44}
Byte 21 Hamming error check off (Data written)
{Bytes , , , ,
34, 44, 34, 44}
Byte 20 Hamming error check on (Data retained)
{Bytes 45, 29, 37, 21,
33, 43, 33, 43}
Byte 20 Hamming error check off (Data written)
{Bytes 45, 29, 37, 21,
33, 43, 33, 43}
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-18/25
LC74792, 74792JM
Command 10 (VPS/PDC control command 6)
• First byte
Contents
DA 0 to 7
Register
7
—
1
First byte identification bit
6
—
1
Command A identification code.
5
—
1
VPS/PDC control settings 6.
4
—
1
Status
3
—
1
2
—
0
1
—
1
0
—
0
Notes
Function
• Second byte
DA 0 to 7
Register
7
—
6
5
4
HXALL2
LKASLC
MSKH1
3
KMW
2
SLH3
Contents
Status
0
Second byte identification bit
0
Slice data discrimination time: Normal
VPS/PDC data discrimination period
1
Discriminates the vertical return period data in all modes
setting
0
Normal operation
1
Always in the locked state
0
1
1
1
0
SLH2
1
0
0
AFC: A mask is applied to the horizontal signal
0
0
1
Notes
Function
SLH1
1
Forcibly set to high or low only during the CSYNC period
MODE
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
S321
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
0
1
0
x
x
1
0
1
0
1
0
x
x
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
x
x
Clock discrimination
1 1 x x 0 0 0 0
0 0 x x 1 1 1 1
1 x x x 0 0 0 0
0 x x x 1 1 1 1
1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1
0 0 0 x
1 1 1 x
0
1
0
1
0
1
0
1
x
x
0
1
x
x
x
x
x
x
x
x
x
x
x
x
Clock discrimination method switching
Note: All registers are cleared to 0 when the IC is reset by the RST pin.
No. 5965-19/25
LC74792, 74792JM
PDC/VPS Output Data Format
Data is read out in order starting with bit 7 of byte 1.
PDC 8/30/mode
Output data
Format1
Data update bit
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
VPS mode
Format2
Header time mode 1 (3)
Header time mode 2 (4)
bit0
1
2
3
4
5
6
7
byte38
bit0
1
2
3
4
5
6
7
byte22
bit0
1
2
3
4
5
6
7
byte39
bit0
1
2
3
4
5
6
7
byte23
bit0
1
2
3
4
5
6
7
byte40
bit0
1
2
3
4
5
6
7
byte24
bit0
1
2
3
4
5
6
7
byte41
bit0
1
2
3
4
5
6
7
byte25
bit0
1
2
3
4
5
6
7
byte42
bit0
1
2
3
4
5
6
7
byte26
bit0
1
2
3
4
5
6
7
byte43
bit0
1
2
3
4
5
6
7
byte27
If data has been updated, "0", not updated, "1".
Bit7
6
5
4
3
2
1
0
byte15
Bit7
6
5
4
3
2
1
0
byte16
Bit7
6
5
4
3
2
1
0
byte17
Bit7
6
5
4
3
2
1
0
byte18
Bit7
6
5
4
3
2
1
0
byte19
Bit7
6
5
4
3
2
1
0
byte20
bit0
1
2
3
4
5
6
7
byte16
bit0
1
2
3
4
5
6
7
byte18
bit0
1
2
3
4
5
6
7
byte20
bit0
1
2
3
4
5
6
7
byte22
bit0
1
2
3
4
5
6
7
byte14
bit0
1
2
3
4
5
6
7
byte24
byte17
byte19
byte21
byte23
byte15
byte25
bit0
1
2
3
bit0
1
2
3
byte11
bit0
1
2
3
bit0
1
2
3
byte12
bit0
1
2
3
bit0
1
2
3
byte13
bit0
1
2
3
bit0
1
2
3
byte14
bit0
1
2
3
bit0
1
2
3
byte5
bit0
1
2
3
bit0
1
2
3
byte15
(30)
(31)
(32)
(33)
(34)
(35)
(14)
(15)
(16)
(17)
(18)
(19)
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
Continued on next page.
No. 5965-20/25
LC74792, 74792JM
Continued from preceding page.
PDC 8/30/mode
Output data
Byte7
Format1
Bit7
6
5
4
3
2
1
0
byte21
Bit7
6
5
4
3
2
1
0
byte13
Bit7
6
5
4
3
2
1
0
byte14
Byte10
Bit7
6
5
4
3
2
1
0
byte22
bit0
1
2
3
4
5
6
7
Byte11
Bit7
6
5
4
3
2
1
0
byte23
bit0
1
2
3
4
5
6
7
Byte12
Bit7
6
5
4
3
2
1
0
byte24
bit0
1
2
3
4
5
6
7
Byte13
Bit7
6
5
4
3
2
1
0
byte25
bit0
1
2
3
4
5
6
7
Byte8
Byte9
VPS mode
Format2
bit0
1
2
3
4
5
6
7
byte13
bit0
1
2
3
4
5
6
7
Error
information 1
bit0
1
2
3
4
5
6
7
Error
information 2
bit0
1
2
3
1
1
1
1
byte16
17
18
19
20
21
22
23
1
1
1
1
1
1
1
0
Error
information
0
0
byte14
15
24
25
13
0
0
0
Header time mode 1 (3)
Header time mode 2 (4)
byte44
bit0
1
2
3
4
5
6
7
byte28
bit0
1
2
3
4
5
6
7
byte29
(36)
byte11
12
13
14
5
15
byte45
(37)
Error
byte38 (30)
information
39 (31)
40 (32)
41 (33)
42 (34)
43 (35)
44 (36)
45 (37)
(20)
(21)
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
Error
byte22 (14)
information
23 (15)
24 (16)
25 (17)
26 (18)
27 (19)
28 (20)
29 (21)
Note: Data with the value 1 is output for sections for which there is no output data setting.
No. 5965-21/25
LC74792, 74792JM
Data is read out in order starting with bit 7 of byte 1.
Status display 1 and 2: 8/30/2 Status display 1 and 2: 8/30/1
Output data
Status display mode 1 (3) Status display mode 2 (4)
Data update bit
Byte1
Bit7
byte26
6
5
4
3
2
1
0
Byte2
Byte3
Byte4
Byte5
Byte6
PAL Puls
If data has been updated, "0"
bit0
(26)
Bit7
6
5
4
3
2
1
0
byte27
Bit7
6
5
4
3
2
1
0
byte28
Bit7
6
5
4
3
2
1
0
byte29
Bit7
6
5
4
3
2
1
0
byte30
Bit7
6
5
4
3
2
1
0
byte31
(27)
(28)
(29)
(30)
(31)
byte36
1
2
3
4
5
6
7
(36)
bit0
1
2
3
4
5
6
7
byte37
bit0
1
2
3
4
5
6
7
byte38
bit0
1
2
3
4
5
6
7
byte39
bit0
1
2
3
4
5
6
7
byte40
bit0
1
2
3
4
5
6
7
byte41
(37)
(38)
(39)
(40)
(41)
bit0
bit0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
bit8
9
10
11
12
13
0
0
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
Note: Data with the value 1 is output for sections for which there is no output data setting.
Continued on next page.
No. 5965-22/25
LC74792, 74792JM
Continued from preceding page.
Output data
Byte7
Status display mode 1 (3) Status display mode 2 (4)
Bit7
byte32
6
5
4
3
2
1
0
Byte8
bit0
(32)
byte42
1
2
3
4
5
6
7
(42)
byte33
Bit7
6
5
4
3
2
1
0
byte34
Bit7
6
5
4
3
2
1
0
byte35
Byte11
Bit7
6
5
4
3
2
1
0
Error
byte26 (26)
information 1 27 (27)
28 (28)
29 (29)
30 (30)
31 (31)
32 (32)
33 (33)
Error
byte36 (36)
information 1 37 (37)
38 (38)
39 (39)
40 (40)
41 (41)
42 (42)
43 (43)
Byte12
Bit7
6
5
4
3
2
1
0
Error
byte34 (34)
information 2 35 (35)
0
0
0
0
0
0
Error
byte44 (44)
information 1 45 (45)
0
0
0
0
0
0
Byte9
Byte10
Byte13
(34)
(35)
bit0
1
2
3
4
5
6
7
byte43
bit0
1
2
3
4
5
6
7
byte44
bit0
1
2
3
4
5
6
7
byte45
1
2
3
4
5
6
7
Bit7
6
5
4
3
2
1
0
(33)
PAL Puls
bit0
(43)
(44)
(45)
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
bit0
1
2
3
4
5
6
7
Bit7
6
5
4
3
2
1
0
Note: Data with the value 1 is output for sections for which there is no output data setting.
No. 5965-23/25
LC74792, 74792JM
Sample Application Circuit
• Using an external system clock
Microcontroller
No. 5965-24/25
LC74792, 74792JM
• Using a crystal oscillator
Microcontroller
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of April, 1999. Specifications and information herein are subject to
change without notice.
PS No. 5965-25/25