HP4410DY Data Sheet December 2001 10A, 30V, 0.0135 Ohm, Single N-Channel, Logic Level Power MOSFET Features • Logic Level Gate Drive This power MOSFET is manufactured using an innovative process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. • 10A, 30V • rDS(ON) = 0.0135Ω at ID = 10A, VGS = 10V • rDS(ON) = 0.020Ω at ID = 8A, VGS = 4.5V • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Ordering Information PART NUMBER HP4410DY PACKAGE SO-8 SOURCE(1) DRAIN(8) SOURCE(2) DRAIN(7) SOURCE(3) DRAIN(6) GATE(4) DRAIN(5) BRAND P4410DY NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HP4410DYT. Packaging SO-8 ©2001 Fairchild Semiconductor Corporation HP4410DY Rev. B HP4410DY Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified HP4410DY UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 30 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 30 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±16 V Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (10µs Pulse Width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 10 50 A A Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 0.02 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TA = 25oC to 125oC. Electrical Specifications TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 30 - - V Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 9) 1 - - V VDS = 30V, VGS = 0V - - 1 µA VDS = 30V, VGS = 0V, TA = 55oC - - 25 µA VGS = ±16V - - 100 nA ID = 8A, VGS = 4.5V (Figures 6, 8) - 0.015 0.020 Ω ID = 10A, VGS = 10V (Figures 6, 8) - 0.011 0.0135 Ω VDD = 25V, ID ≅ 1A, RL = 25Ω, VGEN = 10V, RGS = 6Ω - 15 30 ns - 9 20 ns td(OFF) - 70 100 ns tf - 20 80 ns - 35 60 nC Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance IGSS rDS(ON) Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Total Gate Charge Qg(TOT) VDS = 15V, VGS = 10V, ID ≅ 10A Gate to Source Charge Qgs - 7.5 - nC Gate to Drain Charge Qgd - 5.8 - nC Input Capacitance CISS - 1600 - pF Output Capacitance COSS - 685 - pF Reverse Transfer Capacitance CRSS - 115 - pF Thermal Resistance Junction to Ambient RθJA - - 50 oC/W MIN TYP MAX UNITS ISD = 2.3A (Figure 7) - 0.75 1.1 V ISD = 2.3A, dISD/dt = 100A/µs - 50 80 ns VDS = 25V, VGS = 0V, f = 1MHz (Figure 4) Pulse Width < 10s (Figure 11) Device Mounted on FR-4 Material Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time ©2001 Fairchild Semiconductor Corporation SYMBOL VSD trr TEST CONDITIONS HP4410DY Rev. B HP4410DY Typical Performance Curves 50 VGS = 10V - 5V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 4V 40 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 50 Unless Otherwise Specified 30 3V 20 10 40 30 20 10 TA = 125oC 25oC 0 0 0 2 4 8 6 10 0 1 VDS, DRAIN TO SOURCE VOLTAGE (V) 4 5 4200 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0.025 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 3500 C, CAPACITANCE (pF) ON STATE RESISTANCE (W) 3 FIGURE 2. TRANSFER CHARACTERISTICS 0.030 rDS(ON), DRAIN TO SOURCE 2 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 1. OUTPUT CHARACTERISTICS 0.020 VGS = 4.5V 0.015 0.010 VGS = 10V 2800 2100 CISS 1400 COSS 0.005 CRSS 700 0 0 0 10 20 30 40 50 0 6 12 18 24 VDS , DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) FIGURE 3. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 4. 10 30 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 2.0 VPULSE DURATION = 80µs DS = 15V DUTY CYCLE = 0.5% MAX ID = 10A NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS , GATE TO SOURCE VOLTAGE (V) -55oC 8 6 4 2 0 0 9 18 27 36 45 Qg, GATE CHARGE (nC) FIGURE 5. GATE TO SOURCE VOLTAGE vs GATE CHARGE ©2001 Fairchild Semiconductor Corporation VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 10A 1.5 1.0 0.5 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (oC) 125 150 FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE HP4410DY Rev. B HP4410DY Typical Performance Curves Unless Otherwise Specified (Continued) 0.10 TJ = 150oC rDS(ON), DRAIN TO SOURCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TJ = 25oC 10 ON STATE RESISTANCE (W) ISD, SOURCE TO DRAIN CURRENT (A) 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0.08 0.06 ID = 10A 0.04 0.02 0 1 0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 0 VSD, SOURCE TO DRAIN VOLTAGE (V) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. SOURCE TO DRAIN DIODE VOLTAGE FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE TO SOURCE VOLTAGE 0.4 80 60 0.0 POWER (W) VGS(TH) VARIANCE (V) 0.2 ID = 250µA -0.2 -0.4 40 20 -0.6 -0.8 -50 0 -25 25 50 75 100 125 150 0 0.01 TJ, JUNCTION TEMPERATURE (oC) 0.10 1.00 10.00 t, PULSE WIDTH (s) FIGURE 9. GATE THRESHOLD VOLTAGE VARIANCE vs JUNCTION TEMPERATURE FIGURE 10. SINGLE PULSE POWER CAPABILITY vs PULSE WIDTH 2 1 THERMAL IMPEDANCE ZθJA, NORMALIZED DUTY CYCLE = 0.5 PDM 0.2 0.1 t1 0.1 0.05 t2 DUTY CYCLE, D = t1/t2 TJ = PD x ZθJA x RθJA + TA 0.02 SURFACE MOUNTED SINGLE PULSE 0.01 10-4 10-3 10-2 10-1 1 10 30 t, RECTANGULAR PULSE DURATION (s) FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE ©2001 Fairchild Semiconductor Corporation HP4410DY Rev. B HP4410DY Test Circuits and Waveforms VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS - VDD 10% 0 10% DUT 90% RGS VGS VGS 0 50% 10% FIGURE 12. SWITCHING TIME TEST CIRCUIT 50% PULSE WIDTH FIGURE 13. SWITCHING TIME WAVEFORM VDD VDS RL Qg Qgd VGS Qgs VGS + VDD VDS DUT 0 Ig(REF) Ig(REF) 0 FIGURE 14. GATE CHARGE TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation FIGURE 15. GATE CHARGE WsAVEFORMS HP4410DY Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4