FDG314P Digital FET, P-Channel General Description Features This P-Channel enhancement mode field effect transistor is produced using Fairchild Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize onstate resistance at low gate drive conditions. This device is designed especially for battery power applications such as notebook computers and cellular phones. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts. • Applications • Power Management • Load switch • Signal switch D -0.65 A, -25 V. RDS(ON) = 1.1 Ω @ VGS = -4.5 V RDS(ON) = 1.5 Ω @ VGS = -2.7 V. • Very low gate drive requirements allowing direct operation in 3V cirucuits (VGS(th) <1.5 V). • Gate-Source Zener for ESD ruggedness (>6 kV Human Body Model). • Compact industry standard SC70-6 surface mount package. S 1 6 2 5 3 4 D SC70-6 D D G Absolute Maximum Ratings Symbol T A = 25°C unless otherwise noted Parameter Ratings Units -25 V V A W V DSS Drain-Source Voltage V GSS ID Gate-Source Voltage Drain Current - Continuous - Pulsed (Note 1a) ±8 -0.65 -1.8 PD Power Dissipation for Single Operation (Note 1a) 0.75 (Note 1b) 0.48 T J, T stg ESD Operating and Storage Junction Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf/1500 Ohm) -55 to +150 6.0 °C kV Thermal Characteristics R θJA Thermal Resistance, Junction-to-Ambient (Note 1b) 260 °C/W Package Marking and Ordering Information Device Marking .14 2000 Fairchild Semiconductor International Device Reel Size Tape Width Quantity FDG314P 7’’ 8mm 3000 units FDG314P Rev.C FDG314P July 2000 Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA ∆BVDSS ∆TJ IDSS Breakdown Voltage Temperature Coefficient ID = -250 µA, Referenced to 25°C Zero Gate Voltage Drain Current VDS = -20 V, VGS = 0 V -1 µA IGSS Gate-Body Leakage Current VGS = -8 V, VDS = 0 V -100 nA On Characteristics VGS(th) ∆VGS(th) ∆TJ -25 V mV/°C -19 (Note 2) Gate Threshold Voltage VDS = VGS, ID = -250 µA Gate Threshold Voltage Temperature Coefficient ID = -250 µA, Referenced to 25°C -0.65 -0.72 -1.5 V mV/°C 2 Ω RDS(on) Static Drain-Source On-Resistance ID(on) On-State Drain Current VGS = -4.5 V, ID = -0.5 A VGS = -4.5 V, ID = -0.5 A @ 125°C VGS = -2.7 V, ID = -0.25 A VGS = -4.5 V, VDS = -5 V gFS Forward Transconductance VDS = -4.5 V, ID = -0.5 A 0.9 S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 63 pF 34 pF 10 pF 0.77 1.08 1.06 1.1 1.8 1.5 -1 A Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge (Note 2) VDD = -6 V, ID = -0.5 A, VGS = -4.5 V, RGEN = 50 Ω VDS = -5 V, ID = -0.25 A, VGS = -4.5 V 7 20 8 20 ns ns 55 110 ns 35 70 ns 1.1 1.5 nC 0.32 nC 0.25 nC Drain-Source Diode Characteristics and Maximum Ratings IS VSD Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward VGS = 0 V, IS = -0.42 A Voltage (Note 2) -0.85 -0.42 A -1.2 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 170°C/W when mounted on a 1 in2 pad of 2oz copper. b) 260°C/W when mounted on a minimum mounting pad. 2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0% FDG314P Rev.C FDG314P Electrical Characteristics FDG314P Typical Characteristics 2 2 -3.5V -4.0V -ID, DRAIN CURRENT (A) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = -4.5V -3.0V 1.6 -2.7V 1.2 -2.5V 0.8 -2.0V 0.4 -1.5V 1.8 1.6 VGS = -2.5V -2.7V 1.4 -3.0V -3.5V 1.2 -4.0V -4.5V 1 0.8 0 0 1 2 3 4 0 5 0.4 1.6 2 2.8 1.6 ID = -0.5A VGS = -4.5V RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.2 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. Figure 1. On-Region Characteristics. 1.4 1.2 1 0.8 0.6 -50 ID = -0.33A 2.4 2 1.6 TA = 125oC 1.2 0.8 TA = 25oC 0.4 0 -25 0 25 50 75 100 125 150 1 2 TJ, JUNCTION TEMPERATURE (oC) 3 4 5 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 10 1.2 o -IS, REVERSE DRAIN CURRENT (A) TA = -55 C VDS = -5V o 25 C -ID, DRAIN CURRENT (A) 0.8 -ID, DRAIN CURRENT (A) -VDS, DRAIN-SOURCE VOLTAGE (V) o 0.9 125 C 0.6 0.3 0 VGS = 0V 1 o TA = 125 C o 0.1 25 C -55oC 0.01 0.001 0.0001 0 1 2 3 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 4 0 0.2 0.4 0.6 0.8 1 1.2 -VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDG314P Rev.C (continued) 5 150 ID = -0.5A VDS = -5V f = 1MHz VGS = 0 V -10V 4 120 -15V CAPACITANCE (pF) -VGS, GATE-SOURCE VOLTAGE (V) FDG314P Typical Characteristics 3 90 60 CISS 1 30 COSS 0 0 2 CRSS 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 5 Qg, GATE CHARGE (nC) 10 15 20 25 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate-Charge Characteristics. Figure 8. Capacitance Characteristics. 10 30 SINGLE PULSE 1 RDS(ON) LIMIT POWER (W) 1ms 10ms 100ms 1s 10s DC 0.1 VGS = -4.5V SINGLE PULSE o RθJA = 260 C/W o TA= 25 C 18 12 6 o TA = 25 C 0 0.01 0.1 1 10 0.0001 100 0.001 -VDS, DRAIN-SOURCE VOLTAGE (V) 0.01 0.1 1 10 100 1000 SINGLE PULSE TIME (SEC) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE 1 TRANSIENT THERMAL RESISTANCE -ID, DRAIN CURRENT (A) o RθJA= 260 C/W 24 0.5 D = 0.5 R θJA (t) = r(t) * R θJA R θJA =260°C/W 0.2 0.1 0.05 0.1 P(pk) 0.05 0.01 t1 0.02 Single Pulse 0.01 0.005 0.0001 t2 TJ - TA = P * R θJA (t) Duty Cycle, D = t 1 / t 2 0.001 0.01 0.1 1 10 100 300 t1 , TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient themal response will change depending on the circuit board design. FDG314P Rev.C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST® FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ POP™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. F1