Ordering number : ENN*6695 CMOS IC LC863332/28/24/20/16A 8-Bit Single Chip Microcontroller Preliminary Overview The LC863332/28/24/20/16A are 8-bit single chip microcontrollers with the following on-chip functional blocks: - CPU : Operable at a minimum bus cycle time of 0.424µs - On-chip ROM capacity Program ROM : 32K/28K/24K/20K/16K bytes CGROM : 16K bytes - On-chip RAM capacity : 512 bytes - OSD RAM : 352 × 9 bits - Five channels × 8-bit AD Converter - Three channels × 7-bit PWM - Two 16-bit timer/counters, 14-bit base timer - 8-bit synchronous serial interface circuit - IIC-bus compliant serial interface circuit (Multi-master type) - ROM correction function - 15-source 9-vectored interrupt system - Integrated system clock generator and display clock generator X’tal oscillator (32.768kHz) for PLL reference is used for TV control. All of the above functions are fabricated on a single chip. Ver.1.01 N1798 91400 RM (IM) HS No.6695-1/20 LC863332/28/24/20/16A Features (1) Read-Only Memory (ROM) : 32768 × 8 bits / 28672 × 8 bits / 24576 × 8 bits 20480 × 8 bits / 16384 × 8 bits for program 16128 × 8 bits for CGROM (2) Random Access Memory (RAM) : 512 × 8 bits (including 128 bytes for ROM correction function) 352 × 9 bits (for CRT display) (3) OSD functions - Screen display : 36 characters × 16 lines (by software) - RAM : 352 words (9 bits per word) Display area : 36 words × 8 lines Control area : 8 words × 8 lines - Characters Up to 252 kinds of 16 × 32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts : a 16 × 17 dot and 8 × 9 dot character font - Various character attributes Character colors : 16 colors Character background colors : 16 colors Fringe / shadow colors : 16 colors Full screen colors : 16colors Rounding Underline Italic character (slanting) - Attribute can be changed without spacing - Vertical display start line number can be set for each row independently (Rows can be overlapped) - Horizontal display start position can be set for each row independently - Horizontal pitch (bit 9 - 16)*1 and vertical pitch (bit-32) can be set for each row independently - Different display modes can be set for each row independently Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplifed graphic mode - Ten character sizes *1 Horez. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5) (1.5 × 1), (1.5 × 2), (3 × 2), (3 × 4), (0.75 × 0.5) - Shuttering and scrolling on each row - Simplified Graphic Display *1 Note : range depends on display mode : refer to the manual for details. (4) Bus Cycle Time / Instruction-Cycle Time Bus cycle time 0.424µs Instruction cycle time 0.848µs Oscillation Frequency 14.156MHz 15.0µs System clock oscillation Internal VCO (Ref : X’tal 32.768kHz) Internal RC 7.5µs 183.1µs 366.2µs Crystal 32.768kHz 800kHz Voltage 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V (5) Ports - Input / Output Ports : 5 ports (28 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 4 ports (20 terminals) - Input port : 1 port (1 terminal) No.6695-2/20 LC863332/28/24/20/16A (6) AD converter - 5 channels × 8-bit AD converters (7) Serial interfaces - IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. internally. - Synchronous 8-bit serial interface The two data lines and two clock lines can be connected (8) PWM output - 3 channels × 7-bit PWM (9) Timer - Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. - Timer 1 : 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable bit PWM (9 to 16 bits) In mode0/1,the resolution of Timer1/PWM is 1 tCYC In mode2/3,the resolution is selectable by program; tCYC or 1/2 tCYC - Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 (10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) - Noise rejection function - Polarity switching (11) Watchdog timer External RC circuit is required Interrupt or system reset is activated when the timer overflows (12) ROM correction function Max 128 bytes / 2 addresses (13) Interrupts - 15 sources 9 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H,T1L 7. SIO0 8. Vertical synchronous signal interrupt ( VS ), horizontal line ( HS ), AD 9. IIC, Port 0 No.6695-3/20 LC863332/28/24/20/16A - Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 9 listed above. For the external interrupt INT0 and INT1, high or highest priority can be set. (14) Sub-routine stack level - A maximum of 128 levels (stack is built in the internal RAM) (15) Multiplication/division instruction - 16 bits × 8 bits (7 instruction cycle times) - 16 bits / 8 bits (7 instruction cycle times) (16) 3 oscillation circuits - Built-in RC oscillation circuit used for the system clock - Built-in VCO circuit used for the system clock and OSD - X’tal oscillation circuit used for base timer, system clock and PLL reference (17) Standby function - HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. - HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. • Pull the reset terminal ( RES ) to low level. • Feed the selected level to either P70/INT0 or P71/INT1. • Input the interrupt condition to Port 0. (18) Package - DIP42S - QIP48E (19) Development tools - Flash EEPROM: - Evaluation chip: - Emulator: LC86F3348A LC863096 EVA86000 (main) + ECB863200 (evaluation chip board) + POD863300 (pod: DIP42S) or POD863301 (QIP48E) No.6695-4/20 LC863332/28/24/20/16A System Block Diagram Interrupt Control IR X’tal RC VCO ROM Clock Generator Standby Control PLA PC PLL IIC ROM Correct Control ACC SIO0 XRAM B Register Timer 0 Bus Interface C Register Timer 1 Port 1 ALU Base Timer Port 6 ADC Port 7 PSW INT0-3 Noise Rejection Filter Port 8 RAR PWM RAM CGROM OSD Control Circuit Stack Pointer VRAM Port 0 Watch Dog Timer No.6695-5/20 LC863332/28/24/20/16A Pin Assignment • DIP42S P10/SO0 1 42 P07 P11/SI0 2 41 P06 P12/SCK0 3 40 P05 P13/PWM1 4 39 P04 P14/PWM2 5 38 P03 Package Dimension (unit : mm) P15/PWM3 6 37 P02 3025B P16 7 36 P01 P17/PWM 8 35 P00 VSS 9 34 P73/INT3/T0IN XT1 10 33 P72/INT2/T0IN XT2 11 32 P71/INT1 VDD 12 31 P70/INT0 P84/AN4 13 30 P63/SCLK1 P85/AN5 14 29 P62/SDA1 P86/AN6 15 28 P61/SCLK0 P87/AN7 16 27 P60/SDA0 RES 17 26 I FILT 18 25 BL P83/AN3 19 24 B VS 20 23 G HS 21 22 R SANYO : DIP-42S(600mil) NC P14/PWM2 P13/PWM1 P12/SCK0 P11/SI0 P10/SO0 NC P07 P06 P05 P04 P03 48 47 46 45 44 43 42 41 40 39 38 37 • QIP48E Package Dimension (unit : mm) NC XT1 5 32 P73/INT3/T0IN XT2 6 31 P72/INT2/T0IN VDD 7 30 P71/INT1 NC 8 29 P70/INT0 P84/AN4 9 28 P63/SCLK1 P85/AN5 10 27 P62/SDA1 P86/AN6 11 26 P61/SCLK0 P87/AN7 12 25 P60/SDA0 NC I B BL R G HS VS NC P83/AN3 RES FILT 24 P00 33 23 34 4 22 3 VSS 21 P17/PWM 20 P01 19 35 18 2 17 P16 16 P02 15 36 14 1 13 P15/PWM3 3156 SANYO : QIP-48E No.6695-6/20 LC863332/28/24/20/16A Pin Description Pin Description Table Terminal I/O VSS XT1 I XT2 O VDD I RES FILT O I VS I HS R O G O B O I O BL O Port 0 P00 - P07 I/O Port 1 P10 - P17 I/O Port 6 P60 - P63 I/O Function Description Negative power supply Input terminal for crystal oscillator Output terminal for crystal oscillator Positive power supply Reset terminal Filter terminal for PLL Vertical synchronization signal input terminal Horizontal synchronization signal input terminal Red (R) output terminal of RGB image output Green (G) output terminal of RGB image output Blue (B) output terminal of RGB image output Intensity ( I ) output terminal of RGB image output Fast blanking control signal Switch TV image signal and OSD image signal •8-bit input/output port, Input/output can be specified in nibble unit •Other functions HOLD release input Interrupt input •8-bit input/output port Input/output can be specified in a bit •Other functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 PWM1 output P14 PWM2 output P15 PWM3 output P17 Timer1 (PWM) output Option Pull-up resistor provided/not provided Output Format CMOS/Nch-OD Output Format CMOS/Nch-OD •4-bit input/output port Input/output can be specified for each bit •Other functions P60 IIC0 data I/O P61 IIC0 clock output P62 IIC1 data I/O P63 IIC1 clock output No.6695-7/20 LC863332/28/24/20/16A Terminal Port 7 P70 P71 - P73 Port 8 P83 P84-P87 NC I/O I/O I I/O - Function Description •4-bit input/output port Input or output can be specified for each bit •Other function P70 INT0 input/HOLD release input/ Nch-Tr. output for wachdog timer P71 INT1 input/HOLD release input P72 INT2 input/Timer 0 event input P73 INT3 input (noise rejection filter connected)/ Timer 0 event input Interrupt receiver format, vector addresses rising falling rising/ H level L level vector falling INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH •1-bit input port 4-bit input/output port Input or output can be specified for each bit •Other function AD converter input port (5 lines) unused terminal Leave open Option • Output form and existance of pull-up resistor for all ports can be specified for each bit. • Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. • Port status in reset Terminal Port 0 Port 1 I/O I I Pull-up resistor status at selecting pull-up option Pull-up resistor OFF, ON after reset release Programmable pull-up resistor OFF No.6695-8/20 LC863332/28/24/20/16A 1. Absolute Maximum Ratings at VSS=0V and Ta=25°C Parameter Symbol Pins Supply voltage Input voltage VDDMAX VI(1) Output voltage VO(1) Input/output voltage VIO High level output current Peak output current IOPH(1) IOPH(2) VDD • RES , HS , VS , P83 R, G, B, I, BL, FILT •Ports 0, 1, 6, 7, 84 to 87 •Ports 0, 1, 7, 84 to 87 R, G, B, I, BL Total output current ∑IOAH(1) •Ports 0, 1 ∑IOAH(2) Ports 7, 84 to 87 R, G, B, I, BL ∑IOAH(3) Low level output current Peak output current Total output current IOPL(1) IOPL(2) IOPL(3) ∑IOAL(1) ∑IOAL(2) ∑IOAL(3) Maximum power dissipation Operating temperature range Storage temperature range Pdmax Ports 0, 1, 6, 84 to 87 Port 7 R, G, B, I, BL Ports 0, 1 Ports 6, 7, 84 to 87 R, G, B, I, BL DIP42S QIP48E Conditions •CMOS output •For each pin. •CMOS output •For each pin. The total of all pins. The total of all pins. The total of all pins. For each pin. VDD[V] min. -0.3 -0.3 Ratings typ. max. +7.0 VDD+0.3 -0.3 VDD+0.3 -0.3 VDD+0.3 unit V mA -4 -5 -20 -10 -15 20 For each pin. For each pin. The total of all pins. The total of all pins. The total of all pins. Ta=-10 to +70°C 15 5 40 40 15 Topr -10 800 400 +70 Tstg -55 +125 mW °C No.6695-9/20 LC863332/28/24/20/16A 2. Recommended Operating Range at Ta= -10°C to +70°C, VSS=0V Parameter Symbol Operating supply voltage range VDD(1) Hold voltage VHD VDD High level input voltage VIH(1) Port 0 (Schumitt) VIH(2) •Ports 1,6 (Schumitt) •Port 7 (Schumitt) port input/interrupt • HS , VS , RES (Schumitt) Port 70 Watchdog timer input •Port 8 port input Port 0 (Schumitt) •Ports 1,6 (Schumitt) •Port 7 (Schumitt) port input/interrupt • HS , VS , RES (Schumitt) Port 70 Watchdog timer input Port 8 port input VIH(4) VIL(1) VIL(2) VIL(3) VIL(4) Operation cycle time tCYC(1) tCYC(2) tCYC(3) Oscillation frequency range VDD VDD(2) VIH(3) Low level input voltage Pins FmRC Conditions 0.844µs ≤ tCYC ≤ 0.852µs 4µs ≤ tCYC ≤ 400µs RAMs and the registers data are kept in HOLD mode. Output disable VDD[V] min. 4.5 Ratings typ. max. 5.5 4.5 5.5 2.0 5.5 4.5 - 5.5 0.6VDD VDD Output disable 4.5 - 5.5 0.75VDD VDD Output disable 4.5 - 5.5 VDD-0.5 VDD Output disable 4.5 - 5.5 0.7VDD VDD Output disable Output disable 4.5 - 5.5 4.5 - 5.5 VSS VSS 0.2VDD 0.25VDD Output disable 4.5 - 5.5 VSS 0.6VDD Output disable 4.5 - 5.5 VSS 0.3VDD •All functions operating •AD converter operating •OSD is not operating •OSD and AD converter are not operating Internal RC oscillation 4.5 - 5.5 0.844 4.5 - 5.5 0.844 30 4.5 - 5.5 0.844 400 4.5 - 5.5 0.4 0.848 0.8 0.852 3.0 unit V µs MHz No.6695-10/20 LC863332/28/24/20/16A 3. Electrical Characteristics at Ta=-10°C to +70°C, VSS=0V Parameter High level input current Low level input current Symbol IIH(1) Ports 0, 1, 6, 7, 8 IIH(2) • RES • HS , VS Ports 0, 1, 6, 7, 8 IIL(1) IIL(2) High level output voltage Low level output voltage VOH(1) VOH(2) VOL(1) VOL(2) VOL(3) Pull-up MOS Tr. resistance Bus terminal short circuit resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis voltage Pin capacitance Pins VOL(4) VOL(5) Rpu • RES • HS , VS •CMOS output of ports 0, 1, 71 - 73, 84 - 87 R, G, B, I, BL Ports 0, 1, 71 - 73, 84 - 87 Ports 0, 1, 71 - 73, 84 - 87 •R, G, B, I, BL •Port 6 Port 6 Port 70 •Ports 0, 1, 7, 8 RBS •P60-P62 •P61-P63 VHIS •Ports 0, 1, 6, 7 • RES • HS , VS All pins CP Conditions •Output disable •Pull-up MOS Tr. OFF •VIN=VDD (including the offleak current of the output Tr.) •VIN=VDD VDD[V] 4.5 - 5.5 min. Ratings typ. 4.5 - 5.5 max. 1 unit µA 1 •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including the offleak current of the output Tr.) VIN=VSS 4.5 - 5.5 -1 4.5 - 5.5 -1 IOH=-1.0mA 4.5 - 5.5 VDD-1 IOH=-0.1mA IOL=10mA 4.5 - 5.5 4.5 - 5.5 VDD-0.5 IOL=1.6mA 4.5 - 5.5 0.4 IOL=3.0mA 4.5 - 5.5 0.4 IOL=6.0mA IOL=1mA VOH=0.9VDD 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 0.6 0.4 80 kΩ 130 Ω V 1.5 13 38 4.5 - 5.5 Output disable 4.5 - 5.5 0.1VDD V •f=1MHz •Every other terminals are connected to VSS. •Ta=25°C 4.5 - 5.5 10 pF No.6695-11/20 LC863332/28/24/20/16A Serial output Serial input Symbol Pins Cycle tCKCY(1) •SCK0 •SCLK0 Low Level pulse width High Level pulse width Cycle tCKL(1) 1 tCKH(1) 1 Low Level pulse width High Level pulse width Data set up time tCKL(2) tICK Data hold time tCKI Input clock Parameter Output clock Serial clock 4. Serial Input/Output Characteristics at Ta= -10°C to +70°C, VSS=0V tCKCY(2) •SCK0 •SCLK0 tCKH(2) Output delay time tCKO(1) (Using external clock) Output delay time tCKO(2) (Using internal clock) SI0 SO0 SO0 Conditions Refer to figure 4. VDD[V] 4.5 - 5.5 min. 2 Ratings typ. max. unit tCYC •Use pull-up resistor (1kΩ) when Nch opendrain output. •Refer to figure 4. 4.5 - 5.5 •Data set-up to SCK0. •Data hold from SCK0. •Refer to figure 4. 4.5 - 5.5 •Data hold from SCK0. •Use pull-up resistor (1kΩ) when Nch opendrain output. •Refer to figure 4. 4.5 - 5.5 7/12tCYC +0.2 4.5 - 5.5 1/3tCYC +0.2 2 1/2tCKCY 1/2tCKCY µs 0.1 0.1 5. IIC Input/Output Conditions at Ta=-10°C to +70°C, VSS=0V Parameter SCL Frequency BUS free time between stop - start HOLD time of start, restart condition L time of SCL H time of SCL Set-up time of restart condition HOLD time of SDA Set-up time of SDA Rising time of SDA, SCL Falling time of SDA, SCL Set-up time of stop condition (Note) Symbol fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Refer to figure 9 Cb : Total capacitance of all BUS (unit : pF) Standard min. max. 0 100 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 4.0 - High speed min. max. 0 400 1.3 0.6 1.3 0.6 0.6 0 0.9 100 20+0.1Cb 300 20+0.1Cb 300 0.6 - unit kHz µs µs µs µs µs µs ns ns ns µs No.6695-12/20 LC863332/28/24/20/16A 6. Pulse Input Conditions at Ta=-10°C to +70°C, VSS=0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) Conditions VDD[V] 4.5 - 5.5 min. 1 4.5 - 5.5 2 •Interrupt acceptable •Timer0-countable 4.5 - 5.5 32 •INT0, INT1 •INT2/T0IN INT3/T0IN (1/1 is selected for noise rejection clock.) INT3/T0IN (1/16 is selected for noise rejection clock.) INT3/T0IN (1/64 is selected for noise rejection clock.) •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable 4.5 - 5.5 128 tPIL(5) tPIH(6) tPIL(6) RES 4.5 - 5.5 4.5 - 5.5 200 8 tTHL tTLH HS Reset acceptable •Display position controllable (Note) •The active edge of HS and VS must be apart at least 1 tCYC. •Refer to figure 6. Refer to figure 6. tPIH(3) tPIL(3) tPIH(4) tPIL(4) Rising/falling time Pins HS , VS Ratings typ. max. unit tCYC µs 4.5 - 5.5 500 ns 7. AD Converter Characteristics at Ta=-10°C to + 70°C, VSS=0V Parameter Resolution Absolute precision Conversion time Analog input voltage range Analog port input current Symbol Pins N ET IAINH IAINL VDD[V] 4.5 – 5.5 min. Ratings typ. 8 (Note 3) tCAD VAIN Conditions ±1.5 ADCR2=0 (Note 4) ADCR2=1 (Note 4) AN3 - AN7 16 32 VSS VAIN=VDD VAIN=VSS max. unit bit LSB tCYC VDD V 1 µA -1 (Note 3) Absolute precision does not include quantizing error (1/2LSB). (Note 4) Conversion time is the time till the complete digital conversion value for analog input value is set to a register after the instruction to start conversion is sent. No.6695-13/20 LC863332/28/24/20/16A 8. Sample Current Dissipation Characteristics at Ta=-10°C to +70°C, VSS=0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation during basic operation (Note 3) Symbol IDDOP(1) Pins VDD Current dissipation IDDHALT(1) in HALT mode (Note 3) VDD IDDHALT(2) VDD IDDHALT(3) VDD IDDHOLD VDD Current dissipation in HOLD mode (Note 3) Conditions •FmX’tal=32.768kHz X’tal oscillation •System clock : VCO •VCO for OSD operating •Internal RC oscillation stops •HALT mode •FmX’tal=32.768kHz X’tal oscillation •System clock : VCO •VCO for OSD stops •Internal RC oscillation stops •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock : Internal RC •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock : X’tal •HOLD mode •All oscillation stops. Ratings typ. 17 max. 30 4.5 - 5.5 7 12 mA 4.5 - 5.5 300 1200 µA 4.5 - 5.5 50 200 4.5 - 5.5 0.05 20 VDD[V] 4.5 - 5.5 min. unit mA µA (Note 3) The currents through the output transistors and the pull-up MOS transistors are ignored. No.6695-14/20 LC863332/28/24/20/16A Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: • Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. • Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C) Frequency Manufacturer Oscillator 32.768kHz Seiko Epson C-002RX Notes Recommended circuit parameters C1 18pF C2 18pF Rf Open Rd 390kΩ Operating supply voltage range 4.5 – 5.5V Oscillation stabilizing time typ. max 1.00s 1.50s Notes The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. manufacturer with the following notes in your mind. For further assistance, please contact with oscillator • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 XT2 Rf Rd C1 C2 X’tal Figure 1 Recommended oscillation circuit. No.6695-15/20 LC863332/28/24/20/16A VDD VDD limit 0V Power supply Reset time RES Internal RC resonato oscillation XT1,XT2 tmsVCO VCO for system Operation mode stable Unfixed Reset Instruction execution mode <Reset time and oscillation stabilizing time> HOLD release signal Valid Internal RC resonato oscillation XT1,XT2 tmsVCO stable VCO for system Operation mode HOLD Instruction execution mode <HOLD release signal and oscillation stabilizing time> Figure 2 Oscillation stabilizing time No.6695-16/20 LC863332/28/24/20/16A VDD RRES (Note) RES CRES Figure 3 Determine the CRES, RRES value to generate more than 200µs reset time. Reset circuit 0.5VDD < AC timing measurement point > tCKCY VDD tCKH tCKL SCK0 1KΩ tICK tCKI SI0 tCKO 50pF SO0 SB0 < Timing > Figure 4 < Test load > Serial input / output test condition No.6695-17/20 LC863332/28/24/20/16A tPIL (1)-(5) Figure 5 tPIH (1)-(4) Pulse input timing condition – 1 tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) more than ±1tCYC Figure 6 Pulse input timing condition - 2 LC863332A 10kΩ HS HS C536 Figure 7 Recommended Interface circuit No.6695-18/20 LC863332/28/24/20/16A 100Ω FILT + 2.2µF - 1MΩ Figure 8 (Note) P 33000pF FILT recommended circuit Place FILT parts on board as close to the microcontroller as possible. S Sr P SDA tBUF tHD;STA tR tF tHD;STA tsp SCL tLOW tHIGH tHD;DAT S : start condition P : stop condition Sr : restart condition tSU;DAT tsp : Spike suppression Figure 9 tSU;STA tSU;STO Standard mode : not exist High speed mode : less than 50ns IIC timing No.6695-19/20 LC863332/28/24/20/16A memo: PS No.6695-20/20