Ordering number : ENA0115A LC863264C,LC863256C LC863248C,LC863240C LC863232C,LC863228C LC863224C,LC863220C LC863216C CMOS IC 64K/56K/48K/40K/32K/28K/24K/20K/16K-byte ROM, CGROM16K-byte on-chip 640/512-byte RAM and 352x9 bit OSD RAM 8-bit 1-chip Microcontroller Overview The LC863264C/56C/48C/40C/32C/28C/24C/20C/16C are 8-bit single chip microcontrollers with the following on-chip functional blocks: • CPU : Operable at a minimum bus cycle time of 0.424µs • On-chip ROM capacity Program ROM : 64K/56K/48K/40K/32K/28K/24K/20K/16K bytes CGROM : 16K bytes • On-chip RAM capacity : 640/512 bytes • OSD RAM : 352×9 bits • Closed-Caption TV controller and the on-screen display controller • Closed-Caption data slicer • Four channels×8-bit AD Converter • Three channels×7-bit PWM • Two 16-bit timer/counters, 14-bit base timer • 8-bit synchronous serial interface circuit • IIC-bus compliant serial interface circuit (Multi-master type) • ROM correction function • 16-source 10-vectored interrupt system Continued on next page. Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation. Ver.1.00 71006HKIM No.A0115-1/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Continued from preceding page. • Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators TV control and the Closed Caption function All of the above functions are fabricated on a single chip. Features Read-Only Memory (ROM) : 65536×8 bits / 57344×8 bits / 49152×8 bits / 40960×8 bits / 32768×8 bits / 28672×8 bits / 24576×8 bits / 20480×8 bits / 16384×8 bits for program 16128×8 bits for CGROM Random Access Memory (RAM) : 512×8 bits (working area) : LC863264C/56C/48C/40C 384×8 bits (working area) : LC863232C/28C/24C/20C/16C 128×8 bits (working or ROM correction function) 352×9 bits (for CRT display) OSD functions • Screen display : 36 characters×16 lines (by software) • RAM : 352 words (9 bits per word) Display area : 36 words×8 lines Control area : 8 words×8 lines • Characters Up to 252 kinds of 16×32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts : a 16×17 dot and 8×9 dot character font At least 111 characters need to be divide to display the caption fonts. • Various character attributes Character colors : 16colors Character background colors : 16colors Fringe / shadow colors : 16colors Full screen colors : 16colors Rounding Underline Italic character (slanting) • Attribute can be changed without spacing • Vertical display start line number can be set for each row independently (Rows can be overlapped) • Horizontal display start position can be set for each row independently • Horizontal pitch (9 to 16 dots)*1 and vertical pitch (1 to 32 dots) can be set for each row independently • Different display modes can be set for each row independently Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode • Ten character sizes *1 Horez. × Vert. = (1×1), (1×2), (2×2), (2×4), (0.5×0.5) (1.5×1), (1.5×2), (3×2), (3×4), (0.75×0.5) • Shuttering and scrolling on each row • Simplified Graphic Display Note *1: range depends on display mode : refer to the manual for details. Data Slicer (NTSC) • Line 21 closed caption data and XDS data extraction No.A0115-2/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Bus Cycle Time / Instruction-Cycle Time Bus cycle time Instruction cycle time System clock oscillation Oscillation frequency Voltage 0.424µs 0.848µs Internal VCO 14.156MHz 4.5V to 5.5V 7.5µs 15.0µs Internal RC 800kHz 4.5V to 5.5V 183.1µs 366.2µs Crystal 32.768kHz 4.5V to 5.5V (Ref : X’tal 32.768kHz) Ports • Input / Output Ports : 5 ports (28 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 4 ports (20 terminals) AD converter • 4 channels×8-bit AD converters Serial interfaces • IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. • Synchronous 8-bit serial interface PWM output • 3 channels×7-bit PWM Timer • Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. • Timer 1 : 16-bit timer/PWM Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable bit PWM (9 to 16 bits) In mode0/1, the resolution of Timer1/PWM is 1 tCYC In mode2/3, the resolution is selectable by program; tCYC or 1/2 tCYC • Base timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching Watchdog timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM correction function Max 128 bytes / 2 addresses No.A0115-3/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Interrupts • 16 sources 10 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H,T1L 7. SIO0 8. Data slicer 9. Vertical synchronous signal interrupt (VS), horizontal line (HS), AD 10. IIC, Port 0 • Interrupt priority control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. Sub-routine stack level • A maximum of 128 levels (stack is built in the internal RAM) Multiplication/division instruction • 16 bits×8 bits (7 instruction cycle times) • 16 bits÷8 bits (7 instruction cycle times) 3 oscillation circuits • Built-in RC oscillation circuit used for the system clock • Built-in VCO circuit used for the system clock and OSD • X’tal oscillation circuit used for base timer, system clock and PLL reference Standby function • HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. • HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. - Pull the reset terminal (RES) to low level. - Feed the selected level to either P70/INT0 or P71/INT1. - Input the interrupt condition to Port 0. Package • DIP42S (Lead-free type) • QIP48E (Lead-free type) Development tools • Flash EEPROM: • Evaluation chip: • Emulator: LC86F3264A LC863096 EVA86000 (main) + ECB863200* or ECB863200A (evaluation chip board) + POD863200 (pod: DIP42S) or POD863201 (pod: QIP48E) * This product is no longer available No.A0115-4/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Package Dimensions unit : mm (typ) 3025C 22 1 21 0.25 13.8 42 15.24 37.7 (4.25) 0.51min 3.8 5.1max 0.95 0.48 1.78 SANYO : DIP42S(600mil) (1.05) Package Dimensions unit : mm (typ) 3156A 17.2 0.8 14.0 24 48 13 14.0 37 1 17.2 25 36 12 1.0 0.35 0.15 0.1 3.0max (2.7) (1.5) SANYO : QIP48E(14X14) No.A0115-5/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Pin Assignments P10/SO0 1 42 P07 P11/SI0 2 41 P06 P12/SCK0 3 40 P05 P13/PWM1 4 39 P04 P14/PWM2 5 38 P03 P15/PWM3 6 37 P02 P16 7 36 P01 P17/PWM 8 35 P00 VSS 9 34 P73/INT3/T0IN XT1 10 33 P72/INT2/T0IN XT2 11 32 P71/INT1 VDD 12 31 P70/INT0 P84/AN4 13 30 P63/SCLK1 P85/AN5 14 29 P62/SDA1 P86/AN6 15 28 P61/SCLK0 P87/AN7 16 27 P60/SDA0 RES 17 26 I 5 20 23 G HS 21 22 R NC P14/PWM2 P13/PWM1 P12/SCK0 P11/SI0 P10/SO0 NC P07 P06 P05 P04 P03 48 47 46 45 44 43 42 41 40 39 38 37 Top view P63/SCLK1 27 P62/SDA1 QIP48E 26 P61/SCLK0 25 P60/SDA0 20 28 G P70/INT0 19 29 R P71/INT1 HS 12 P72/INT2/T0IN 30 18 P87/AN7 31 17 11 P73/INT3/T0IN VS 10 P86/AN6 32 16 P85/AN5 NC NC 9 33 15 P84/AN4 P00 CVIN 8 P01 34 14 NC 35 13 7 LC863264C/ LC863256C/ LC863248C/ LC863240C/ LC863232C/ LC863228C/ LC863224C/ LC863220C/ LC863216C FILT 6 P02 RES XT2 VDD 36 24 XT1 VS NC 4 B 23 VSS BL 24 I 3 25 19 22 2 18 21 P16 P17/PWM FILT CVIN B 1 DIP42S BL P15/PWM3 LC863264C/ LC863256C/ LC863248C/ LC863240C/ LC863232C/ LC863228C/ LC863224C/ LC863220C/ LC863216C Top view No.A0115-6/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C System Block Diagram Interrupt Control IR X’tal RC VCO ROM Clock Generator Standby Control PLA PC PLL IIC ROM Correct Control ACC SIO0 XRAM B Register Timer 0 Bus Interface C Register Timer 1 Port 1 ALU Base Timer Port 6 ADC Port 7 PSW INT0-3 Noise Rejection Filter Port 8 RAR PWM Data Slicer RAM OSD Control Circuit CGROM VRAM Stack Pointer Port 0 Watch Dog Timer No.A0115-7/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Pin Description Pin Description Table Terminal Function Description I/O VSS - Negative power supply XT1 I Input terminal for crystal oscillator XT2 O Output terminal for crystal oscillator VDD - Positive power supply RES I Reset terminal FILT O Filter terminal for PLL CVIN I Video signal input terminal VS I Vertical synchronization signal input terminal HS I Horizontal synchronization signal input terminal R O Red (R) output terminal of RGB image output G O Green (G) output terminal of RGB image output B O Blue (B) output terminal of RGB image output I O Intensity ( I ) output terminal of RGB image output BL O Fast blanking control signal Switch TV image signal and caption/OSD image signal •8-bit input/output port, Port 0 Input/output can be specified in nibble unit P00 to P07 I/O Option •Other functions Pull-up resistor provided/not provided Output Format HOLD release input CMOS/Nch-OD Interrupt input Port 1 •8-bit input/output port Input/output can be specified in a bit P10 to P17 Output Format CMOS/Nch-OD •Other functions I/O Port 6 P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 PWM1 output P14 PWM2 output P15 PWM3 output P17 Timer1 (PWM) output •4-bit input/output port Input/output can be specified for each bit P60 to P63 •Other functions I/O P60 IIC0 data I/O P61 IIC0 clock output P62 IIC1 data I/O P63 IIC1 clock output Continued on next page. No.A0115-8/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Continued from preceding page. Terminal I/O I/O Port 7 Function Description Option •4-bit input/output port Input or output can be specified for each bit P70 •Other functions P71 to P73 P70 INT0 input/HOLD release input/ Nch-Tr. output for watchdog timer P71 INT1 input/HOLD release input P72 INT2 input/Timer 0 event input P73 INT3 input (noise rejection filter connected)/ Timer 0 event input Interrupt receiver format, vector addresses Rising I/O Port 8 Falling Rising/ Falling H level L level Vector INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH •4-bit input/output port Input or output can be specified for each bit P84 to P87 •Other function AD converter input port (4 lines) NC - Unused terminal Leave open • Output form and existence of pull-up resistor for all ports can be specified for each bit. • Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. Port status in reset Terminal I/O Pull-up resistor status at selecting pull-up option Port 0 I Pull-up resistor OFF, ON after reset release Port 1 I Programmable pull-up resistor OFF No.A0115-9/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Absolute Maximum Ratings / Ta = 25°C, VSS = 0V Parameter Maximum supply Symbol VDD max Pins Conditions VDD voltage Ratings VDD[V] min typ unit max -0.3 +6.5 Input voltage VI(1) RES , HS , VS , CVIN -0.3 VDD+0.3 Output voltage VO(1) R, G, B, I, BL, FILT -0.3 VDD+0.3 Input/output voltage VIO Ports 0, 1, 6, 7, 8 -0.3 VDD+0.3 High Peak IOPH(1) Ports 0, 1, 7, 8 level output output current •CMOS output •For each pin. IOPH(2) R, G, B, I, BL current •CMOS output •For each pin. -4 -5 Total ΣIOAH(1) Ports 0, 1 Total of all pins. output ΣIOAH(2) Ports 7, 8 Total of all pins. -10 ΣIOAH(3) R, G, B, I, BL Total of all pins. -15 current -20 mA Low Peak IOPL(1) Ports 0, 1, 6, 8 For each pin. 20 level output IOPL(2) Port 7 For each pin. 15 output current IOPL(3) R, G, B, I, BL For each pin. ΣIOAL(1) Ports 0, 1 Total of all pins. 40 40 current Total output current Maximum power Operating 5 ΣIOAL(2) Ports 6, 7, 8 Total of all pins. ΣIOAL(3) R, G, B, I, BL Total of all pins. 15 Pd max DIP42S Ta=-10 to +70ºC 715 dissipation QIP48E 385 -10 +70 range temperature mW Topr temperature Storage V ºC Tstg -55 +125 range No.A0115-10/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Recommended Operating Range / Ta = -10°C to +70°C, VSS = 0V Parameter Operating Symbol VDD(1) Pins VDD supply voltage range Conditions Ratings VDD[V] 0.844µs ≤ tCYC VHD 4.5 5.5 2.0 5.5 4.5 to 5.5 0.6VDD VDD 4.5 to 5.5 0.75VDD VDD 4.5 to 5.5 VDD-0.5 VDD 4.5 to 5.5 0.7VDD VDD 4.5 to 5.5 VSS 0.2VDD 4.5 to 5.5 VSS 0.25VDD 4.5 to 5.5 VSS 0.6VDD 4.5 to 5.5 VSS 0.3VDD 4µs ≤ tCYC ≤ VDD unit max 5.5 400µs Hold voltage typ 4.5 ≤ 0.852µs VDD(2) min RAMs and the registers data are kept in HOLD mode. High level input VIH(1) Port 0 (Schumitt) Output disable voltage VIH(2) •Ports 1,6 (Schumitt) Output disable •Port 7 (Schumitt) port input/interrupt • HS , VS RES , (Schumitt) VIH(3) Port 70 Output disable Watchdog timer input VIH(4) •Port 8 Output disable port input Low level input VIL(1) Port 0 (Schumitt) Output disable voltage VIL(2) •Ports 1,6 (Schumitt) Output disable •Port 7 (Schumitt) port input/interrupt V • HS , VS RES , (Schumitt) VIL(3) Port 70 Output disable Watchdog timer input VIL(4) Port 8 Output disable port input CVIN Operation VCVIN CVIN tCYC(1) cycle time 5.0 •All functions operating tCYC(2) 1Vp-p -3dB 1Vp-p 0.848 1Vp-p +3dB 4.5 to 5.5 0.844 4.5 to 5.5 0.844 30 4.5 to 5.5 0.844 400 4.5 to 5.5 0.4 Vp-p* 0.852 •AD converter operating •OSD and Data slicer are not µs operating tCYC(3) •OSD, AD converter and Data slicer are not operating Oscillation FmRC frequency Internal RC oscillation 0.8 3.0 MHz range * Vp-p : Peak-to-peak voltage No.A0115-11/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Electrical Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter High level input Symbol IIH(1) Pins Ports 0, 1, 6, 7, 8 current Conditions Ratings VDD[V] min typ max unit •Output disable •Pull-up MOS Tr. OFF •VIN=VDD (including the off- 4.5 to 5.5 1 4.5 to 5.5 1 leak current of the output Tr.) IIH(2) • RES •VIN=VDD • HS , VS Low level input IIL(1) Ports 0, 1, 6, 7, 8 current µA •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including the off- 4.5 to 5.5 -1 4.5 to 5.5 -1 4.5 to 5.5 VDD-1 VDD-0.5 leak current of the output Tr.) IIL(2) • RES VIN=VSS • HS , VS High level VOH(1) output voltage •CMOS output of IOH=-1.0mA ports 0, 1, 71 to 73 VOH(2) R, G, B, I, BL IOH=-0.1mA 4.5 to 5.5 Low level output VOL(1) Ports 0, 1, 71 to 73 IOL=10mA 4.5 to 5.5 1.5 voltage VOL(2) Ports 0, 1, 71 to 73 IOL=1.6mA 4.5 to 5.5 0.4 VOL(3) •R, G, B, I, BL IOL=3.0mA 4.5 to 5.5 0.4 •Port 6 Pull-up MOS VOL(4) Port 6 IOL=6.0mA 4.5 to 5.5 0.6 VOL(5) Port 70 IOL=1mA 4.5 to 5.5 0.4 Rpu Ports 0, 1, 7, 8 VOH=0.9VDD Tr. resistance Bus terminal RBS short circuit 4.5 to 5.5 13 V 38 80 kΩ 4.5 to 5.5 130 300 Ω 4.5 to 5.5 0.1VDD •P60 to P62 •P61 to P63 resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis VHYS voltage •Ports 0, 1, 6, 7 Output disable • RES • HS , VS Input clump VCLMP CVIN CP All pins V 5.0 voltage Pin capacitance 2.3 2.5 2.7 •f=1MHz •Every other terminals are connected to VSS. 4.5 to 5.5 10 pF •Ta=25ºC No.A0115-12/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Serial Input/Output Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Input clock tCKCY(1) Conditions •SCK0 Ratings VDD[V] min Refer to figure 4. Low Level tCKL(1) 4.5 to 5.5 pulse width High Level tCKCY(2) Low Level tCKL(2) 1 •SCK0 •Use pull-up •SCLK0 resistor (1kΩ) when Nch opendrain output. pulse width High Level tCYC 2 4.5 to 5.5 1/2tCKCY •Refer to figure 4. tCKH(2) 1/2tCKCY pulse width Serial input Data set up time tICK •Data set-up to 0.1 SCK0. SCK0. tCKI 4.5 to 5.5 •Refer to figure 4. Output delay time Serial output SI0 •Data hold from Data hold time tCKO(1) SCK0. •Use pull-up tCKO(2) 0.1 µs •Data hold from SO0 (Using external clock) Output delay time unit max 1 tCKH(1) Cycle typ 2 •SCLK0 pulse width Output clock Serial clock Cycle Pins 4.5 to 5.5 7/12tCYC +0.2 4.5 to 5.5 1/3tCYC +0.2 resistor (1kΩ) SO0 when Nch open- (Using internal clock) drain output. •Refer to figure 4. IIC Input/Output Conditions / Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Standard min High speed max min unit max SCL Frequency fSCL 0 100 0 400 BUS free time between stop - start tBUF 4.7 - 1.3 - µs HOLD time of start, restart condition tHD;STA 4.0 - 0.6 - µs L time of SCL tLOW 4.7 - 1.3 - µs H time of SCL tHIGH 4.0 - 0.6 - µs Set-up time of restart condition tSU;STA 4.7 - 0.6 - µs HOLD time of SDA tHD;DAT 0 - 0 0.9 µs Set-up time of SDA tSU;DAT 250 - 100 - ns Rising time of SDA, SCL tR - 1000 20+0.1Cb 300 ns Falling time of SDA, SCL tF - 300 20+0.1Cb 300 ns Set-up time of stop condition tSU;STO 4.0 - 0.6 - µs kHz Refer to figure 10 Note 1: Cb : Total capacitance of all BUS (unit : pF) No.A0115-13/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Pulse Input Conditions / Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Pins Conditions High/low level tPIH(1) •INT0, INT1 •Interrupt acceptable pulse width tPIL(1) •INT2/T0IN •Timer0-countable tPIH(2) INT3/T0IN •Interrupt acceptable tPIL(2) (1tCYC is selected for noise •Timer0-countable Ratings VDD[V] min 4.5 to 5.5 1 4.5 to 5.5 2 4.5 to 5.5 32 typ max unit rejection clock.) tPIH(3) INT3/T0IN •Interrupt acceptable tPIL(3) (16tCYC is selected for •Timer0-countable tCYC noise rejection clock.) tPIH(4) INT3/T0IN •Interrupt acceptable tPIL(4) (64tCYC is selected for •Timer0-countable 4.5 to 5.5 128 4.5 to 5.5 200 4.5 to 5.5 8 noise rejection clock.) tPIL(5) RES Reset acceptable tPIH(6) HS , VS •Display position tPIL(6) controllable •The active edge of HS and VS must be apart µs at least 1tCYC. •Refer to figure 6. Rising/falling tTHL time tTLH Refer to figure 6. HS 4.5 to 5.5 500 ns AD Converter Characteristics / Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Resolution N Absolute ET Pins Conditions Ratings VDD[V] min typ 8 (Note 2) tCAD ADCR2=0 (Note 3) ADCR2=1 (Note 3) Analog input VAIN AN4 to AN7 16 4.5 to 5.5 Analog port IAINH VAIN=VDD input current IAINL VAIN=VSS LSB tCYC 32 VSS voltage range unit bit ±1.5 precision Conversion time max VDD 1 -1 V µA Note 2: Absolute precision does not include quantizing error (1/2LSB). Note 3: Conversion time is the time till the complete digital conversion value for analog input value is set to a register after the instruction to start conversion is sent. No.A0115-14/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Sample Current Dissipation Characteristics / Ta= -10°C to +70°C, VSS=0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation Symbol IDDOP(1) Pins VDD Conditions Ratings VDD[V] min typ max unit •FmX’tal=32.768kHz during basic X’tal oscillation operation •System clock : VCO (Note 4) •VCO for OSD operating 4.5 to 5.5 10 24 mA 4.5 to 5.5 3 9 mA 4.5 to 5.5 300 1000 •Internal RC oscillation stops Current dissipation IDDHALT(1) VDD in HALT mode •HALT mode •FmX’tal=32.768kHz (Note 4) X’tal oscillation •System clock : VCO •VCO for OSD stops •Internal RC oscillation stops IDDHALT(2) VDD •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock : Internal RC IDDHALT(3) VDD µA •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops 4.5 to 5.5 45 200 4.5 to 5.5 0.05 20 •VCO for OSD stops •System clock : X’tal Current dissipation in HOLD mode IDDHOLD VDD •HOLD mode •All oscillation stops. µA (Note 4) Note 4: The currents through the output transistors and the pull-up MOS transistors are ignored. No.A0115-15/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C) Frequency Manufacturer Oscillator 32.768kHz SEIKO EPSON C-002RX Recommended circuit parameters Operating Oscillation supply stabilizing time C1 C2 Rf Rd voltage range typ max 18pF 18pF OPEN 390kΩ 4.5 to 5.5V 1.0s 1.5s Notes Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 XT2 Rf Rd C1 C2 X’tal Figure 1 Recommended Oscillation Circuit No.A0115-16/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C VDD VDD limit 0V Power supply Reset time RES Internal RC resonator oscillation XT1,XT2 tmsVCO VCO for system Operation mode stable Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD release signal Valid Internal RC resonator oscillation XT1, XT2 tmsVCO VCO for system Operation mode stable HOLD Instruction execution mode HOLD Release Signal and Oscillation Stabilizing Time Figure 2 Oscillation Stabilizing Time No.A0115-17/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C VDD Note: Determine the CRES, RRES value to generate more than 200µs reset time. RRES RES CRES Figure 3 Reset Circuit 0.5VDD AC Timing Measurement Point VDD tCKCY tCKL tCKH SCK0 1kΩ tICK tCKI SI0 tCKO 50pF SO0 SB0 Timing Test load Figure 4 Serial Input / Output Test Condition No.A0115-18/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C tPIL (1)-(5) tPIH (1)-(4) Figure 5 Pulse Input Timing Condition - 1 tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) more than ±1tCYC Figure 6 Pulse Input Timing Condition - 2 LC863264C 10kΩ HS HS C536 Figure 7 Recommended Interface Circuit No.A0115-19/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C Noise filter 1µF C-Video 1000pF CVIN 200Ω Coupling capacitor Output impedance of C-Video before Noise filter should be less then 100Ω. Figure 8 CVIN Recommended Circuit 100Ω + - 2.2µF 1MΩ 33000pF FILT Figure 9 FILT Recommended Circuit (Note) Place FILT parts on board as close to the microcontroller as possible. P S P Sr SDA tBUF tHD;STA tR tF tHD;STA tsp SCL tLOW tHIGH tHD;DAT S : start condition P : stop condition Sr : restart condition tSU;DAT tsp : spike suppression tSU;STA tSU;STO Standard mode : not exist High speed mode : less than 50ns Figure 10 IIC Timing No.A0115-20/21 LC863264C/56C/48C/40C/32C/28C/24C/20C/16C This catalog provides information as of July, 2006. Specifications and information herein are subject to change without notice. PS No.A0115-21/21