Ordering number : ENA0117B LC863448C,LC863440C LC863432C,LC863428C LC863424C,LC863420C LC863416C CMOS IC 48K/40K/32K/28K/24K/20K/16K-byte ROM, CGROM16K-byte on-chip 640/512-byte RAM and 352x9 bit OSD RAM 8-bit 1-chip Microcontroller Overview The LC863448C/40C/32C/28C/24C/20C/16C are 8-bit single chip microcontrollers with the following on-chip functional blocks: • CPU: Operable at a minimum bus cycle time of 0.424μs • On-chip ROM capacity Program ROM: 48K/40K/32K/28K/24K/20K/16K bytes CGROM: 16K bytes • On-chip RAM capacity: 640/512 bytes • OSD RAM: 352×9 bits • Closed-Caption TV controller and the on-screen display controller • Closed-Caption data slicer • Four channels×6-bit AD Converter • Three channels×7-bit PWM • 16-bit timer/counter, 14-bit base timer Continued on next page. Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 O0108HKIM 20080916-S00001 No.A0117-1/18 LC863448C/40C/32C/28C/24C/20C/16C Continued from preceding page. • IIC-bus compliant serial interface circuit (Multi-master type) • ROM correction function • 12-source 8-vectored interrupt system • Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators TV control and the Closed Caption function All of the above functions are fabricated on a single chip. Features Read-Only Memory (ROM): 49152×8 bits / 40960×8 bits / 32768×8 bits / 28672×8 bits / 24576×8 bits / 20480×8 bits / 16384×8 bits for program 16128×8 bits for CGROM Random Access Memory (RAM): 512×8 bits (working area) : LC863448C/40C 384×8 bits (working area) : LC863432C/28C/24C/20C/16C 128×8 bits (working or ROM correction function) 352×9 bits (for CRT display) OSD Functions • Screen display : 36 characters×16 lines (by software) • RAM : 352 words (9 bits per word) Display area : 36 words×8 lines Control area : 8 words×8 lines • Characters Up to 252 kinds of 16×32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts (Ex. 16×16 dot character font×2) At least 111 characters need to be divide between a 16×17 dot and 8×9 dot character font to display the caption fonts. • Various character attributes Character colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Character background colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Fringe / shadow colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Full screen colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Rounding Underline Italic character (slanting) • Attribute can be changed without spacing • Vertical display start line number can be set for each row independently (Rows can be overlapped) • Horizontal display start position can be set for each row independently • Horizontal pitch (9 to 16 dots)*1 and vertical pitch (1 to 32 dots) can be set for each row independently • Different display modes can be set for each row independently Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode • Ten character sizes *1 Horez. × Vert. = (1×1), (1×2), (2×2), (2×4), (0.5×0.5) (1.5×1), (1.5×2), (3×2), (3×4), (0.75×0.5) • Shuttering and scrolling on each row • Simplified Graphic Display Note *1: range depends on display mode : refer to the manual for details. Data Slicer (closed caption format) • Closed caption data and XDS data extraction • NTSC/PAL, and extracted line can be specified No.A0117-2/18 LC863448C/40C/32C/28C/24C/20C/16C Bus Cycle Time / Instruction-Cycle Time Bus Cycle Time Instruction Cycle Time Clock Divider 0.424μs 0.848μs 1/2 System Clock Oscillation Internal VCO (Ref: X'tal 32.768kHz) Oscillation Frequency 14.156MHz Voltage 4.5V to 5.5V 7.5μs 15.0μs 1/2 Internal RC 800kHz 4.5V to 5.5V 91.55μs 183.1μs 1/1 Crystal 32.768kHz 4.5V to 5.5V 183.1μs 366.2μs 1/2 Crystal 32.768kHz 4.5V to 5.5V Ports • Input / Output Ports : 4 ports (23 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 3 ports (15 terminals) AD Converter • 4 channels×6-bit AD converters Serial Interfaces • IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. PWM Output • 3 channels×7-bit PWM Timer • Timer 0: 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0: Two 8-bit timers with a programmable prescaler Mode 1: 8-bit timer with a programmable prescaler + 8-bit counter Mode 2: 16-bit timer with a programmable prescaler Mode 3: 16-bit counter The resolution of timer is 1 tCYC. • Base Timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976μs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote Control Receiver Circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching Watchdog Timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM Correction Function Max 128 bytes / 2 addresses No.A0117-3/18 LC863448C/40C/32C/28C/24C/20C/16C Interrupts • 12 sources 8 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Data slicer 7. Vertical synchronous signal interrupt (VS), horizontal line (HS) 8. IIC, Software • Interrupt Priority Control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. Sub-routine Stack Level • A maximum of 128 levels (stack is built in the internal RAM) Multiplication/Division Instruction • 16 bits×8 bits (7 instruction cycle times) • 16 bits÷8 bits (7 instruction cycle times) 3 Oscillation Circuits • Built-in RC oscillation circuit used for the system clock • Built-in VCO circuit used for the system clock and OSD • X’tal oscillation circuit used for base timer, system clock and PLL reference Standby Function • HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. • HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. - Pull the reset terminal (RES) to low level. - Feed the selected level to either P70/INT0 or P71/INT1. Package • MFP36SDJ(375mil) • DIP36S(400mil) Development Tools • Flash EEPROM: • Evaluation chip: • Emulator: : Lead-free type : Lead-free type LC86F3448B LC863096 EVA86000 (main) + ECB863200A (evaluation chip board) + SUB863400A (sub board) + POD36-CABLE (cable) + POD36-DIP (for DIP36S) or POD36-MFP (for MFP36SDJ) No.A0117-4/18 LC863448C/40C/32C/28C/24C/20C/16C Package Dimensions unit : mm (typ) 3263 15.2 0.65 7.9 19 10.5 36 1 0.8 18 0.3 0.25 0.1 (2.25) 2.45max (0.8) SANYO : MFP36SDJ(375mil) Package Dimensions unit : mm (typ) 3170A 32.4 10.16 19 1 18 (3.25) 0.51min 3.0 3.95max 0.95 0.25 8.6 36 1.78 0.48 (1.1) SANYO : DIP36S(400mil) No.A0117-5/18 LC863448C/40C/32C/28C/24C/20C/16C Pin Assignment P10/SDA0 1 36 P03 P11/SCLK0 2 35 P02 P12/SDA1 3 34 P01 P13/SCLK1 4 33 P00 VSS 5 32 P17 XT1 6 31 P16/PWM3 30 P15/PWM2 29 P14/PWM1 28 P73/INT3/T0IN 27 P72/INT2/T0IN 26 P71/INT1 25 P70/INT0 LC863448C LC863440C LC863432C LC863428C LC863424C LC863420C LC863416C XT2 7 VDD 8 P04/AN4 9 P05/AN5 10 P06/AN6 11 P07/AN7 12 RES 13 24 P32 FILT 14 23 P31 CVIN 15 22 BL P30 16 21 B VS 17 20 G HS 18 19 R Top view SANYO: MFP36SDJ(375mil) “Lead-free Type” SANYO: DIP36S(400mil) “Lead-free Type” No.A0117-6/18 LC863448C/40C/32C/28C/24C/20C/16C System Block Diagram Interrupt Control IR X’tal RC VCO ROM Clock Generator Standby Control PLA PC PLL IIC Timer 0 ROM Correct Control ACC XRAM B Register Bus Interface C Register Port 1 ALU Base Timer Port 3 ADC Port 7 PSW INT0-3 Noise Rejection Filter RAR PWM RAM CGROM Data Slicer OSD Control Circuit Stack Pointer VRAM Port 0 Watchdog Timer No.A0117-7/18 LC863448C/40C/32C/28C/24C/20C/16C Pin Description Pin Description Table Terminal Function Description I/O VSS - Negative power supply XT1 I Input terminal for crystal oscillator XT2 O Output terminal for crystal oscillator VDD - Positive power supply RES I Reset terminal FILT O Filter terminal for PLL CVIN I Video signal input terminal VS I Vertical synchronization signal input terminal HS I Horizontal synchronization signal input terminal R O Red (R) output terminal of RGB image output G O Green (G) output terminal of RGB image output B O Blue (B) output terminal of RGB image output BL O Option Fast blanking control signal Switch TV image signal and caption/OSD image signal Port 0 I/O P00 to P07 • 8-bit input/output port, Pull-up resistor Input/output can be specified in nibble unit provided/not provided (If the N-ch open drain output is selected by option, the corresponding port data Output Format can be read in output mode.) CMOS/Nch-OD • Other functions AD converter input port (P04 to P07: 4 channels) Port 1 I/O • 8-bit input/output port Output Format CMOS/Nch-OD Input/output can be specified for each bit P10 to P17 (programmable pull-up resister provided) • Other functions Port 3 I/O P10 IIC0 data I/O P11 IIC0 clock output P12 IIC1 data I/O P13 IIC1 clock output P14 PWM1 output P15 PWM2 output P16 PWM3 output • 3-bit input/output port Input/output can be specified for each bit P30 to P32 (CMOS output/input with programmable pull-up resister) Port 7 I/O • 4-bit input/output port P70 Input or output can be specified for each bit P71 to P73 P70: I/O with programmable pull-up resister P71 to P73: CMOS output/input with programmable pull-up resister • Other functions P70 INT0 input/HOLD release input/ Nch-Tr. output for watchdog timer P71 INT1 input/HOLD release input P72 INT2 input/Timer 0 event input P73 INT3 input (noise rejection filter connected)/ Timer 0 event input Interrupt receiver format, vector addresses Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising/ H level L level disable enable enable 03H disable enable enable 0BH enable enable disable disable 13H enable enable disable disable 1BH Falling Vector Note: A capacitor of at least 10µF must be inserted between VDD and VSS when using this IC. No.A0117-8/18 LC863448C/40C/32C/28C/24C/20C/16C • Output form and existence of pull-up resistor for all ports can be specified for each bit. • Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. • Port status in reset Terminal I/O Pull-up resistor status at selecting CMOS output option Port 0 I Pull-up resistor OFF, ON after reset release Port 1 I Programmable pull-up resistor OFF Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Maximum supply Symbol Pins VDD max VDD Input voltage VI(1) Output voltage VO(1) Input/output voltage High Peak level output output current Conditions Ratings VDD[V] min typ unit max -0.3 +6.5 RES , HS , VS , CVIN -0.3 VDD+0.3 R, G, B, BL, FILT -0.3 VDD+0.3 VIO Ports 0, 1, 3, 7 -0.3 VDD+0.3 IOPH(1) Ports 0, 1, 3, 7 voltage •CMOS output •For each pin. IOPH(2) R, G, B, BL current •CMOS output •For each pin. -4 -5 Total ΣIOAH(1) Ports 0, 1 Total of all pins. -20 output ΣIOAH(2) Ports 3, 7 Total of all pins. -10 current ΣIOAH(3) R, G, B, BL Total of all pins. -12 Low Peak IOPL(1) Ports 0, 1, 3 For each pin. 20 level output 15 output current current Total IOPL(2) Port 7 For each pin. IOPL(3) R, G, B, BL For each pin. ΣIOAL(1) Ports 0, 1 Total of all pins. 40 20 5 ΣIOAL(2) Ports 3, 7 Total of all pins. current ΣIOAL(3) R, G, B, BL Total of all pins. 12 Pd max MFP36SDJ(375mil) Ta=-10 to +70°C 360 dissipation Operating mA output Maximum power DIP36S(400mil) -10 +70 range temperature mW 610 Topr temperature Storage V °C Tstg -55 +125 range No.A0117-9/18 LC863448C/40C/32C/28C/24C/20C/16C Recommended Operating Range at Ta = -10°C to +70°C, VSS = 0V Parameter Operating Symbol VDD(1) Pins VDD supply voltage Conditions Ratings VDD[V] 0.844μs ≤ tCYC ≤ VDD(2) Hold voltage VHD unit max 5.5 4.5 5.5 2.0 5.5 4.5 to 5.5 0.6VDD VDD 4.5 to 5.5 0.75VDD VDD 4μs ≤ tCYC ≤ 400μs VDD typ 4.5 0.852μs range min RAMs and the registers data are kept in HOLD mode. High level input VIH(1) Port 0 Output disable voltage VIH(2) • Ports 1, 3 (Schumitt) Output disable • Port 7 (Schumitt) port input/interrupt V • HS , VS , RES (Schumitt) VIH(3) Port 70 Output disable Watchdog timer input Low level input VIL(1) Port 0 Output disable voltage VIL(2) • Ports 1, 3 (Schumitt) Output disable • Port 7 (Schumitt) port input/interrupt 4.5 to 5.5 VDD-0.5 VDD 4.5 to 5.5 VSS 0.2VDD 4.5 to 5.5 VSS 0.25VDD 4.5 to 5.5 VSS 0.6VDD • HS , VS , RES (Schumitt) VIL(3) Port 70 Output disable Watchdog timer input CVIN VCVIN Operation tCYC(1) CVIN cycle time 5.0 • All functions operating tCYC(2) 0.7Vp-p 1Vp-p 1.4Vp-p 4.5 to 5.5 0.844 0.848 0.852 4.5 to 5.5 0.844 4.5 to 5.5 0.4 μs • OSD and Data slicer are not Vp-p* 400 operating Oscillation FmRC frequency Internal RC oscillation 0.8 3.0 MHz range * Vp-p: Peak-to-peak voltage No.A0117-10/18 LC863448C/40C/32C/28C/24C/20C/16C Electrical Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter High level input Symbol IIH(1) Pins Ports 0, 1, 3, 7 current Conditions Ratings VDD[V] min typ max unit •Output disable •Pull-up MOS Tr. OFF •VIN=VDD (including the off-leak 4.5 to 5.5 1 4.5 to 5.5 1 current of the output Tr.) IIH(2) • RES •VIN=VDD • HS , VS Low level input IIL(1) Ports 0, 1, 3, 7 current μA •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including the off-leak 4.5 to 5.5 -1 4.5 to 5.5 -1 4.5 to 5.5 VDD-1 VDD-0.5 current of the output Tr.) IIL(2) • RES VIN=VSS • HS , VS High level VOH(1) output voltage • CMOS output of IOH=-1.0mA ports 0, 1, 3, 71 to 73 VOH(2) R, G, B, BL IOH=-0.1mA R. G. B: digital mode 4.5 to 5.5 Low level output VOL(1) Ports 0, 1, 3, 71 to 73 IOL=10mA 4.5 to 5.5 1.5 voltage VOL(2) Ports 0, 3, 71 to 73 IOL=1.6mA 4.5 to 5.5 0.4 VOL(3) • R, G, B, BL IOL=3.0mA • Port 1 R. G. B: digital mode 4.5 to 5.5 0.4 VOL(4) Port 70 IOL=1mA 4.5 to 5.5 0.4 Rpu Ports 0, 1, 3, 7 VOH=0.9VDD RBS • P10 to P12 Pull-up MOS Tr. resistance Bus terminal 4.5 to 5.5 13 V 38 80 kΩ 4.5 to 5.5 130 300 Ω 4.5 to 5.5 0.1VDD • P11 to P13 short circuit resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis VHYS • Ports 1, 3, 7 Output disable • RES voltage • HS , VS Input clump VCLMP CVIN CP All pins V 5.0 voltage Pin capacitance 2.3 2.5 2.7 • f=1MHz • Every other terminals are connected to VSS. 4.5 to 5.5 10 pF • Ta=25ºC No.A0117-11/18 LC863448C/40C/32C/28C/24C/20C/16C IIC Input/Output Conditions at Ta = -10°C to +70°C, VSS = 0V Parameter Standard Symbol min High speed max min unit max SCL Frequency fSCL 0 100 0 400 BUS free time between stop - start tBUF 4.7 - 1.3 - μs HOLD time of start, restart condition tHD;STA 4.0 - 0.6 - μs L time of SCL tLOW 4.7 - 1.3 - μs H time of SCL tHIGH 4.0 - 0.6 - μs Set-up time of restart condition tSU;STA 4.7 - 0.6 - μs HOLD time of SDA tHD;DAT 0 - 0 0.9 μs Set-up time of SDA tSU;DAT 250 - 100 - ns Rising time of SDA, SCL tR - 1000 20+0.1Cb 300 ns Falling time of SDA, SCL tF - 300 20+0.1Cb 300 ns Set-up time of stop condition tSU;STO 4.0 - 0.6 - μs kHz Refer to figure 8 Note 1: Cb: Total capacitance of all BUS (unit : pF) Pulse Input Conditions at Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Pins Ratings Conditions VDD[V] High/low level tPIH(1) • INT0, INT1 •Interrupt acceptable pulse width tPIL(1) • INT2/T0IN •Timer0-countable tPIH(2) INT3/T0IN •Interrupt acceptable tPIL(2) (1tCYC is selected for noise •Timer0-countable min 4.5 to 5.5 1 4.5 to 5.5 2 4.5 to 5.5 32 typ unit max rejection clock.) tPIH(3) INT3/T0IN •Interrupt acceptable tPIL(3) (16tCYC is selected for •Timer0-countable tCYC noise rejection clock.) tPIH(4) INT3/T0IN •Interrupt acceptable tPIL(4) (64tCYC is selected for •Timer0-countable 4.5 to 5.5 128 4.5 to 5.5 200 4.5 to 5.5 3 noise rejection clock.) tPIL(5) RES Reset acceptable tPIH(6) HS , VS •Display position controllable •The active edge of tPIL(6) HS and VS must be apart μs at least 1tCYC. •Refer to figure 4. Rising/falling tTHL time tTLH Refer to figure 4. HS 4.5 to 5.5 500 ns AD Converter Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Resolution N Absolute ET Pins Conditions Ratings VDD[V] min typ 6 (Note 2) Analog input tCAD VAIN Vref selection to conversion 1 bit conversion finish time=2×Tcyc AN4 to AN7 VSS voltage range Analog port IAINH VAIN=VDD input current IAINL VAIN=VSS VDD 1 -1 LSB μs 1.69 4.5 to 5.5 unit bit ±1 precision Conversion time max V μA Note 2: Absolute precision does not include quantizing error (1/2LSB). No.A0117-12/18 LC863448C/40C/32C/28C/24C/20C/16C Analog Mode RGB Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Pins Analog output R.G.B voltage Analog Conditions mode R.G.B VDD[V] Low level output Intensity output output Time setting Ratings Hi level output 5.0 min. typ. max. 0.45 0.5 0.55 0.90 1.0 1.10 1.35 1.5 1.65 70% 50 10pf load unit V ns Sample Current Dissipation Characteristics at Ta = -10°C to +70°C, VSS = 0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation Symbol IDDOP(1) Pins VDD during basic Conditions Ratings VDD[V] min typ max unit • FmX’tal=32.768kHz X’tal oscillation operation • System clock : VCO (Note 3) • VCO for OSD operating 4.5 to 5.5 11 25 • OSD is Digital mode • Internal RC oscillation stops IDDOP(2) VDD mA • FmX’tal=32.768kHz X’tal scillation • System clock: VCO • VCO for OSD operating 4.5 to 5.5 20 35 4.5 to 5.5 65 300 μA 4.5 to 5.5 3 9 mA 4.5 to 5.5 300 1000 • OSD is Analog mode • Internal RC oscillation stops IDDOP(3) VDD • FmX’tal=32.768kHz X’tal scillation • System clock : X’tal (Instruction cycle time: 366.2µs) • VCO for system VCO for OSD, internal RC oscillation stop • Data slicer, AD converters stop Current dissipation IDDHALT(1) VDD • HALT mode • FmX’tal=32.768kHz in HALT mode (Note 3) X’tal oscillation • System clock : VCO • VCO for OSD stops • Internal RC oscillation stops IDDHALT(2) VDD • HALT mode • FmX’tal=32.768kHz X’tal oscillation • VCO for system stops • VCO for OSD stops • System clock : Internal RC IDDHALT(3) VDD μA • HALT mode • FmX’tal=32.768kHz X’tal oscillation • VCO for system stops 4.5 to 5.5 57 200 4.5 to 5.5 0.05 20 • VCO for OSD stops • System clock: X’tal (Instruction cycle time: 366.2μs) Current dissipation in HOLD mode IDDHOLD VDD • HOLD mode • All oscillation stops. μA (Note 3) Note 3: The currents through the output transistors and the pull-up MOS transistors are ignored. No.A0117-13/18 LC863448C/40C/32C/28C/24C/20C/16C Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10°C to +70°C) Frequency 32.768kHz Manufacturer EPSON TOYOCOM Oscillator Recommended circuit parameters Operating Oscillation supply voltage stabilizing time C1 C2 Rf Rd range typ max 18pF 18pF OPEN 390kΩ 4.5 to 5.5V 1.0s 1.5s Notes Applicable MC-306 CL value=12.5pF SMD type Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 XT2 Rf Rd C1 C2 X’tal Figure 1 Recommended Oscillation Circuit No.A0117-14/18 LC863448C/40C/32C/28C/24C/20C/16C VDD VDD limit 0V Power supply Reset time RES Internal RC resonator oscillation XT1,XT2 tmsVCO VCO for system Operation mode stable Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD release Valid Internal RC resonator oscillation XT1, XT2 tmsVCO VCO for system Operation mode stable HOLD Instruction execution mode HOLD Release Signal and Oscillation Stabilizing Time Figure 2 Oscillation Stabilizing Time No.A0117-15/18 LC863448C/40C/32C/28C/24C/20C/16C tPIL (1)-(5) tPIH (1)-(4) Figure 3 Pulse Input Timing Condition - 1 tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) more than ±1tCYC Figure 4 Pulse Input Timing Condition - 2 LC863448C 10kΩ HS HS C536 Figure 5 Recommended Interface Circuit No.A0117-16/18 LC863448C/40C/32C/28C/24C/20C/16C Noise filter 1μF C-Video CVIN 200Ω 1000pF Coupling capacitor Output impedance of C-Video before Noise filter should be less then 100Ω. Figure 6 CVIN Recommended Circuit 100Ω 33000pF 1MΩ 2.2μF FILT + - Figure 7 FILT Recommended Circuit Note: Place FILT parts on board as close to the microcontroller as possible. P S P Sr SDA tBUF tHD;STA tR tF tHD;STA tsp SCL tHIGH tLOW tHD;DAT S : start condition P : stop condition Sr : restart condition tSU;DAT tsp : spike suppression tSU;STA tSU;STO Standard mode : not exist High speed mode : less than 50ns Figure 8 IIC Timing No.A0117-17/18 LC863448C/40C/32C/28C/24C/20C/16C I ≈1mA ↓ I ↓ I R≈ 500Ω ↓ PAD Figure 9 R.G.B. Analog Output Equivalent Circuit SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2008. Specifications and information herein are subject to change without notice. PS No.A0117-18/18