Ordering number : ENN*6712 CMOS IC LC87F72C8A 8-Bit Single Chip Microcontroller with 128 KB Flash Memory and 2048-Byte RAM On Chip Preliminary Overview The LC87F72C8A is an 8 bit single chip microcontroller with the following on-chip functional blocks : - CPU: operable at a minimum bus cycle time of 100 ns - 128K bytes flash ROM (on-board rewritable) - On-chip RAM: 2048 bytes - LCD controller / driver - 16 bit timer / counter (can be divided into two 8 bit timers) - 16 bit timer / PWM (can be divided into two 8 bit timers) - Timer for use as date / time clock - Synchronous serial I/O port (with automatic block transmit / receive function) - Asynchronous / synchronous serial I/O port - 12-channel × 8-bit AD converter - Small signal detector - 14-source 10-vectored interrupt system All of the above functions are fabricated on a single chip. Features (1) Flash ROM -Single 5V power supply, on-board writable -Block erase in 128 byte units -131072 × bits (LC87F72C8A) (2) Random Access Memory (RAM): 2048 × 9 bits (LC87F72C8A) Ver.1.04 61899 91400 RM (IM) SK No.6712-1/24 LC87F72C8A (3) Minimum Bus Cycle Time: 100 ns (10 MHz) Note: The bus cycle time indicates ROM read time. (4) Minimum Instruction Cycle Time: 300 ns (10MHz) (5) Ports - Input/output ports Data direction programmable for each bit individually : 26 (P1n, P30-P35, P70-P73, P8n) Data direction programmable in nibble units : 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) - Input ports : 2 (XT1,XT2) - LCD ports Segment output : 48 (S00-S47) Common output : 4 (COM0-COM3) Bias terminals for LCD driver 3 (V1-V3) Other functions Input/output ports : 48(PAn,PBn,PCn,PDn,PEn,PFn) Input ports : 7 (PLn) - Oscillator pins : 2 (CF1,CF2) - Reset pin : 1 (RES) - Power supply : 6 (VSS1-3,VDD1-3) (6) LCD controller - Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias) - Segment output and common output can be switched to general purpose input/output ports. (7) Small signal detection (MIC signals etc) - Counts pulses with the level which is greater than a preset value - 2 bit counter (8) Timers - Timer 0: 16 bit timer / counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit Counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register - Timer 1: PWM / 16 bit timer with toggle output function Mode 0: 2 channel 8 bit timer (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer (with toggle output) Toggle output from lower 8 bits is also possible. Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM. - Base Timer 1) The clock signal can be selected from any of the following : Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts of five different time intervals are possible. No.6712-2/24 LC87F72C8A (9) Serial-interface - SIO 0: 8 bit synchronous serial interface 1) LSB first / MSB first is selectable 2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 Tcyc) 3) Consecutive automatic data communication (1-256 bits) - SIO 1: 8 bit asynchronous / synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 Tcyc) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048Tcyc) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 Tcyc) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) (10) AD converter -8 bits × 12 channels (11) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal) -Noise rejection function (noise rejection filter’s time constant can be selected from 1 / 32 / 128 Tcyc) (12) Watchdog timer - The watching time period is determined by an external RC. - Watchdog timer can produce interrupt or system reset (13) Interrupts: 14 sources, 10 vectors 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level Interrupt signal 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L 4 0001BH H or L INT3/Base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0 8 0003BH H or L SIO1 9 00043H H or L ADC/MIC 10 0004BH H or L Port 0 • Priority Level: X>H>L • For equal priority levels, vector with lowest address takes precedence. (14) Subroutine stack levels: 1024 levels max. Stack is located in RAM. (15) Multiplication and division - 16 bit × 8 bit (executed in 5 cycles) - 24 bit × 16 bit (12 cycles) - 16 bit ÷ 8 bit ( 8 cycles) - 24 bit ÷ 16 bit (12 cycles) (16) Oscillation circuits - On-chip RC oscillation for system clock use. - CF oscillation for system clock use. (Rf built in, Rd external) - Crystal oscillation low speed system clock use. (Rf built in, Rd external) No.6712-3/24 LC87F72C8A (17) Standby function - HALT mode HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1) Oscillation circuits are not stopped automatically. 2) Released by the system reset or interrupts. -HOLD mode HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. 1) CF, RC and crystal oscillation circuits stop automatically. 2) Released by any of the following conditions. 1. Low level input to the reset pin 2. Specified level input to one of INT0, INT1, INT2 3. Port 0 interrupt -X’tal HOLD made X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1) CF and RC oscillation circuits stop automatically. 2) Crystal oscillator operation is kept in its state at HOLD mode inception. 3) Released by any of the following conditions 1. Low level input to the reset pin 2. Specified level input to one of INT0, INT1, INT2 3. Port 0 interrupt 4. Base-timer interrupt (18) Package - QIP100E - SQFP100 (19) Development tools - Evaluation chip: LC876096 - Emulator: EVA62S + ECB876500 (Evaluation chip board) + SUB877200 + POD100QFP or POD100SQFP (Type B) (20) Same package and pin assignment as mask ROM version. 1) LC877200 series options can be set using flash ROM data. Thus the board used for mass production can be used for debugging and evaluation without modifications. 2) If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM version. No.6712-4/24 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN S0/PA0 V2/PL5 V1/PL4 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30 P31 VSS3 VDD3 P32 P33 P34 P35 P00 P01 P02 P03 P04 P05 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 V3/PL6 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 S23/PC7 S22/PC6 S21/PC5 LC87F72C8A Pin Assignment 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1PA1 SANYO : QIP100-E Package Dimension (unit : mm) 3151 SANYO : QIP100-E No.6712-5/24 LC87F72C8A 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 Pin Assignment 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1PA1 S0/PA0 P73/INT3/T0IN P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 S47/PF7 V3/PL6 V2/PL5 V1/PL4 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30 P31 VSS3 VDD3 P32 P33 P34 P35 P00 P01 P02 P03 P04 P05 P06 P07 P10/SO0 SANYO : SQFP-100 Package Dimension (unit : mm) 3181B SANYO : SQFP-100 No.6712-6/24 LC87F72C8A System Block Diagram Interrupt Control IR CF RC Flash ROM Clock Generator Stand-by Control PLA PC X’tal Bus Interface ACC SIO0 Port 0 B Register SIO1 Port 1 C Register Timer 0 Port 3 ALU Timer 1 Port 7 Base Timer Port 8 PSW LCD Controller ADC RAR INT0 to 3 Noise Rejection Filter Weak Signa Detector RAM Stack Pointer Watch Dog Timer No.6712-7/24 LC87F72C8A Pin Assignment Pin name I/O VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 PORT0 P00 to P07 - • Power supply (-) Function No - • Power supply (+) No I/O • 8bit input/output port • Data direction programmable in nibble units • Use of pull-up resistor can be specified in nibble units • Input for HOLD release • Input for port 0 interrupt Yes PORT1 P10 to P17 I/O • 8bit input/output port • Data direction programmable for each bit • Use of pull-up resistor can be specified for each bit individually • Other pin functions P10 SIO0 data output P11 SIO0 data input or bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input or bus input/output P15 SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output Yes PORT3 P30 to P35 I/O Yes PORT7 P70 to P73 I/O • 6bit Input/output port • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit individually • 4bit Input/output port • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit individually • Other functions P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input P73: INT3 input(noise rejection filter attached)/timer 0 event input/Timer0H capture input AD input port: AN8(P70), AN9(P71) • Interrupt detection selection Rising Falling Rising and falling H level L level INT0 INT1 INT2 INT3 Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Option Yes Yes No No No Yes Yes No No No.6712-8/24 LC87F72C8A Pin name I/O Function description Option I/O • 8bit Input/output port • Input/output can be specified for each bit individually • Other functions: AD input port: AN0 to AN7 Small signal detector input port: MICIN(P87) No S0/PA0 to S7/PA7 I/O • Segment output for LCD • Can be used as general purpose input/output port (PA) No S8/PB0 to S15/PB7 I/O • Segment output for LCD • Can be used as general purpose input/output port (PB) No S16/PC0 to S23/PC7 I/O • Segment output for LCD • Can be used as general purpose input/output port (PC) No S24 /PD0to S31/PD7 I/O • Segment output for LCD • Can be used as general purpose input/output port (PD) No S32/PE0 to S39/PE7 I/O • Segment output for LCD • Can be used as general purpose input/output port (PE) No S40/PF0 to S47/PF7 I/O • Segment output for LCD • Can be used as general purpose input/output port (PF) No COM0/PL0 to COM3/PL3 I/O • Common output for LCD • Can be used as general purpose input port (PL) No V1/PL4 to V3/PL6 I/O • LCD output bias power supply • Can be used as general purpose input port (PL) No PORT8 P80 to P87 RES I Reset terminal No XT1 I • Input for 32.768kHz crystal oscillation • Other functions: General purpose input port AD input port: AN10 • When not in use, connect to VDD1 No XT2 I/O • Output for 32.768kHz crystal oscillation • Other functions: General purpose input port AD input port: AN11 • When not in use, set to oscillation mode and leave open No CF1 I Input terminal for ceramic oscillator No CF2 O Output terminal for ceramic oscillator No No.6712-9/24 LC87F72C8A Port Configuration Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode. Terminal P00 to P07 P10 to P17 P30 to P35 Option applies to: Options each bit 1 CMOS 2 Nch-open drain Programmable (Note 1) None 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain None each bit each bit Output Form Pull-up resistor P70 – None Nch-open drain Programmable P71 to P73 – None CMOS Programmable P80 to P87 – None Nch-open drain S0/PA0 to S47/PF7 – None CMOS COM0/PL0 to COM3/PL3 – None Input only None V1/PL4 to V3/PL6 – None Input only None XT1 – None Input only None XT2 – None Output for 32.768kHz crystal oscillation None None Programmable Note 1Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00-03, P04-07). * Note 1: Connect as follows to reduce noise on VDD. VSS1, VSS2 and VSS3 must be connected together and grounded. *Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the VDD2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore, when the VDD2 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented. LSI VDD1 Power Back-up capacitors *2 VDD2 VDD3 VSS1 VSS2 VSS3 No.6712-10/24 LC87F72C8A 1. Absolute Maximum Ratings at Ta=25°C and VSS1=VSS2=VSS3=0V Parameter Symbol Pins Conditions Ratings VDD[V] min. typ. max. Supply voltage VDDMAX VDD1,VDD2,VDD3 VDD1=VDD2 =VDD3 -0.3 +6.5 Supply voltage for LCD VLCD V1/PL4, V2/PL5, V3/PL6 VDD1=VDD2 =VDD3 -0.3 VDD Input voltage VI Port L XT1,XT2,CF1, RES -0.3 VDD+0.3 Input/Output voltage VI0(1) • Port0, 1, 3, 7, 8 • Port A, B, C, D, E, F -0.3 VDD+0.3 High level output current IOPH(1) Port 0, 1, 3 Peak output current Total output current Low Peak level output output current current Total output current • CMOS output selected • Current at each pin -10 -3 V mA IOPH(2) Port 71,72,73 Current at each pin IOPH(3) Port A, B, C, D, E, F Current at each pin ΣIOAH(1) Port 0, 1, 32, 33, 34, 35 Total of all pins -40 ΣIOAH(2) Port 30, 31 Total of all pins -10 ΣIOAH(3) Port 7 Total of all pins -5 ΣIOAH(4) Port A, B, C Total of all pins -25 ΣIOAH(5) Port D, E, F Total of all pins -25 IOPL(1) Port 0, 1, 32-35 Current at each pin 20 IOPL(2) Port 30, 31 Current at each pin 30 IOPL(3) Port 7,8 Current at each pin 5 IOPL(4) Port A, B,C, D, E, F Current at each pin ΣIOAL(1) Port 0, 1, 32, 33, 34, 35 Total of all pins -5 15 60 ΣIOAL(2) Port 30, 31 Total of all pins 60 ΣIOAL(3) Port 7,8 Total of all pins 20 ΣIOAL(4) Port A,B,C Total of all pins 40 ΣIOAL(5) Port D, E, F Total of all pins 40 QIP100E Ta = -20 to +70°C 500 Maximum power Pdmax consumption unit SQFP100 mW 400 Operating temperature range Topg -20 70 Storage temperature range Tstg -55 125 °C No.6712-11/24 LC87F72C8A 2. Recommended Operating Range at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol Pins Operating VDD(1) supply voltage range VDD(2) VDD1=VDD2=VDD3 Supply voltage range in Hold mode VHD Input high voltage Input low voltage Operation cycle time Conditions Ratings VDD[V] min. typ. max. 0.294µs≤ tCYC≤ 200µs 4.5 5.5 0.735µs≤ tCYC≤ 200µs 3.0 5.5 VDD1 Keep RAM and register data in HOLD mode. 2.0 5.5 VIH(1) • Port 0, 3, 8 • Port A,B,C,D,E,F,L Output disable 3.0–5.5 0.3VDD +0.7 VDD VIH(2) Output disable • Port 1 • Port 71,72,73 • P70 port input/interrupt 3.0–5.5 0.3VDD +0.7 VDD VIH(3) P87 small signal input Output disable 3.0–5.5 0.75VDD VDD VIH(4) Port 70 Watchdog timer Output disable 3.0–5.5 VDD 0.9VDD VIH(5) XT1, XT2, CF1, RES VIL(1) • Port 0, 3, 8 • Port A,B,C,D,E,F,L Output disable 3.0–5.5 VSS 0.15VDD +0.4 VIL(2) Output disable • Port 1 • Port 71,72,73 • P70 port input/interrupt 3.0–5.5 VSS 0.1VDD +0.4 VIL(3) Port 87 small signal input Output disable 3.0–5.5 VSS 0.25VDD VIL(4) Port 70 Watchdog timer 3.0–5.5 VSS 0.8VDD -1.0 VIL(5) XT1,XT2,CF1, RES 3.0–5.5 VSS 0.25VDD 3.0–5.5 0.75VDD Output disable tCYC External system FEXCF(1) CF1 clock frequency • CF2 open • system clock divider :1/1 • external clock DUTY = 50 ± 5% • CF2 open • system clock divider :1/2 4.5–5.5 0.294 200 0.735 200 4.5–5.5 0.1 10 3.0–5.5 0.1 4 4.5–5.5 0.2 20 0.2 V VDD 3.0–5.5 3.0–5.5 unit µs MHz 8 Continued/ No.6712-12/24 LC87F72C8A Parameter Oscillation frequency range (Note 1) Symbol Pins Conditions FmCF(1) CF1, CF2 10MHz ceramic resonator oscillation FmCF(2) CF1, CF2 4MHz ceramic resonator oscillation Ratings VDD[V] min. typ. 4.5–5.5 10 3.0–5.5 4 max. unit MHz Refer to figure 1 Refer to figure 1 FmRC FsX’tal XT1, XT2 RC oscillation 3.0–5.5 32.768kHz crystal resonator oscillation 3.0–5.5 0.3 1.0 32.768 2.0 kHz Refer to figure 2 (Note 1) The parts value of oscillation circuit is shown in table 1 and table 2. No.6712-13/24 LC87F72C8A 3. Electrical Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter High level input current Low level input current High level output voltage Symbol IIH(1) Pins • Port 0,1,3,7,8 • Output disabled • Port A,B,C,D,E,F,L • Pull-up resister OFF. • VIN=VDD (including OFF state leak current of the output Tr.) min. typ. max. 3.0–5.5 1 RES VIN=VDD 3.0–5.5 1 IIH(3) XT1,XT2 When configured as an input 3.0–5.5 port VIN=VDD 1 IIH(4) CF1 VIN=VDD 3.0–5.5 IIH(5) P87/AN7/MICIN small signal input VIN=VBIS+0.5V (VBIS : Bias voltage) 3.0–5.5 4.2 IIL(1) • Port 0,1,3,7,8 • Output disabled • Port A,B,C,D,E,F,L • Pull-up resister OFF. • VIN=VSS (including OFF state leak current of the output Tr.) 3.0–5.5 -1 15 -8.5 -4.2 RES VIN=VSS 3.0–5.5 -1 IIL(3) XT1,XT2 When configured as an input 3.0–5.5 port VIN=VSS -1 IIL(4) CF1 VIN=VSS 3.0–5.5 -15 IIL(5) P87/AN7/MICIN small signal input VIN=VBIS-0.5V (VBIS : Bias voltage) 3.0–5.5 -15 VOH(1) Port 0,1,3: CMOS output option IOH=-1.0mA 4.5–5.5 VDD-1 VOH(2) IOH=-0.1mA 3.0–5.5 VDD-0.5 VOH(3) Port 7 IOH=-0.4mA 3.0–5.5 VDD-1 VOH(4) Port A,B,C,D,E,F IOH=-1.0mA 4.5–5.5 VDD-1 IOH=-0.1mA 3.0–5.5 VDD-0.5 IOL=10mA 4.5–5.5 IOL=1.6mA 3.0–5.5 0.4 VOL(1) Port 0,1,3 VOL(2) 1.5 Port 30,31 IOL=30mA 4.5–5.5 1.5 VOL(4) Port 7,8 IOL=1mA 4.5–5.5 0.4 IOL=0.5mA 3.0–5.5 0.4 Port A,B,C,D,E,F IOL=8mA 4.5–5.5 1.5 IOL=1.4mA 3.0–5.5 VODLS S0–S47 I0=0mA VLCD, 2/3VLCD, 1/3VLCD level output Refer to figure 8 3.0–5.5 0 ± 0.2 VODLC COM0–COM3 3.0–5.5 I0=0mA VLCD, 2/3VLCD, 1/2VLCD 1/3VLCD level output Refer to figure 8 0 ± 0.2 VOL(7) µA V VOL(3) VOL(6) unit 15 8.5 IIL(2) VOL(5) LCD output voltage regulation Ratings VDD[V] IIH(2) VOH(5) Low level output voltage Conditions 0.4 Continued/ No.6712-14/24 LC87F72C8A Parameter Symbol Pins LCD bias resistor RLCD(1) Resistance per one bias resistor RLCD(2) • Resistance per one bias resistor • 1/2R mode Resistance of Rpu • Port 0,1,3,7 pull-up • Port A,B,C,D,E,F MOS Tr. Hysterisis voltage Conditions Ratings VDD[V] min. typ. Refer to figure 8 3.0–5.5 60 Refer to figure 8 3.0–5.5 30 VOH=0.9VDD 4.5–5.5 15 40 70 3.0–5.5 25 70 150 VHIS(1) • Port 1,7 • RES 3.0–5.5 0.1VDD VHIS(2) Port 87 small signal input All pins 3.0–5.5 0.1VDD 3.0–5.5 10 Pin capacitance CP Input sensitivity Vsen max. • All Other Terminals unit kΩ kΩ V pF Connected To VSS. • F=1MHz • Ta=25°C Port 87 small signal input 3.0–5.5 0.12VDD Vpp No.6712-15/24 LC87F72C8A 4. Serial Input/Output Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Serial input Output clock Serial clock Input clock Parameter Symbol Conditions Ratings VDD[V] min. 3.0–5.5 4/3 Cycle time tSCK(1) Low level pulse width tSCKL(1) 2/3 tSCKLA(1) 2/3 tSCKH(1) 2/3 High level pulse width SCK0(P12) Refer to figure 6 tSCKHA(1) typ. Low level pulse width High level pulse width Cycle time tSCKL(2) 1 tSCKH(2) 1 Low level pulse width tSCKL(3) 1/2 tSCKLA(2) 3/4 tSCKH(3) 1/2 High level pulse width SCK1(P15) SCK0(P12) Refer to figure 6 • CMOS output • Refer to figure 6 3.0–5.5 3.0–5.5 2 4/3 SCK1(P15) • CMOS output • Refer to figure 6 3.0–5.5 Cycle time tSCK(4) Low level pulse width High level pulse width tSCKL(4) 1/2 tSCKH(4) 1/2 Data hold time tsDI thDI tSCK 2 tSCKHA(2) Data set-up time unit 3 tSCK(2) tSCK(3) max. tCYC Cycle time Output delay time tdDO Serial output Pins 2 SI0(P10), SI1(P13), SB0(P11), SB1(P14) • Measured with respect 4.5–5.5 0.03 to SI0CLK leading edge. • Refer to figure 6 3.0–5.5 0.1 4.5–5.5 0.03 3.0–5.5 0.1 SO0(P12), SO1(P15), SB0(011), SB1(P14) • When Port is open drain: Time delay form SIOCLK trailing edge to the SO data change • Refer to figure 6 tCYC tSCK µs 4.5–5.5 1/3 tCYC +0.05 3.0–5.5 1/3 tCYC +0.25 No.6712-16/24 LC87F72C8A 5. Pulse Input Conditions at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol High/low level tPIH(1) pulse width tPIL(1) Pins INT0(P70), INT1(P71), INT2(P72) tPIH(2) tPIL(2) INT3(P73) (Noise rejection ratio is 1/1.) tPIH(3) tPIL(3) INT3(P73) (Noise rejection ratio is 1/32.) tPIH(4) tPIL(4) INT3(P73) (Noise rejection ratio is 1/128.) tPIL(5) tPIL(5) MICIN(P87) tPIL(6) RES Ratings Conditions VDD[V] • Condition that interrupt 3.0–5.5 is accepted • Condition that event input to timer 0 is accepted • Condition that interrupt 3.0–5.5 is accepted • Condition that event input to timer 0 is accepted • Condition that interrupt 3.0–5.5 is accepted • Condition that event input to timer 0 is accepted • Condition that interrupt 3.0–5.5 is accepted • Condition that event input to timer 0 is accepted • Condition that signal is 3.0–5.5 accepted to small signal detection counter. • Condition that reset is 3.0–5.5 accepted min. 1 typ. max. unit tCYC 2 64 256 1 µs 200 6. AD converter Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol Resolution Absolute precision Conversion time N ET •CAD Pins AN0(P80) –AN7(P87) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) Conditions (Note2) AD conversion time = 32 × tCYC (ADCR2=0) (Note 3) AD conversion time = 64 × tCYC (ADCR2=1) (Note 3) Analog input voltage range Analog port input current VAIN IAINH IAINL VAIN=VDD VAIN=VSS Ratings VDD[V] min. 3.0–5.5 3.0–5.5 4.0–5.5 max. 8 15.62 (tCYC= 0.488µs) 3.0–5.5 23.52 (tCYC= 0.735µs) 4.5–5.5 18.82 (tCYC= 0.294µs) 3.0–5.5 47.04 (tCYC= 0.735µs) 3.0–5.5 VSS 3.0–5.5 3.0–5.5 typ. ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) 97.92 (tCYC= 1.53µs) VDD 1 unit bit LSB µs V µA -1 (Note 2) Absolute precision does not include quantizing error (±1/2 LSB). (Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register. No.6712-17/24 LC87F72C8A 7. Current Consumption Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Parameter Symbol Pins Conditions Ratings VDD[V] min. typ. max Current consumption IDDOP(1) during normal operation (Note 4) VDD1= • FmCF=10MHz VDD2= Ceramic resonator VDD3 oscillation • FsX’tal=32.768kHz crystal oscillation • System clock: CF 10MHz oscillation • Internal RC oscillation stopped. • Divider : 1/1 4.5–5.5 18 35 IDDOP(2) • CF1=20MHz external clock • FsX’tal=32.768kHz crystal oscillation • System clock: CF1 oscillation • Internal RC oscillation stopped. • Divider :1/2 4.5–5.5 19 36 IDDOP(3) • FmCF=4MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock: CF 4MHz oscillation • Internal RC oscillation stopped. • Divider :1/1 4.5–5.5 10 22 3.0–4.5 5.5 14 4.5–5.5 6 15 3.0–4.5 3 12 4.5–5.5 4.5 14 3.0–4.5 2 9 IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: RC oscillation • Divider :1/2 • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: 32.768kHz • Internal RC oscillation stopped. • Divider :1/2 unit mA Continued/ No.6712-18/24 LC87F72C8A Parameter Current consumption during HALT mode (Note 4) Symbol IDDHALT(1) Pins Conditions Ratings VDD[V] min. typ. max. 4.5–5.5 VDD1= HALT mode VDD2= • FmCF=10MHz Ceramic VDD3 resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock : CF 10MHz oscillation • Internal RC oscillation stopped. • Divider: 1/1 6 12 4.5–5.5 7 13 IDDHALT(2) HALT mode • CF1=20MHz external clock • FsX’tal=32.768kHz crystal oscillation • System clock : CF1 oscillation • Internal RC oscillation stopped. • Divider :1/2 IDDHALT(3) HALT mode 4.5–5.5 • FmCF=4MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock : 3.0–4.5 CF 4MHz oscillation • Internal RC oscillation stopped. • Divider: 1/1 2.5 6 1.5 5 4.5–5.5 HALT mode • FmCF=0Hz (Oscillation stop) • FsX’tal=32.768kHz crystal oscillation 3.0–4.5 • System clock : RC oscillation • Divider: 1/2 600 1600 300 1300 25 100 12 60 IDDHALT(4) IDDHALT(5) IDDHALT(6) IDDHALT(7) IDDHALT(8) HALT mode 4.5–5.5 • FmCF=0Hz (Oscillation stop) • FsX’tal=32.768kHz crystal oscillation • System clock : 32.768kHz 3.0–4.5 • Internal RC oscillation stopped. • Divider: 1/2 unit mA µA Continued/ No.6712-19/24 LC87F72C8A Parameter Symbol Current consumption IDDHOLD(1) during HOLD mode Pins Conditions VDD1 HOLD mode • CF1=VDD or open (when using external clock) Date/time clock HOLD mode • CF1=VDD or open (when using external clock) • FmX’tal=32.768kHz crystal oscillation IDDHOLD(2) Current consumption IDDHOLD(3) during Date/time clock HOLD mode VDD1 IDDHOLD(4) Ratings VDD[V] min. typ. max. 4.5–5.5 0.015 25 3.0–4.5 0.015 20 4.5–5.5 20 100 3.0–4.5 8 55 unit µA (Note 4) The currents through the output transistors and the pull-up MOS transistors are ignored. 8. F-ROM Write Characteristics at Ta=+10 to +55°C, VSSI=VSS2=VSS3=0V Parameter Symbol On board write current IDDF(1) Write cycle time tFW(1) Pins Conditions VDD1 • 128-byte write • Including erase current • 128-byte write • Including erase current • Not including time to prepare 128-byte data Ratings VDD[V] min. unit typ. max. 4.5–5.5 30 65 mA 4.5–5.5 6.3 9 mS No.6712-20/24 LC87F72C8A Main system clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 1. Main system clock oscillation circuit characteristics using ceramic resonator Frequency Manufacturer C1 10MHz Murata 4MHz Murata Oscillation stabilizing time Operating supply voltage range Rd1 Circuit parameters Oscillator C2 typ max Notes CSA10.0MTZ CST10.0MTW 33pF 33pF 470Ω (30pF) (30pF) 470Ω 4.5 – 5.5V 4.5 – 5.5V 0.09ms 0.09ms 0.4ms 0.4ms Built in C1,C2 CSA4.00MG CST4.00MGW 33pF 33pF 680Ω (30pF) (30pF) 680Ω 3.0 – 5.5V 3.0 – 5.5V 0.07ms 0.07ms 0.2ms 0.2ms Built in C1,C2 The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4) Subsystem clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator Frequency Manufacturer Circuit parameters Oscillator C3 32.768MHz Seiko EPSON C-002RX MC-306 18pF C4 Rf Rd2 18pF OPEN 390kΩ Operating supply voltage range 3.0 – 5.5V Oscillation stabilizing time typ max 1.0s 3.0s Notes The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4) (Notes) • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 CF2 XT1 Rd1 XT2 Rf Rd2 C1 CF C2 C4 C3 X’tal Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit No.6712-21/24 LC87F72C8A 0.5VDD Figure 3 AC timing measurement point VDD VDD limit Power Supply 0V Reset time RES Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode Reset Unfixed Instruction execution mode Reset time and oscillation stable time HOLD release signal Without HOLD Release signal HOLD release signal VALID Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode HOLD HALT HOLD release signal and oscillation stable time Figure 4 Oscillation stabilizing time No.6712-22/24 LC87F72C8A VDD (Note) Select CRES and RRES value to assure that at least 200µs reset time is generated after the VDD becomes higher than the minimum operating voltage. RRES RES CRES Figure 5 Reset circuit SIOCLK DATAIN DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transmission period (only SIO0) tSCK tSCKL tSCKH SIOCLK tsDI thDI DATAIN tdDO DATAOUT tSCKLA tSCKHA Data RAM transmission period (only SIO0) SIOCLK tsDI thDI DATAIN tdDO DATAOUT Figure 6 Serial input / output wave form No.6712-23/24 LC87F72C8A tPIL tPIH Figure 7 Pulse input timing VDD SW : ON/OFF(programmable) 4R SW : ON(VLCD=VDD) VLCD 2R 2/3VLCD R 1/2VLCD R 1/3VLCD 2R GND Figure 8 LCD bias resistor PS No.6712-24/24