www.fairchildsemi.com KA9260D 5-Channel Motor Driver Features Description • • • • • • The KA9260D is a monolithic integrated circuit, suitable for 5-ch motor driver which drives focus actuator, tracking actuator, sled motor, spindle motor and loading motor of CD system. 1 phase, full-wave, linear DC motor driver Built-in TSD (Thermal shutdown) circuit Built-in 5V regulator (With an external PNP transistor) Built-in mute circuit Built-in loading motor speed control circuit Wide operating supply voltage range: 6V~13.2V 28-SSOPH-375 Typical Applications • • • • Ordering Information Compact disk player (CDP) Video compact disk player (VCD) Automotive compact disk player (CDP) Other compact disk media Device Package Operating Temp. KA9260CD 28-SSOPH-375 −25°C ~ +75°C KA9260CDTF 28-SSOPH-375 −25°C ~ +75°C Rev. 1.0.1 February. 2000. ©2000 Fairchild Semiconductor International 1 1 2 3 4 5 6 7 DO1.1 DO1.2 DI1.1 DI1.2 REB REO MUTE GND3 DO4.2 DO4.2 DI4.2 DI4.1 VREF VCC2 28 27 26 25 24 23 22 2 LD CTL DI3 DO3.2 DO3.1 DO5.2 DO5.1 20 19 18 17 16 15 8 9 10 11 12 13 14 DI2 DO2.1 DO2.2 GND2 DI5.2 FIN (GND) 21 DI5.1 KA9260D VCC1 FIN (GND) GND1 KA9260D Pin Assignments KA9260D Pin Definitions Pin Number Pin Name I/O Pin Function Description 1 DO1.1 O Focus output 1 (−) 2 DO1.2 O Focus output 2 (+) 3 DI1.1 I Focus input 1 4 DI1.2 I Focus input 2 (Adjustable) 5 REB O Regulator base 6 REO O Regulator output, 5V 7 MUTE I Mute 8 GND1 - Ground 1 9 DI5.1 I Loading input 1 10 DI2 I Spindle input 2 11 DO2.1 O Spindle output (+) 12 DO2.2 O Spindle output (−) 13 GND2 - Ground 2 14 DI5.2 I Loading input 2 15 DO5.1 O Loading output (+) 16 DO5.2 O Loading output (−) 17 DO3.1 O Sled output (−) 18 DO3.2 O Sled output (+) 19 DI3 I Sled input 20 LD CTL I Loading motor speed control 21 VCC1 - Supply voltage 1 22 VCC2 - Supply voltage 2 23 VREF I 2.5V bias 24 DI4.1 I Tracking input 1 (Adjustable) 25 DI4.2 I Tracking input 2 26 DO4.1 O Tracking output 1 (+) 27 DO4.2 O Tracking output 2 (−) 28 GND3 - Ground 3 3 KA9260D 22 DO5.1 VCC2 23 DO5.2 VREF 24 DO3.1 DI4.1 25 DO3.2 DI4.2 26 DI3 DO4.1 27 LD CTL DO4.2 28 FIN (GND) VCC1 GND3 Internal Block Diagram 21 20 19 18 17 16 15 10k + + + 10k 10k − − Level shift + Level shift TSD − − + + + − − − Level shift 10k Mute + 10k 10k 50k + − − − + Regulator 10k Level shift + COMP 2.5V − Level shift + − 50k DO1.2 DI1.1 DI1.2 REB REO MUTE FIN (GND) 4 8 9 10 11 12 13 14 DI5.2 7 GND2 6 DO2.2 5 DO2.1 4 DI2 3 DI5.1 2 GND1 1 DO1.1 10k KA9260D Equivalent Circuits Driver input (Except for loading motor driver) Driver output 10k 2.5V 1 2 11 12 15 16 17 18 27 26 10k 20k 3 10 4 19 25 24 0.58k VREF1 Loading motor driver input Loading motor speed control input 14 9 50k 50k 50k 50k 50k 50k 50k 50k 50k 50k 50k 50k 50k 20 50k Mute input Bias input 50k 50k 23 7 50k Drive input 2.5V 19 10 5 KA9260D Absolute Maximum Ratings (Ta= 25°°C) Parameter Symbol Value Unit Maximum supply voltage VCC MAX 18 V Power dissipation 1.7 PD note W Operating temperature TOPR −25 ~ +75 °C Storage temperature TSTG −55 ~ +150 °C Maximum current output IOMAX 1 A NOTE: 1. When mounted on 76mm × 114mm × 1.57mm PCB (Phenolic resin material). 2. Power dissipation reduces 13.6mW / °C for using above Ta=25°C. 3. Do not exceed Pd and SOA (Safe Operating Area). Power Dissipation Curve Pd (mW) 3,000 2,000 1,000 0 0 25 50 75 100 125 150 175 Ambient temperature, Ta [°C] Recommended Operating Condition (Ta= 25°°C) Parameter Operating supply voltage Symbol Value Unit VCC 6 ~ 13.2 V 6 KA9260D Electrical Characteristics (Ta=25°C, VCC=8V, RL=8Ω, f=1kHz, unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Units Quiescent circuit current ICCQ Under no-load 7 10 13 mA Mute-on current IMUTE Pin 7=GND - 4 7 mA Mute-on voltage VMON - 0 - 0.5 V Mute-off voltage VMOFF - 2 - - V REGULATOR Output voltage VREG IL=100mA 4.7 5.0 5.3 V Load regulation ∆VRL3 IL=0→200mA −50 0 50 mV Line regulation ∆VCC VCC=6→13V, IL=100mA −20 0 80 mV DRIVER (Except for loading motor driver) Input offset voltage Output offset voltage 1 VIO - −15 - 15 mV VOO1 - −40 - 40 mV 0.25 0.4 - A Maximum sink current 1 ISINK1 RL=8Ω→GND 0.25 0.4 - A Maximum output voltage 1 VOM1 VIN=0.7V 2.5 3.3 - V Maximum output voltage 2 VOM2 VIN=7V - −4.5 −3.7 V Closed-loop voltage gain 1 Closed-loop voltage gain 2 AVF1 AVF2 VIN=0.1VRMS VIN=1VRMS, RIN=10kΩ 5 5 6.5 6.5 8 8 dB dB Ripple rejection ratio RR VIN=0.1VRMS, f=120Hz 40 60 - dB Slew rate SR 120Hz, VIN=1VRMS, Square wave 1 2 - V / µs Maximum source current 1 ISOURCE1 RL=8Ω→VCC LOADING MOTOR DRIVER (Unless otherwise specified, VCTL=open) Output voltage 1 VO1 VPIN9=5V, VPIN14=0V, RL=45Ω 2.5 3.1 3.8 V VO2 VPIN9=0V, VPIN14=5V, RL=45Ω 2.5 3.1 3.8 V Output voltage regulation 1 (CTL) VOCTL1 VCTL=3.5→4.5V, VPIN9=5V VPIN14=0V, RL=45Ω 0.5 1.0 1.5 V Output voltage regulation 2 (CTL) VOCTL2 VCTL=3.5→4.5V, VPIN9=0V VPIN14=5V, RL=45Ω 0.5 1.0 1.5 V Load regulation 1 ∆VRL1 IL=100→400mA, VPIN9=5V, VPIN14=0V - 300 700 mV Load regulation 2 ∆VRL2 IL=100→400mA, VPIN9=0V, VPIN14=5V - 300 700 mV Output offset voltage 2 VOO2 VPIN9=5V, VPIN14=5V −40 - 40 mV Output offset voltage 3 VOO3 VPIN9=0V, VPIN14=0V −40 - 40 mV Output voltage 2 7 KA9260D Application Information 1. MUTE Pin #7 Mute circuit High Turn-off Low Turn-on Output driver bias 7 • When the mute pin #7 is open or the voltage of the mute pin #7 is below 0.5V, the mute circuit is activated so that the output circuit will be muted. • When the voltage of the mute pin is above 2V, the mute circuit is stopped and the output circuit is operated normally. • If the chip temperature rises above 175°C, then the TSD (Thermal Shutdown) circuit is activated and the output circuit is muted. 2. TSD (THERMAL SHUTDOWN) VREF BG Output driver bias R11 Q11 R12 • The VREF BG is the output voltage of the band-gap-referenced biasing circuit and acts as the input voltage of the TSD circuit. • The base-emitter voltage of the TR,Q11 is designed to turn-on at below voltage. VBE = VREF BG × R12 / (R11 + R12) = 400mV • When the chip temperature rises up to 175°C, then the turn-on voltage of the Q11 would drop down to 400mV. Hence, the Q11 would turn on so the output circuit will be muted. 3. REGULATOR 5 I VREF BG D1 KSB772 − 6 + R2 VOUT (5V) + R1 R3 D2 8 CE 100µF KA9260D • The VREF BG is the output voltage of the band-gap-referenced biasing circuit and is the reference voltage of the regulator. • The external circuit is composed of the transistor, KSB772 and a capacitor, 100µF, and the capacitor is used as a ripple eliminator and should have a good temperature characteristics. • The output voltage, VOUT is decided as follows. VOUT = VREF BG × 2 = 2.5 × 2 = 5V (R2 = R3) where, the VREF BG = VD1 + VD2 + (I × R1) R2=R3 4. LOADING MOTOR DRIVER 20 I +∆V + + 14 − − R COMP 9 Buffer Q1 −∆V +∆V 15 I −∆V Q2 M VREF1 + 16 Q3 Buffer Q4 − R VREF1 • The input voltages of (5V and 0V) or (0V and 5V) pairs are applied to the input pin #9 and #14 respectively. • When the input voltages are applied to the input pin #9 and #14, then the output of the comparator depends on the input voltage status. • As shown in the above diagram, the difference ∆V, [VREF1 + (I × R)] - [VREF1 -(I × R)], is applied to the both terminals of the motor. The direction of the motor is decided by the voltage difference, +∆V and −∆V. • The output characteristics is as follows, - If pin # 9=5V and #14=0V, then pin # 15=+∆V and #16= −∆V, hence the motor turn in forward direction. - If pin # 9=0V and #14=5V, then pin # 15= −∆V and #16=+∆V, hence the motor turn in reverse direction. - If pin # 9=5V and #14=5V, then ∆V=0V, hence the motor stop. - If pin # 9=0V and #14=0V, then ∆V=0V, hence the motor stop. • When the rotation speed control of the loading motor is desired, refer to the circuit below. 5. LOADING MOTOR SPEED CONTROL VCC VCC (8V) 50k VCC VCC (8V) 50k R 20 R 20 4V 4V 50k 50k D • If the torque of the loading motor is too low when it is used with the pin #20 OPEN, then it should be used as in the above diagram. • The desired torque could be obtained by selecting the appropriate resistor R as shown in the left diagram. • If it is necessary, the zener diode can be used as in the right diagram. • The maximum torque is obtained when the applied voltage at pin #20 is about 6.8V (at VCC=8V). 9 KA9260D 6. DRIVER (EXCEPT FOR LOADING MOTOR DRIVER) VREF (2.5V) + − 3 −∆I AMP Level shift + Buffer − Q1 10k 10 19 24 10k +∆I 100k +∆V Q2 M 19 25 4 −∆V 10 + Q3 Buffer − 1 2 11 12 17 18 27 26 Q4 • The voltage, VREF, is the reference voltage given by the bias voltage of the pin #23. • The input signal through the pin #3 is amplified by 10k/10k times and then fed to the level shift. • The level shift produces the current due to the difference between the input signal and the arbitrary reference signal. The current produced as +∆I and −∆I is fed into the driver buffer. • Driver buffer operates the power TR of the output stage according to the state of the input signal. • The output stage is the BTL driver and the motor is rotating in forward direction by operating TR Q1 and TR Q4. On the other hand, if TR Q2 and TR Q3 is operating, the motor is rotating in reverse direction. • When the input voltage through the pin #3 is below the VREF, then the direction of the motor in forward direction. • When the input voltage through the pin #3 is above the VREF, then the direction of the motor in reverse direction. 7. When the bias voltage of the pin #23 is below 1.4V, then the output circuit is muted. Hence for the normal operation, the bias voltage should be used in 1.6V~6.5V. 8. Connect a by-pass capacitor, 0.1µ µF between the supply voltage source. VCC2 22 VCC1 21 104 9. Radiation fin is connecting to the internal GND of the package. Connect the fin to the external GND. 10 KA9260D Typical Performance Characteristics Vcc vs. Imute 16.00 8.00 14.00 7.00 12.00 6.00 Imute[mA] Icc[mA] Vcc vs. Icc 10.00 8.00 6.00 5.00 4.00 3.00 2.00 4.00 2.00 1.00 pin23=2.5 pin23=2.5 0.00 0.00 4 6 8 10 12 14 16 18 4 20 6 8 10 12 14 16 18 20 Vcc[V] Vcc[V] Vcc vs. Isink Vcc vs. Avf 1000 7.5 900 7.0 Avf[mA] Isink[mA] 800 700 600 500 6.0 pin23=2.5 RL=8Ω 5.5 pin23=2.5 RL=8Ω 400 6.5 5.0 300 4 6 8 10 12 14 4 16 6 8 Vcc[V] Vcc vs. Vom 12 14 16 Vcc vs. Vreg 4.5 6.0 5.5 Vreg[mA] 4.0 Vom[mA] 10 Vcc[V] 3.5 3.0 2.5 5.0 4.5 4.0 pin23=2.5 RL=8Ω 3.5 pin23=2.5 3.0 2.0 4 6 8 10 12 14 3 16 5 7 9 11 Vcc[V] Vcc[V] 11 13 15 KA9260D Typical Performance Characteristics (Continued) Frequency vs. Avf 7.0 Avf[dB] 6.0 5.0 4.0 3.0 2.0 1 100 10000 1000000 Frequency [Hz] 12 KA9260D Test Circuits SW13 3 2 8Ω 1 SW12 VCC 8Ω 3 SW14 2 8Ω 1 IL 3 SW20 SW10 3 8Ω 1 VCC VCC 2 8Ω SW19 1 ~ VCC SLED CTL 100µF Ripple ~ SW9 ~ VCC + 8Ω 3 2 TRACKING SW21 3 2 + 2 1 1 SW18 8Ω 1 10µF 2 + 45Ω 2 + 10µF 3 20Ω SW17 3 1 SW16 SW15 27 26 25 24 23 8Ω 1 IL VCC 10kΩ 28 3 2 2.5V VCC GND3 DO4.2 DO4.1 DI4.2 DI4.1 SW11 22 21 VREF VCC2 20 19 18 17 16 15 VCC1 LD ctl DI3 DO3.2 DO3.1 DO5.2 DO5.1 GND DO2.1 DO2.2 GND2 DI5.2 KA9260D DO1.1 DO1.2 DI1.1 DI1.2 REB 1 2 3 4 6 MUTE 7 9 10 11 12 13 14 VCC 10kΩ SW4 1 SW1 2 Mute 3 KSB772 1 8Ω 3 + 2 8Ω VCC Spindle Focus SW2 3 Loading reverse 8Ω VCC ~ 100µF 1 2 8Ω + 2 Loading forwaed IL ~ SW3 SW7 3 SW5 + 1 DI5.1 DI2 8 VCC VCC 1 REO 5 SW6 SW8 1 2 2 3 8Ω 8Ω 13 3 KA9260D Application Circuits SERVO PRE-AMP FOUCS TRACKING BIAS CONTROLLER SLED SPINDLE TRACKING ACTUATOR CONTROL FORWARD SLED MOTOR VCC REVERSE LOADING MOTOR 102 28 27 26 25 24 GND3 DO4.2 DO4.1 DI4.2 23 DI4.1 22 21 VREF VCC2 20 VCC1 LD ctl 19 18 17 16 15 DI3 DO3.2 DO3.1 DO5.2 DO5.1 KA9260D DO1.1 DO1.2 DI1.1 DI1.2 1 2 3 4 REB REO 5 6 MUTE 7 GND DI5.1 DI2 8 9 10 DO2.1 DO2.2 GND2 DI5.2 11 12 VCC KSB772 FOCUS ACTUATOR 100µF 5V out + MUTE Low: ON High: OFF 14 SPINDLE MOTOR 13 14 KA9260D DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 12/1/00 0.0m 001 Stock#DSxxxxxxxx 2000 Fairchild Semiconductor International