SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination. Regulates while sourcing or sinking 1.5A AVCC range is from 2.5V to 5V Reference output Minimum number of external components Accurate internal voltage divider SOIC8-EDP package.Pb-free,Halogen free, and RoHS/ WEEE compliant The SC2595 can source and sink 1.5A current at the output VTT while maintaining excellent load regulation. Applications VTT is designed to track the VREF voltage with a tight tolerance over the entire current range while preventing shoot through on the output stage. DDR memory termination High speed data line termination PC motherboards Graphics boards Disk drives CD-ROM drives A VSENSE pin is incorporated to provide excellent load regulation, along with a buffered reference voltage. The SC2595 incorporates a disable function built into the AVCC pin to tri-state the output during Suspend To Ram (STR) states. (Multiple patents pending.) Typical Application Circuit VDD SC2595 1 2 3 VREF September 24, 2009 4 NC VTT GND PVCC VSENSE AVCC VREF VDDQ 1 8 VTT 7 6 5 www.semtech.com SC2595 POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. P ar am et er S y m b ol M ax i m u m Units PVCC, AVCC, VDDQ to GN D VCC -0.3 to +6.0 V Thermal Resistance Junction to Case SOIC8-EDP θJC 5.5 °C/W Thermal Resistance Junction to Ambient SOIC8-EDP θJA 36.5 Op erating Temp erature Range TA -40 to +105 °C Op erating Junction Temp erature Range TJ -40 to +150 °C Storage Temp erature Range TSTG -65 to +150 °C Peak IR Reflow Temp erature 10 - 40s T LE A D 240 °C Peak IR Reflow Temp erature 10 - 40s T LE A D 260 °C ESD Rating (Human Body Model) ESD 2 KV °C/W Operating Range P ar am et er S y m b ol M ax i m u m Units TJ -40 to +150 °C AVCC to GN D AVCC 2.3 to 5.5 V PVCC to GN D PVCC 2.3 to AVCC V Junction Temp erature Range Electrical Characteristics Specifications with standard typeface are for TJ = 25oC and limits in boldface type apply over the full Operating Temperature Range (TJ = -40oC to +150oC). Unless otherwise specified, AVCC = PVCC = 2.5V, VDDQ = 2.5V. P ar am et er Reference Voltage Load Regulation (1) V TT Outp ut Voltage Offset Quiescent Current S y m b ol Te s t C o n d i t i o n s Min Ty p M ax Units V REF IREF_OUT = 0mA V DDQ/2 - 40mV 1.25 V DDQ/2 + 40mV V REGLOAD ILOAD : 0 to +1.5A ILOAD : 0 to -1.5A V OSV TT IOUT=0A , V TT- V REF IQ ILOAD = 0A AV CC Enab le Threshold V DDQ Inp ut Imp edance ZVDDQ -0.5 +0.5 -20 0 % +20 mV 400 μA 2.1 V 100 kΩ Note: (1) For Load Regulation, use a 10ms current pulse width when measuring VTT. ©2009 Semtech Corp. 2 www.semtech.com SC2595 POWER MANAGEMENT Pin Configuration Ordering Information TOP VIEW NC 1 8 VTT GND 2 7 PVCC VSENSE 3 6 AVCC VREF 4 5 VDDQ Par t Number Package Temp. Range (T A ) SC2595STRT(1)(2) SOIC8-EDP -40 to +105OC SC2595EVB Evaluation Board Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for SOIC8-EDP package. (2) Pb-free,Halogen free, and RoHS and WEEE compliant. (SOIC8-EDP) ©2009 Semtech Corp. 3 www.semtech.com SC2595 POWER MANAGEMENT Pin Descriptions PRELIMINARY S O I C- 8L E DP Pin # P i n N am e 1 NC 2 GN D 3 V SEN SE V SENSE is a feedb ack p in. V TT p lane is always a narrow and long strip p lane in most m o t h e r b o ar d ap p l i cat i o n s. T h i s l o n g st r i p p l an e w i l l cau se a l ar g e t r ace inductance and trace resistance. Consider the load transient condition; a fast load current going through V TT strip p lane can create voltage sp ikes on the V TT p lane. The load current can also cause a DC voltage drop on the V TT p lane. It is recommen d ed th at V SEN SE sh ou l d b e con n ected to th e cen ter of V TT p l an e to i mp rove th e l oad regu l ati on an d th e n oi se i mmu n i ty. In case th at on e can 't connect the V SENSE p in to the center of the V TT p lane, one should connect it to the SC2595 V TT p in directly. A longer trace of V SENSE may p ick up noise and cause the error of load regulation; hence the longer trace must b e avoided. A 10nF to 100nF ceramic cap acitor close to the V SENSE p in is req uired to avoid oscillation during transient condition. 4 V REF V REF is an outp ut p in, which p rovides the b uffered outp ut of the internal reference voltage. System designer can use the V REF outp ut voltage for N or thb ridge chip set an d memory. B ecau se th ese i n p u t p i n s are ty p i cal l y h i gh i mp ed an ce, th ere should b e a small amount of current drawn from the VREF p in [figure 9, 10]. To imp rove the noise immunity, a ceramic cap acitor (10nF - 100nF) should b e added from the V REF p in to ground with shor t distance. 5 V DDQ(2) The V DDQ p in is an inp ut for creating internal reference voltage to regulate V TT. The V DDQ voltage is connected to internal 100Kohm resistor divider. The central tap of resi stor d i vi d er ( V DDQ/2) i s con n ected to th e i n tern al vol tage b u ffer, w h i ch outp ut is connected to V REF p in and the non-inver ting inp ut of the error amp lifier as the reference voltage. With the feedb ack loop closed, the V TT outp ut voltage will always track the V DDQ/2 p recisely. It is recommended to use 5.1 ohm + a 1uF ceramic cap acitor for V DDQ p in's filter to increase the noise immunity. 6 AV CC (2) The AV CC p in is used to sup p ly all of the internal control circuitry. AV CC voltage h as to b e greater th an i ts U V LO th resh ol d vol tage ( 2.1V ty p i cal ) to al l ow th e SC2595 b e in normal op eration. If AV CC voltage is lower than the UV LO threshold voltage, the V TT outp ut voltage will remain at 0V. 7 PV CC (2) The PV CC p in p rovides the rail voltage from where the V TT p in draws load current. There is a limitation b etween AV CC and PV CC. The PV CC voltage must b e less or eq ual to AV CC voltage to ensure the correct outp ut voltage regulation. The V TT source current cap ab ility is dep endent on PV CC voltage. Higher the voltage on PV CC, higher the source current; however, it will cause more p ower loss and higher temp erature rise [figure 5, 11, 12]. 8 V TT The V TT p in is the outp ut of SC2595. It can sink and source 1.5A continuous cu rren t an d 3A p eak cu rren t w h i l e k eep i n g ex cel l en t l oad reg u l at i on . I t i s recommen d ed th at on e sh ou l d u se at l east 220u F l ow E SR cap aci tors ( E SR sh ou l d b e l ow er t h an 250m oh m) an d 10u F cerami c cap aci t ors, w h i ch are uniformly sp read on the VTT strip p lane to reduce the voltage sp ike under load transient condition. Thermal Pad ©2009 Semtech Corp. P i n Fu n c t i o n N o internal connection. (1) Ground. Thermal p ad should b e connected to GN D. 4 www.semtech.com SC2595 POWER MANAGEMENT Notes: (1) Can be used for vias. (2) Power up of AVCC, PVCC and VDDQ supplies. (a) The preferred mode of operation is when the AVCC, PVCC and VDDQ pins are tied together to a single supply. (b) If and when AVCC, PVCC pins are tied to a supply separate to that of the VDDQ supply pin; then the VDDQ supply should lead AVCC, PVCC supply or the VDDQ supply and the AVCC, PVCC supply should rise simultaneously. (c) If the AVCC, PVCC and VDDQ supply pins are connected in a way such that, AVCC, PVCC supplies precedes VDDQ supply; then VTT output precedes VDDQ. This can cause the SDRAM device to latch-up, which may cause permanent damage to the SDRAM. Block Diagram AVCC PVCC UVLO VDDQ OUT + + Driver Circuit OUT - VTT VREF GND VSENSE NC ©2009 Semtech Corp. 5 www.semtech.com SC2595 POWER MANAGEMENT Application Information PRELIMINARY Application_2: Lower Power Loss Configuration f or SS TL -2 SSTL TL-2 Overview Double Data Rate (DDR) SDRAM was defined by JEDEC 1997. Its clock speed is the same as previous SDRAM but data transfers speed is twice than previous SDRAM. By now, the requirement voltage range is changed from 3.3V to 2.5V; the power dissipation is smaller than SDRAM. For above reasons, it is very popular and widely used in M/B, N/B, Video-cards, CD ROM drives, Disk drives. If power loss is a major concern, separated the PVCC form the AVCC and the VDDQ will be a good choice. The PVCC can operate at lower voltage (1.8V to 2.5V). If 2.5V voltage is applied on AVCC and the VDDQ, but the source current is lower due to the lower operating voltage applied on the PVCC. Please find the relative test result in Figures 5, 11 and 12. Regarding the DDR power management solution, there are two topologies can be selected for system designers. One is switching mode regulator that has bigger sink/ source current capability, but the cost is higher and the board space needed is bigger. Another solution is linear mode regulator, which costs less, and needs the less board space. For two DIMM motherboards, system designers usually choose the linear mode for DDR power management solution. Applications Typical Application Cir cuits & W a v ef orms Circuits Wa eforms SC2595 1 2 3 4 Csense Cref 2.2uF 10nF NC VTT GND PVCC VSENSE AVCC VREF VDDQ 8 7 6 VTT 1.8V to 2.5V 2.5V VDD 1.25V Vin 5 R2 R Cin2 Cin1 Cout1 Cin2 1uF 68uF 220uF 10uF Cddq 1uF Figure 2: Lower power loss for SSTL-2 application Two different application circuits are shown below in Figure 1 to Figure 2. Each circuit is designed for specific condition. More details are described below. See Note 1. Below for recommended power up sequencing. Notes: (1) Power up of AVCC, PVCC and VDDQ supplies. (a) The preferred mode of operation is when the AVCC, PVCC and VDDQ pins are tied together to a single supply. (b) If and when AVCC, PVCC pins are tied to a supply separate to that of the VDDQ supply pin; then the VDDQ supply should lead AVCC, PVCC supply or the VDDQ supply and the AVCC, PVCC supply should rise simultaneously. (c) If the AVCC, PVCC and VDDQ supply pins are con nected in a way such that, AVCC, PVCC supplies precedes VDDQ supply; then VTT output precedes VDDQ. This can cause the SDRAM device to latchup, which may cause permanent damage to the SDRAM. Application_1: Standar d SS TL -2 Application Standard SSTL TL-2 The AVCC pins, the PVCC pin, and the VDDQ pin can be tied together for SSTL-2 application. It only needs a 2.5V power rail for normal operation. System designer can save the PCB space and reduce the cost. Please refer to figures 3 to 4 for test waveforms. SC2595 1 2 3 4 NC GND VTT PVCC VSENSE AVCC VREF VDDQ 8 7 VDD 6 5 2.5V R1 5.1 Csence Cref 2.2uF 10nF VTT 1.25V Cin1 Cout1 Cout2 68uF 220uF 10uF Cin2 1uF Figure 1: Standard SSTL-2 application ©2009 Semtech Corp. 6 www.semtech.com SC2595 POWER MANAGEMENT Application Information (Cont.) Layout guidelines 1)The SC2595 has a SOIC8-EDP package. It can improve the thermal impedance (θJC) significantly. A suitable thermal pad should be added when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB ground layer. This will improve the thermal performance . 2)To increase the noise immunity, a ceramic capacitor of 10nf to 100nf is required to decouple the VREF pin with the shortest connection trace, also A 10nF to 100nF ceramic capacitor close to the VSENSE pin is required to avoid oscillation during transient condition. 3)To reduce the noise on the input power rail for standard SSTL-2 application, a 68μF low ESR capacitor and a 1μF ceramic capacitor have to be used on the input power rail with shortest possible connection. 4)For lower power loss SSTL-2 application, a 220μF AL. capacitor (ESR should be lower than 250m ohm) and a 10μF ceramic has to be added on the PVCC pin and a 1μF ceramic capacitor +5.1 ohm filter has to be added on the VDDQ pin with shortest possible connection. 5)VTT output copper plane should be as large as possible. 6)VSENSE trace should be as short as possible. ©2009 Semtech Corp. 7 www.semtech.com SC2595 POWER MANAGEMENT Test Waveforms PRELIMINARY Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V Cout1=220uF, Cout2=10uF, Sink 2A. Test condition: Avcc=PVcc=VDDQ=2.5V,VTT=1.25V Cout1=220uF, Cout2=10uF, Source 2A. VDDQ AVcc PVcc VDDQ AVcc PVcc VTT VTT VREF VREF Figure 3 Figure 4 Typical Characteristics AVcc vs IQ AVCC=VDDQ=2.5V 600 3.00 550 2.75 500 450 Quiescent current(uA) OUTPUT CURRENT(A) 2.50 2.25 MAX SOURCE CURRENT 2.00 1.75 400 350 VDDQ =2.5V VDDQ =1.8V 300 250 200 150 1.50 100 1.25 50 0 2.5 1.00 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 3.5 4.0 4.5 5.0 5.5 6.0 AVcc(V) PVCC(V) Figure 6 Figure 5 ©2009 Semtech Corp. 3.0 8 www.semtech.com SC2595 POWER MANAGEMENT Typical Characteristics (Cont.) Temp vs UVLO Quiescent Current(AVCC= 2.5V) 2.00 800 1.99 700 1.98 1.97 2.5V 500 Voltage(V) Current(uA) 600 1.8V 1.96 UVLO (Ty pical) 1.95 1.94 400 1.93 1.92 300 1.91 200 0 20 40 60 1.90 80 100 120 140 20 30 40 50 60 70 80 90 100 110 Temperature (℃) Temperature(℃) Figure 7 Figure 8 VREF_max vs IREF(VDDQ=2.5V) 1.250 1.250 1.245 1.245 1.240 1.240 1.235 1.235 VREF(V) VREF(V) VDDQ=PVCC=AVCC=2.5V 1.230 -40℃ 0℃ 25℃ 1.230 75℃ 1.225 1.225 150℃ 1.220 1.220 1.215 1.215 1.210 1.210 0 0 100 200 300 400 500 600 700 800 900 100 200 300 400 500 600 700 800 900 IREF(uA) IREF(uA) Figure 10 Figure 9 ©2009 Semtech Corp. 9 www.semtech.com SC2595 POWER MANAGEMENT Typical Characteristics (Cont.) PRELIMINARY VDDQ=1.8V VDDQ=2.5V 6.5 6.0 6.0 5.5 5.5 5.0 4.5 4.5 Current(A) Current(A) 5.0 MAX SOURCE CURRENT 4.0 4.0 MAX SOURCE CURRENT 3.5 3.5 3.0 3.0 2.5 2.5 2.0 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVCC=PVCC(V) AVCC=PVCC(V) Figure 11 Figure 12 AVCC=PVCC=VDDQ=2.5V 140 120 Temperature(℃ ) 100 80 SOURCE 60 SINK 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 DC CURRENT (A) Figure 13 ©2009 Semtech Corp. 10 www.semtech.com SC2595 POWER MANAGEMENT Outline Drawing - SOIC8-EDP ©2009 Semtech Corp. 11 www.semtech.com SC2595 POWER MANAGEMENT PRELIMINARY Land Pattern - SOIC8-EDP Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 ©2009 Semtech Corp. 12 www.semtech.com