TDA7449 TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR 1 ■ FEATURES Figure 1. Package INPUT MULTIPLEXER – 2 STEREO INPUTS – SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ■ ONE STEREO OUTPUT ■ TREBLE, AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS ■ TWO SPEAKER ATTENUATORS: – TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY – INDEPENDENT MUTE FUNCTION 2 SO20 Table 1. Order Codes ■ ■ DIP20 ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7449 is a volume tone (bass and treble) balance (Left/Right) processor for quality audio Part Number Package TDA7449 DIP20 TDA7449D SO20 applications in TV systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. Figure 2. Block Diagram MUXOUTL 10 L-IN1 TREBLE(L) 16 BIN(L) BOUT(L) 15 8 14 RB 100K L-IN2 9 100K R-IN1 G VOLUME SPKR ATT LEFT BASS I2CBUS DECODER + LATCHES 20 18 100K R-IN2 6 100K 5 19 0/30dB 2dB STEP 7 TREBLE G VOLUME TREBLE SPKR ATT RIGHT BASS 4 LOUT SCL SDA DIG_GND ROUT VREF 2 SUPPLY INPUT MULTIPLEXER + GAIN RB 11 MUXOUTR June 2004 17 TREBLE(R) 12 13 BIN(R) BOUT(R) 3 VS AGND 1 CREF D98AU847A REV. 4 1/19 TDA7449 Table 2. Absolute Maximum Ratings Symbol Parameter VS Operating Supply Voltage Tamb Operating Ambient Temperature Tstg Storage Temperature Range Value Unit 10.5 V 0 to 70 °C -55 to 150 °C Figure 3. Pin Connection CREF 1 20 SDA VS 2 19 SCL PGND 3 18 DIG_GND ROUT 4 17 TREBLE(R) LOUT 5 16 TREBLE(L) R_IN2 6 15 BIN(L) R_IN1 7 14 BOUT(L) L_IN1 8 13 BOUT(R) L_IN2 9 12 BIN(R) 10 11 MUXOUT(R) MUXOUT(L) D98AU848 Table 3. Thermal Data Symbol Rth j-pin Parameter Thermal Resistance Junction- pins Value Unit 85 °C/W Table 4. Quick Reference Data Symbol Parameter Min. Typ. Max. Unit 9 10.2 V VS Supply Voltage 6 VCL Max Input Signal Handling 2 THD Total Harmonic Distortion V = 0.1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio Vout = 1Vrms (mode = OFF) 106 dB SC Channel Separation f = 1KHz 90 dB Input Gain (2dB step) 0.1 % 0 30 dB Volume Control (1dB step) -47 0 dB Treble Control (2dB step) -14 14 dB Bass Control (2dB step) -14 14 dB Balance Control 1dB step -79 0 dB Mute Attenuation 2/19 VRMS 100 dB TDA7449 Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS Supply Voltage IS Supply Current SVR 6 Ripple Rejection 60 9 10.2 V 7 mA 90 dB 100 KΩ INPUT STAGE RIN Input Resistance VCL Clipping Level THD = 0.3% 2 2.5 Vrms SIN Input Separation The selected input is grounded through a 2.2µ capacitor 80 100 dB -1 0 Ginmin Minimum Input Gain Ginman Maximum Input Gain 30 dB Step Resolution 2 dB Gstep 1 dB VOLUME CONTROL Control Range 45 47 49 dB AVMAX Max. Attenuation 45 47 49 dB ASTEP Step Resolution 0.5 1 1.5 dB AV = 0 to -24dB -1.0 0 1.0 dB AV = -24 to -47dB -1.5 0 1.5 dB AV = 0 to -24dB 0 1 dB AV = -24 to -47dB 0 2 dB adjacent attenuation steps 0 3 mV CRANGE EA ET VDC Attenuation Set Error Tracking Error DC Step from 0dB to AV max Amute Mute Attenuation 0.5 mV 80 100 dB +12.0 +14.0 +16.0 dB 1 2 3 dB 18.75 25 31.25 KΩ +13.0 +14.0 +15.0 dB 1 2 3 dB BASS CONTROL (1) Gb Control Range BSTEP Step Resolution RB Max. Boost/cut Internal Feedback Resistance TREBLE CONTROL (1) Gt Control Range TSTEP Step Resolution Max. Boost/cut 3/19 TDA7449 Table 5. Electrical Characteristcs (continued) SPEAKER ATTENUATORS CRANGE Control Range SSTEP Step Resolution EA Attenuation Set Error 76 AV = 0 to -20dB AV = -20 to -56dB VDC DC Step Amute Mute Attenuation dB 0.5 1 1.5 dB -1.5 0 1.5 dB -2 0 2 dB 0 3 mV adjacent attenuation steps 80 100 dB 2.1 2.6 VRMS AUDIO OUTPUTS VCLIP Clipping Level d = 0.3% RL Output Load Resistance 2 RO Output Impedance 10 VDC DC Voltage Level KΩ 40 70 3.8 W V GENERAL ENO Et Output Noise All gains = 0dB; BW = 20Hz to 20KHz flat 5 15 µV Total Tracking Error AV = 0 to -24dB 0 1 dB AV = -24 to -47dB 0 2 dB S/N Signal to Noise Ratio SC Channel Separation Left/Right d Distortion All gains 0dB; VO = 1VRMS ; 80 AV = 0; VI = 1VRMS ; 106 dB 100 dB 0.01 0.08 % 1 V BUS INPUT VIL Input Low Voltage VIH Input High Voltage IIN Input Current VIN = 0.4V VO Output Voltage SDA Acknowledge IO = 1.6mA 3 V -5 0.4 5 µA 0.8 V Note: 1. The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device. 2. BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry. 4/19 TDA7449 Figure 4. P.C.Board (Referred to DIP20 package only) Figure 5. Test Circuit R2 2K C9 5.6nF 150nF J5 IN1L C7 TREBLE(L) MUXOUTL J3 10 RCA 1 2 J4 3 4 5 330nF 16 C8 BIN(L) BOUT(L) 15 14 GND IN2L GND CON3 L-IN1 OUT_L 100K C3 0.47µF L-IN2 RB 8 5 LOUT 9 100K C4 0.47µF G VOLUME TREBLE OUT_ R SPKR ATT LEFT BASS J2 RCA 0/30dB 2dB STEP J1 2 3 4 IN2R GND IN1R GND R-IN2 18 DIG_GND 19 SCL 20 SDA G VOLUME TREBLE BASS SPKR ATT RIGHT C2 0.47µF 4 CON4 1 2 3 J6 4 ROUT 100K SUPPLY MOUTL GND RB 11 MUXOUTR TREBLE(R) MOUTR 13 BOUT(R) C5 2 C13 100nF R3 30 C12 22µF AGND 1 VS 12 17 BIN(R) 3 J10 4 4 7 INPUT MULTIPLEXER + GAIN 2 3 CON4 100K 3 1 2 VREF CON J5 JP1 JUMPER 6 C1 0.47µF R-IN1 I2CBUS DECODER + LATCHES 1 CON4 +9 V IN1R 1 J9 OUT_L GND IN1L J8 OUT_R +V8 1 +9V GND 2 J7 CON2 CREF C6 GND C10 5.6nF 150nF R1 330nF 2K C11 10µF D98AU849A 5/19 TDA7449 3 APLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7449 audioprocessor provides 2 bands tones control. 3.1 Bass, Stages The Bass cell has an internal resistor Ri = 25KΩ typical. Several filter types can be implemented, connecting external components to the Bass IN and OUT pins. The fig.6 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal Fc, the gain Av at max. boost and the filter Q factor are computed as follows: Figure 6. Ri internal IN OUT C1 C2 R2 D95AU313 1 FC = ----------------------------------------------------------------2 ⋅ π ⋅ R1 ⋅ R2 ⋅ C 1 ⋅ C2 R2C 2 + R2C1 + RiC1 AV = -----------------------------------------------------------R2 C1 + R2C2 R 1 ⋅ R2 ⋅ C1 ⋅ C2 Q = -------------------------------------------------R 2C1 + R2C2 Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be: 2 Q ⋅ C1 C2 = -----------------------------2AV – 1 – Q AV – 1 C1 = -----------------------------------------2 ⋅ π ⋅ Fc ⋅ Ri ⋅ Q 2 AV – 1 – Q R2 = ---------------------------------------------------------------------2 ⋅ π ⋅ C1 ⋅ Fc ⋅ ( AV – 1 ) ⋅ Q 3.2 Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and an external capacitor connected between treble pins and ground Typical responses are reported in Figg. 10 to 13. 3.3 CREF The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires faster power ON. 6/19 TDA7449 Figure 7. THD vs. frequency Figure 10. Bass response Figure 8. THD vs. RLOAD Figure 11. Treble response Figure 9. Channel separation vs. frequency 7/19 TDA7449 4 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7449 and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 4.1 Data Validity As shown in fig. 12, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.2 Start and Stop Conditions As shown in fig.13 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 4.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 14). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 4.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 12. Data Validity on the I2CBUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 13. Timing Diagram of I2CBUS SCL I2CBUS SDA START 8/19 D99AU1032 STOP TDA7449 Figure 14. Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START 5 ACKNOWLEDGMENT FROM RECEIVER D99AU1033 SOFTWARE SPECIFICATION 5.1 Interface Protocol The interface protocol comprises: ■ A start condition (S) ■ A chip address byte, containing the TDA7449 address ■ A subaddress bytes ■ A sequence of data (N byte + acknowledge) ■ A stop condition (P) Figure 15. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA 1 to DATA n LSB X X B DATA MSB ACK LSB DATA ACK P D96AU420 ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment 6 EXAMPLES 6.1 No Incremental Bus The TDA7449 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. Figure 16. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA LSB X X 0 D3 D2 D1 D0 ACK MSB LSB DATA ACK P D96AU421 9/19 TDA7449 6.2 Incremental Bus The TDA7449 receive a start conditions, the correct chip address, a subaddress with the B = 1 incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. Figure 17. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA 1 to DATA n LSB X X MSB 1 D3 D2 D1 D0 ACK LSB DATA ACK D96AU422 Table 6. POWER ON RESET CONDITION 7 INPUT SELECTION IN2 INPUT GAIN 28dB VOLUME MUTE BASS 0dB TREBLE 2dB SPEAKER MUTE DATA BYTES Address = 88 HEX (ADDR:OPEN). Table 7. FUNCTION SELECTION: First byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 X X X B 0 0 0 0 INPUT SELECT X X X B 0 0 0 1 INPUT GAIN X X X B 0 0 1 0 VOLUME X X X B 0 0 1 1 NOT ALLOWED X X X B 0 1 0 0 BASS X X X B 0 1 0 1 TREBLE X X X B 0 1 1 0 SPEAKER ATTENUATE "R" X X X B 0 1 1 1 SPEAKER ATTENUATE "L" B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON’T CARE 10/19 P TDA7449 Table 8. INPUT SELECTION MSB LSB INPUT MULTIPLEXER D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 NOT ALLOWED X X X X X X 0 1 NOT ALLOWED X X X X X X 1 0 IN2 X X X X X X 1 1 IN1 Table 9. INPUT GAIN SELECTION MSB D7 D6 D5 D4 LSB INPUT GAIN D3 D2 D1 D0 2dB STEPS 0 0 0 0 0dB 0 0 0 1 2dB 0 0 1 0 4dB 0 0 1 1 6dB 0 1 0 0 8dB 0 1 0 1 10dB 0 1 1 0 12dB 0 1 1 1 14dB 1 0 0 0 16dB 1 0 0 1 18dB 1 0 1 0 20dB 1 0 1 1 22dB 1 1 0 0 24dB 1 1 0 1 26dB 1 1 1 0 28dB 1 1 1 1 30dB GAIN = 0 to 30dB 11/19 TDA7449 Table 10. VOLUME SELECTION MSB D7 D6 0 D5 0 D4 D3 0 0 LSB VOLUME D2 D1 D0 1dB STEPS 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB X 1 1 1 X X X MUTE LSB BASS VOLUME = 0 to 47dB/MUTE Table 11. BASS SELECTION MSB D7 12/19 D6 D5 D4 D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB TDA7449 Table 12. TREBLE SELECTION MSB D7 D6 D5 D4 LSB TREBLE D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB Table 13. SPEAKER ATTENUATE SELECTION MSB D7 D6 D5 D4 D3 LSB SPEAKER ATTENUATION D2 D1 D0 1dB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 -72dB 1 1 1 1 X X X MUTE SPEAKER ATTENUATION = 0 to -79dB/MUTE 13/19 TDA7449 Figure 18. PIN :1 Figure 21. PINS: 10, 11 VS VS VS VS 20µA 20K CREF MUXOUT 20K GND D96AU430 D96AU491 Figure 22. PINS: 12, 15 Figure 19. PINS: 4, 5 VS VS 20µA 24 ROUT LOUT 20µA 25K BIN(L) BIN(R) D98AU850 D96AU434 Figure 20. PINS: 6, 7, 8, 9 Figure 23. PINS: 13, 14, VS VS 20µA 20µA IN 100K VREF 44K D96AU425 BOUT(L) BOUT(R) 14/19 D96AU429 TDA7449 Figure 24. PINS: 16, 17 Figure 26. PIN 20 VS 20µA 20µA SDA TREBLE(L) TREBLE(R) 50K D96AU433 D96AU423 Figure 25. PIN: 19 20µA SCL D96AU424 15/19 TDA7449 Figure 27. DIP20 Mechanical Data & Package Dimensions mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L OUTLINE AND MECHANICAL DATA 3.3 0.130 DIP20 Z 16/19 1.34 0.053 TDA7449 Figure 28. SO20 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO20 0016022 D 17/19 TDA7449 Table 14. Revision History 18/19 Date Revision Description of Changes March 2004 3 Third Issue June 2004 4 Modified the style-sheet in compliance with the last revision of the “Corporate Technical Pubblications Design Guide”. TDA7449 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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