TDA7449L LOW COST DIGITALLY CONTROLLED AUDIO PROCESSOR INPUT MULTIPLEXER - 2 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DIP20 ORDERING NUMBER: TDA7449L DESCRIPTION The TDA7449L is a volume control and balance (Left/Right) processor for quality audio applications in TV systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor net- works and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. BLOCK DIAGRAM MUXOUTL L-IN1 10 8 100K L-IN2 9 100K G VOLUME SPKR ATT LEFT 5 LOUT 19 R-IN1 0/30dB 2dB STEP 7 2 I CBUS DECODER + LATCHES 18 100K R-IN2 20 6 G VOLUME 100K SPKR ATT RIGHT 4 SCL SDA DIG_GND ROUT VREF 2 SUPPLY INPUT MULTIPLEXER + GAIN 11 MUXOUTR April 1999 3 VS AGND 1 CREF D98AU868 1/13 TDA7449L ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value 10.5 V Tamb Operating Ambient Temperature -10 to 85 °C Tstg Storage Temperature Range -55 to 150 °C VS Operating Supply Voltage Unit PIN CONNECTION CREF 1 20 SDA VS 2 19 SCL PGND 3 18 DIG_GND ROUT 4 17 N.C. LOUT 5 16 N.C. R_IN2 6 15 N.C. R_IN1 7 14 N.C. L_IN1 8 13 N.C. L_IN2 9 12 N.C. 10 11 MUXOUT(R) MUXOUT(L) D98AU869 THERMAL DATA Symbol R th j-pin Parameter Thermal Resistance Junction-pins Value Unit 150 °C/W QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. 9 10.2 VS Supply Voltage 6 VCL Max. input signal handling 2 Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio V out = 1Vrms (mode = OFF) 106 SC Channel Separation f = 1KHz 2/13 0.1 % dB 90 dB 0 30 dB 0 dB 0 dB Volume Control (1dB step) -47 Balance Control 1dB step -79 Mute Attenuation V Vrms THD Input Gain in (2dB step) Unit 100 dB TDA7449L ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 6 9 10.2 60 7 90 mA dB THD = 0.3% 2 100 2.5 KΩ Vrms The selected input is grounded through a 2.2µ capacitor 80 100 dB -1 0 30 2 1 dB dB dB 45 45 0.5 47 47 1 49 49 1.5 dB dB dB -1.0 -1.5 0 0 0 1.0 1.5 1 dB dB dB 2 3 80 0 0 0.5 100 dB mV mV dB 0.5 76 1 1.5 dB dB -1.5 -2 0 0 0 1.5 2 3 dB dB mV 80 100 dB 2.1 2.6 VRMS SUPPLY VS Supply Voltage IS SVR Supply Current Ripple Rejection V INPUT STAGE R IN V CL Input Resistance Clipping Level SIN Input Separation Ginmin Ginman Gstep Minimum Input Gain Maximum Input Gain Step Resolution VOLUME CONTROL C RANGE AVMAX ASTEP Control Range Max. Attenuation Step Resolution EA Attenuation Set Error ET Tracking Error VDC DC Step Amute Mute Attenuation AV = 0 to -24dB AV = -24 to -47dB AV = 0 to -24dB AV = -24 to -47dB adjacent attenuation steps from 0dB to AV max SPEAKER ATTENUATORS C RANGE SSTEP Control Range Step Resolution EA Attenuation Set Error VDC DC Step Amute Mute Attenuation AV = 0 to -20dB AV = -20 to -56dB adjacent attenuation steps AUDIO OUTPUTS VCLIP Clipping Level RL RO VDC Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 2 10 KΩ 40 3.8 70 Ω V 5 15 µV 0 0 1 2 dB dB 0.08 dB dB % GENERAL ENO Output Noise Et Total Tracking Error S/N SC d BUS PUT Signal to Noise Ratio Channel Separation Left/Right Distortion All gains = 0dB; BW = 20Hz to 20KHz flat AV = 0 to -24dB AV = -24 to -47dB All gains 0dB; V O = 1VRMS ; 80 AV = 0; VI = 1VRMS ; 106 100 0.01 IN3/13 TDA7449L ELECTRICAL CHARACTERISTICS (continued.) Symbol Parameter Test Condition Min. Typ. Max. Unit 1 V V 5 µA V BUS INPUT V IL VIH IIN Input Low Voltage Input High Voltage Input Current VO Output Voltage SDA Acknowledge 3 -5 VIN = 0.4V IO = 1.6mA 0.4 0.8 TEST CIRCUIT MUXOUTL 10 L-IN1 8 0.47µF L-IN2 100K 9 0.47µF R-IN1 100K R-IN2 0.47µF SPKR ATT LEFT 2 I CBUS DECODER + LATCHES 20 18 100K 6 100K 5 19 0/30dB 2dB STEP 7 0.47µF VOLUME G G VOLUME SPKR ATT RIGHT 4 LOUT SCL SDA DIG_GND ROUT VREF 2 SUPPLY INPUT MULTIPLEXER + GAIN 11 MUXOUTR 3 VS AGND 1 CREF D98AU870 10µF APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. 4/13 The TDA7449L audioprocessor provides 2 bands tones control. CREF The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires faster power ON. TDA7449L Figure 2: THD vs. frequency Figure 3: THD vs. RLOAD Figure 4: Channel separation vs. frequency 5/13 TDA7449L I2C BUS INTERFACE Data transmission from microprocessor to the TDA7449L and vice versa takes place through the 2 wires I 2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS Figure 4: Timing Diagram of I2CBUS Figure 5: Acknowledge on the I2CBUS 6/13 knowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. TDA7449L address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7449L CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA 1 to DATA n LSB X X B DATA MSB ACK LSB DATA ACK P D96AU420 ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment EXAMPLES No Incremental Bus The TDA7449L receives a start condition, the cor- CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 rect chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. 0 0 MSB ACK X DATA LSB X X MSB 0 D3 D2 D1 D0 ACK LSB DATA ACK P D96AU421 Incremental Bus The TDA7449L receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 SUBADDRESS from ”XXX1000” to ”XXX1111” of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. 0 0 MSB ACK X DATA 1 to DATA n LSB X X 1 D3 D2 D1 D0 ACK MSB LSB DATA ACK P D96AU422 7/13 TDA7449L POWER ON RESET CONDITION INPUT SELECTION IN2 INPUT GAIN 28dB VOLUME MUTE SPEAKER MUTE DATA BYTES Address = 88 HEX (ADDR:OPEN). FUNCTION SELECTION: First byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 X X X B 0 0 0 0 INPUT SELECT X X X B 0 0 0 1 INPUT GAIN X X X B 0 0 1 0 VOLUME X X X B 0 0 1 1 NOT USED X X X B 0 1 0 0 NOT USED X X X B 0 1 0 1 NOT USED X X X B 0 1 1 0 SPEAKER ATTENUATE ”R” X X X B 0 1 1 1 SPEAKER ATTENUATE ”L” B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON’T CARE In Incremental Bus Mode, the three ”not used” functions must be addressed in any case. For example to refresh ”Volume = 0dB” and Speaker_R = -40dB”, the following bytes must be sent: SUBADDRESS XXX10010 VOLUME DATA X0000000 NOT USED 1 DATA XXXX1111 NOT USED 2 DATA XXXX1111 NOT USED 3 DATA XXXX1111 SPEAKER_R DATA X0000010 INPUT SELECTION MSB LSB INPUT MULTIPLEXER D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 NOT ALLOWED X X X X X X 0 1 NOT ALLOWED X X X X X X 1 0 IN2 X X X X X X 1 1 IN1 8/13 TDA7449L DATA BYTES (continued) INPUT GAIN SELECTION MSB D7 D6 D5 D4 LSB INPUT GAIN D3 D2 D1 D0 2dB STEPS 0 0 0 0 0dB 0 0 0 1 2dB 0 0 1 0 4dB 0 0 1 1 6dB 0 1 0 0 8dB 0 1 0 1 10dB 0 1 1 0 12dB 0 1 1 1 14dB 1 0 0 0 16dB 1 0 0 1 18dB 1 0 1 0 20dB 1 0 1 1 22dB 1 1 0 0 24dB 1 1 0 1 26dB 1 1 1 0 28dB 1 1 1 1 30dB LSB VOLUME 1dB STEPS GAIN = 0 to 30dB VOLUME SELECTION MSB D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 X 1 1 1 -40dB X X X MUTE VOLUME = 0 to 47dB/MUTE 9/13 TDA7449L DATA BYTES (continued) SPEAKER ATTENUATE SELECTION MSB D7 D6 D5 D4 D3 LSB SPEAKER ATTENUATION D2 D1 D0 1dB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 -72dB 1 1 1 1 X X X MUTE SPEAKER ATTENUATION = 0 to -79dB/MUTE PIN: 1 PINS: 4, 5 VS VS VS 20K 24 ROUT LOUT CREF 20µA 20K D96AU430 D96AU434 10/13 TDA7449L PINS: 6,7,8,9 PINS: 10,11 VS VS VS 20µA 20µA MUXOUT IN 100K GND VREF D96AU425 PIN: 19 D96AU491 PIN: 20 20µA SCL 20µA SDA D96AU423 D96AU424 11/13 TDA7449L mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 12/13 OUTLINE AND MECHANICAL DATA 3.3 0.130 1.34 DIP20 0.053 TDA7449L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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