L4973V3.3 - L4973V5.1 L4973D3.3 - L4973D5.1 3.5A STEP DOWN SWITCHING REGULATOR UPTO 3.5ASTEP DOWNCONVERTER OPERATING INPUT VOLTAGE FROM 8V TO 55V 3.3V AND 5.1V (±1%) FIXED OUTPUT, AND ADJUSTABLE OUTPUTS FROM: 0V TO 50V (3.3V type) 5.1V TO 50V (5.1 type) FREQUENCY ADJUSTABLE UP TO 300KHz VOLTAGE FEED FORWARD ZERO LOAD CURRENT OPERATION (min 1mA) INTERNAL CURRENT LIMITING (PULSE BY PULSE AND HICCUP MODE) PRECISE 5.1V (1.5%) REFERENCE VOLTAGE EXTERNALLY AVAILABLE INPUT/OUTPUT SYNCHRONIZATION FUNCTION INHIBIT FOR ZERO CURRENT CONSUMPTION (100µA Typ. at VCC = 24V) PROTECTION AGAINST FEEDBACK DISCONNECTION THERMAL SHUTDOWN OUTPUT OVERVOLTAGE PROTECTION SOFT START FUNCTION MULTIPOWER BCD TECHNOLOGY POWERDIP (12+3+3) SO20(12+4+4) ORDERING NUMBERS: L4973V3.3 (Powerdip) L4973D3.3 (SO20) L4973V5.1 (Powerdip) L4973D5.1 (SO20) DESCRIPTION The L4973 is a step down monolithic power switching regulator delivering 3.5A at fixed voltages of 3.3V or 5.1V and using a simple external divider output adjustable voltage up to 50V. Realized in BCD mixed technology, the device TYPICAL APPLICATION CIRCUIT (POWERDIP) VCC (8V to 55V) 7 10 12 8 ROSC 9 L4973 CIN C2 1 4,5,6, 13,14,15 16 CBOOT 3 11 2 17 VO(3.3V or 5.1V) L1 RCOMP COSC CSS D1 COUT CCOMP D97IN554A April 2000 1/16 L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1 uses an internal power D-MOS transistor (with a typical Rdson of 0.15ohm) to obtain very high efficiency and very fast switching times. Switching frequency up to 300KHz are achievable (the maximum power dissipation of the packages must be observed). A wide input voltage range between 8V to 55V and output voltages regulated from 3.3V to 40V cover the majority of the today applications. Features of this new generation of DC-DC con- verter includes pulse by pulse current limit, hiccup mode for output short circuit protection, voltage feed forward regulation, soft start, input/output synchronization, protection against feedback loop disconnection, inhibit for zero current consumption and thermal shutdown. Packages available are in plastic dual in line, DIP18 (12+3+3) for standard assembly, and SO20 (12+4+4) for SMD assembly. PIN CONNECTIONS (Top view) OSC 1 18 SYNC OSC 1 20 SYNC OUT 2 17 SS OUT 2 19 SS V5.1 OUT 3 18 V5.1 GND GND 4 17 GND GND 5 16 GND GND 6 15 GND GND 7 14 GND VCC 8 13 VFB VCC 9 12 COMP 10 11 INH 3 OUT 16 4 GND 15 5 GND 14 GND GND 6 13 GND VCC 7 12 VFB VCC 8 11 COMP BOOT 9 10 INH BOOT D94IN162A D94IN163A POWERDIP (12+3+3) SO20 (12+4+4) BLOCK DIAGRAM VCC V5.1 INH 10(11) 16(18) VCC 7(8) 8(9) CBOOT CHARGE ZERO CURRENT INHIBIT VREF GOOD 5.1V INTERNAL REFERENCE INTERNAL SUPPLY 5.1V 3.3V SS COMP 17(19) SOFT START 11(12) THERMAL SHUTDOWN 5.1V 3.3V VFB SYNC 12(13) 18(20) + E/A - CURRENT LIMITING PWM + R Q S Q 9(10) BOOT OSCILLATOR DRIVER 1(1) OSC Pin x = Powerdip Pin (x) = S020 2/16 HICCUP CURRENT LIMITING 4,5,6,13,14,15 (4,5,6,7,14,15,16,17) GND 2(2) OUT 3(3) OUT D94IN161B L4973V3 - L4973V5 - L4973D3 - L4973D5 THERMAL DATA Symbol Powerdip SO20 Unit Rth(j-pin) Thermal Resistance Junction to pin Parameter Max. 12 15 °C/W Rth(j-amb) Thermal Resistance to Ambient Max. 60 (*) 80 (*) °C/W Value Unit (*) Package mounted on board. ABSOLUTE MAXIMUM RATINGS Symbol Parameter DIP-18 S0-20 V7,V8 V9,V8 Input voltage 58 V V2,V3 V2,V3 Output DC voltage Output peak voltage at t = 0.1µs f=200KHz -1 -5 V V I2,I 3 I2,I3 V9-V8 V10-V8 14 V V9 V10 Bootstrap voltage 70 V V Maximum output current int. limit. V11 V12 Analogs input voltage (VCC = 24V) 12 V17 V19 Analogs input voltage (VCC = 24V) 13 V V12 V13 (VCC = 20V) 6 -0.3 V V V18 V20 (VCC = 20V) 5.5 -0.3 V V V10 V11 Inhibit Vcc -0.3 V V 5 1.3 2 W W W Ptot TJ,TSTG Power dissipation a Tpins ≤ 90°C (Tamb = 70°C no copper area) (Tamb = 70°C 4cm copper area on PCB) DIP 12+3+3 Power dissipation a Tpins = 90°C SO20 Junction and storage temperature 4 W -40 to 150 °C PIN FUNCTIONS Powerdip SO20 NAME 11 12 COMP DESCRIPTION 10 11 INH A logic signal (active high) disables the device (sleep mode operation). If not used it must be connected to GND; if floating the device is disabled. 9 10 BOOT A capacitor connected between this pin and the output allows to drive the internal D-MOS. E/A output to be used for frequency compensation 18 20 SYNC Input/Output synchronization. 7,8 8,9 Vcc Unregulated DC input voltage 2,3 2,3 OUT Stepdown regulator output. 12 13 VFB Stepdown feedback input. Connecting the output directly to this pin results in an output voltage of 3.3V for the L4973V3.3 and 5.1V. An external resistive divider is required for higher output voltages. For output voltage less than 3.3V, see note ** and Figure 32. 16 18 V5.1 Reference voltage externally available. 4,5,6 13,14,15 4,5,6,7 14,15,16,17 GND Signal ground 1 1 OSC An external resistor connected between the unregulated input voltage and Pin 1 and a capacitor connected from Pin 1 to ground fixes the switching frequency. (Line feed forward is automatically obtained) 3/16 L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1 ELECTRICAL CHARACTERISTICS ( Refer to the test circuit,VCC = 24V; Tj = 25°C, COSC = 2.7nF; ROSC = 20KΩ; unless otherwise specified) • = specifications referred to TJ from 0 to 125°C. Symbol Parameter Test Conditions DYNAMIC CHARACTERISTICS Input Voltage Range (*) Output Voltage L4973V5.1 Output Voltage L4973V3.3 R DSON η ∆fsw Maximum Limiting Current Efficiency Switching Frequency Supply Voltage Ripple Rejection Switching Frequency Stability vs, Supply Voltage VO = VREF to 40V; IO = 3.5A IO = 1A IO = 0.5A to 3.5A VCC = 8V to 55V IO = 1A IO = 0.5A to 3.5A VCC = 8V to 40V VCC = 10.5V IO = 3.5A VCC = 8V to 55V VO = 5.1V; IO = 3.5A VO = 3.3V; IO = 3.5A Min. • Typ. 8 • 5.05 5.00 4.95 3.326 3.292 3.26 • • 5.1 5.1 5.1 3.36 3.36 3.36 0.15 4 4.5 90 85 100 • • Vi = VCC +2VRMS VO = Vref; IO = 1A; fripple = 100Hz VCC = 8V to 55V 90 60 Max. Unit 55 V 5.15 5.20 5.25 3.393 3.427 3.46 0.22 0.35 5.5 V V V V V V Ω Ω A % % KHz dB 110 2 5 % 5.1 5.1 5.175 5.250 V V 5 10 mV 30 2 6 65 10 25 100 mV mV mA Soft Start Charge Current 30 45 60 µA Soft Start Discharge Current 15 22 30 µA 16 15 0.8 50 50 V V µA µA 4 6 mA 2.7 100 150 4 200 300 mA µA µA 2 300 0.65 3 600 V V µA µA REFERENCE SECTION Reference Voltage Line Regulation Load Regulation Iref = 0 to 20mA; VCC = 8 to 55V Iref = 0mA; VCC = 8 to 55V Vref = 0 to 5mA; VCC = 0 to 20mA • Short Circuit Current 5.025 4.950 SOFT START INHIBIT High Level Voltage Low Level Voltage Isource High Level Isource Low Level VINH = 3V VINH = 0.8V • • • • 3.0 10 10 DC CHARACTERISTICS Total Operating Quiescent Current Quiescent Current Total stand-by quiescent current Duty Cycle = 50% Duty Cycle = 0 VCC = 24V; VINH = 5V VCC = 55V; VINH = 5V ERROR AMPLIFIER High Level Output Voltage Low Level Output Voltage Source Bias Current Source Output Current 4/16 11.0 1 200 L4973V3 - L4973V5 - L4973D3 - L4973D5 ELECTRICAL CHARACTERISTICS (continued) Sink Output Current Supply Voltage Ripple Rejection VCOMP = VFB CREF =4.7µF 1-5mA load current RL = ∞ Icomp = -0.1 to 0.1mA; Vcomp = 6V DC Open Loop Gain Transconductance 200 300 µA 60 80 dB 50 60 2.5 dB mS 0.78 1.9 9 95 0.85 2.1 9.6 97 OSCILLATOR SECTION Ramp valley Ramp peak VCC = 8V VCC = 55V Maximum Duty Cycle Maximum Frequency 0.92 2.3 10.2 Duty Cycle = 0%; R OSC = 13KΩ; COSC = 820pF; 500 V V V % KHz SYNC FUNCTION High Input Voltage Low Input Voltage Slave Sink Current Master Output Amplitude Output Pulse Width VCC = 8V to 55V VCC = 8V to 55V 3.5 0.15 4 0.20 Isource = 3mA no load, Vsync = 4.5V 0.9 0.45 0.25 4.5 0.35 V V mA V µs (*) Pulse testing with a low duty cycle. (**) The maximum power dissipation of the package must be observed. Figure 1. Evaluation Board Circuit VCC (DIP18) R2 7,8 12 1 C1 C2 C7 16 9 L4973 17 11 10 C8 4,5,6 2,3 13,14,15 L1 VO R3 C3 C4 C5 D1 R1 3x C0 C12 C6 R4 D97IN515B C1=1000µF/63V C2=220nF/63V C3=470nF C4=1µF/50V C5=220pF C6=22nF C7=2.7nF C8=220nF/63V C0=100µF/40V(C9,C10,C11) C12=Optional (220nF) L1=150µH KOOLµ 77310 - 40 Turns - 0.9mm R1=9.1K R2=20K D1=GI SB560 L4973 V3.3 VO(V) R3(KΩ) 3.3 0 5.1 2.7 12 12 15 L4973 V5.1 R4(KΩ) VO(V) R3(KΩ) 5.1 0 R4(KΩ) 4.7 12 6.2 4.7 4.7 15 9.1 4.7 16 4.7 18 12 4.7 18 20 4.7 24 18 4.7 24 30 4.7 5/16 L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1 Typical Performance (Using Evaluation Board) fsw = 100kHz Output Voltage Output Ripple Efficiency Line Regulator Io = 3.5A VCC = 8 to 50V Load Regulator VCC =35V IO = 1 to 3.5A 3.3V 20mV 81.5 (%) 3mV 6mV 5.1V 20mV 86.7 (%) 3mV 6mV 12V 30mV 93.5 (%) 3mV (VCC =15 to 50V) 4mV Figure 1a: Evaluation Board (Components Side) Figure 1b: Evaluation Board (Solder Side) 6/16 L4973V3 - L4973V5 - L4973D3 - L4973D5 Figure 1c: Application Circuit (see fig. 1 part list) VCC R2 INH SYNC 10 18 7,8 9 C8 1 L4973V5.1 17 C1 C2 C7 C3 16 C4 4,5,6 13,14,15 12 11 C5 L1 Vo 2,3 3x C0 D1 R1 C12 C6 D97IN665A Figure 1d: Application Circuit (see fig. 1 part list) VCC R2 7,8 INH SYNC 10 18 9 C8 1 C1 C2 C7 C3 C4 17 L4973V3.3 16 4,5,6 13,14,15 C5 11 L1 12 D1 R1 Vo 2,3 3x C0 C12 C6 D97IN664A Figure 2: Quiescent Drain Current vs. Input Voltage (0% Duty Cycle) Ibias (mA) D97IN633A 200KHz-R2=22K C7=1.2nF 5.0 Tamb=25°C 0% DC Figure 3: Quiescent Drain Current vs. Junction Temperature Ibias (mA) D97IN634 200KHz-R2=22K C7=1.2nF 4.0 4.5 100KHz-R2=20K C7=2.7nF 4.0 100KHz-R2=20K C7=2.7nF 3.5 3.5 0% DC VCC = 35V 0Hz 3.0 3.0 0Hz 2.5 2.0 0 10 20 30 40 50 VCC(V) 2.5 -50 0 50 100 Tj(°C) 7/16 L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1 Figure 4: Stand by Drain Current vs. input Voltage Ibias (µA) D97IN635A Figure 5: Reference Voltage vs. Junction Temperature (Pin 16) VREF (V) D97IN637 Vinh = 5V Pin 16 5.15 150 Vcc=35V 25°C 5.1 100 125°C 5.05 50 0 10 20 30 40 50 VCC(V) Figure 6: Reference Voltage vs. Input Voltage (Pin 16) VREF (V) D97IN636A 5.0 -40 -20 0 20 40 60 80 100 Tj(°C) Figure 7: Reference Voltage vs. Reference Input Current VREF (V) D97IN638 Tj=25°C Pin 16 5.15 5.2 Vcc=40V 5.1 5.1 Vcc=10V 5.05 5.0 Tj=25°C 5.0 0 10 20 30 40 50 VCC(V) Figure 8: Inhibit Current vs. Inhibit Voltage (Pin 10) Iinh (µA) D97IN651 Vcc=35V Pin 10 100 4.9 0 10 20 30 40 50 IREF(mA) Figure 9: Line Regulation (see fig. 1) VO (V) D97IN639A Tj=0°C 5.12 Tj=125°C C 5° =2 Tj Tj=25°C 5.1 50 Tj=125°C 5.08 0 -50 8/16 5.06 0 5 10 15 Vinh(V) IO = 1A 0 10 20 30 40 50 VCC(V) L4973V3 - L4973V5 - L4973D3 - L4973D5 Figure 10: Load Regulation (see fig. 1c) VO (V) Figure 11: Line Regulation (see fig. 1d) D97IN640 VO (V) D97IN660A 3.35 VCC = 35V 5.15 Tj=125°C 3.34 Tj=125°C Tj=25°C 5.1 3.33 Tj=25°C 3.32 5.05 IO = 1A 3.31 5.0 0 1 2 3 IO(A) Figure 12: Load Regulation (see fig. 1d) VO (V) 0 10 20 30 40 50 VCC(V) Figure 13: Switching Frequency vs.R2 and C7 (fig. 1) D97IN661 fsw (KHz) D97IN630 500 VCC = 35V 3.35 3.3 Tamb=25°C 0.8 2nF 200 3.34 1.2 Tj=125°C nF 100 2.2n F 3.33 50 3.3n F Tj=25°C 3.32 4.7n F 20 F 3.31 3.3 5.6n 10 5 0 1 2 3 Figure 14: Switching Frequency vs. Input Voltage fsw (KHz) 0 IO(A) D97IN631 20 40 60 80 R2(KΩ) Figure 15: Switching Frequency vs. Junction temperature (see fig. 1) fsw (KHz) D97IN632 Tamb=25°C 105 105 100 100 95 95 90 0 10 20 30 40 50 VCC(V) 90 -50 0 50 100 Tj(°C) 9/16 L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1 Figure 16: Dropout Voltage Between pin 7,8 and 2,3 ∆V (V) D97IN643 η (%) D97IN641 98 Tj=125°C 100KHz °C 25 0.6 Figure 17: Efficiency vs. Output Voltage (see fig.1) 96 Tj= 94 0.4 200KHz 92 Tj=0°C 90 0.2 IO = 3A VCC = 50V 88 86 0 0 1 2 3 IO(A) 10 20 30 40 VO(V) Figure 19: Efficiency vs. Output Current ( see fig.1c) Figure 18: Efficiency vs. Output Voltage (Diode STPS745D) η (%) 0 D97IN642 η (%) D97IN645 98 VO = 5.1V fsw = 100KHz 100KHz 96 95 Vcc=12V 94 200KHz 90 92 Vcc=24V 90 Vcc=48V 85 IO = 3A VCC = 35V 88 86 0 5 10 15 20 25 30 VO (V) Figure 20: Efficiency vs. Output Current (see fig.1c) η (%) 80 0 1 2 3 IO(A) Figure 21: Efficiency vs. Output Current (see fig.1d) D97IN646 η (%) D97IN644 V O = 3.3V fsw = 100KHz Vcc=12V 90 90 Vcc=12V Vcc=24V 85 85 Vcc=24V Vcc=48V 80 75 10/16 80 VO = 5.1V fsw = 200KHz 0 1 2 3 IO (A) 75 Vcc=48V 0 1 2 3 IO(A) L4973V3 - L4973V5 - L4973D3 - L4973D5 Figure 23: Power dissipation vs. Input Voltage (Device only) (see fig.1c) Figure 22: Efficiency vs. Output Current (see fig.1d) η (%) Pdiss (W) D97IN662 VO = 5.1V fsw = 100KHz VO = 3.3V fsw = 200KHz 90 D97IN647A 1.5 Vcc=12V IO =3.5A 85 Vcc=24V IO =3A 1.0 80 IO=2.5A Vcc=48V 0.5 75 70 0 0.5 1 1.5 2 2.5 3 Figure 24: Power dissipation vs. Output Voltage (Device only) Pdiss (W) VCC = 35V fsw = 100KHz 0 10 20 30 40 50 Vcc(V) Figure 25: Pulse by Pulse Limiting Current vs. Junction Temperature Ilim (A) D97IN648 3.0 0 3.5 IO (A) IO =2A D97IN652 5.2 I O =3.5A 2.5 5 2.0 I O=3A 1.5 IO =2.5A 4.8 1.0 IO =2A 0.5 I O =1A 0 0 5 10 15 20 25 30 Vcc=35 4.6 4.4 V O(V) Figure 26: Load Transient IO (A) 4.2 -40 -20 0 VCC (V) D97IN649 30 2 20 D97IN650 10 T VO (mV) 2 VO (mV) 1 200µs/DIV I O = 1A f sw = 100KHz 100 1 Tj(°C) Figure 27: Line Transient 3 1 20 40 60 80 100 120 T 0 VCC = 35V fsw = 100KHz 2 100 0 -100 -100 1ms/DIV 11/16 L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1 Figure 29: Soft Start Capacitor Selection vs. Inductor and VCC max (ref. AN938) Figure 28: Source Current Rise and Fall Time, pin 2, 3 (See fig1) Lomax (µH) D97IN653 Css=1µF Css=820nF 300 fsw = 100KHz 250 Css=680nF 200 Css=470nF 150 100 Css=220nF Css=100nF 50 0 Figure 30:Soft Start Capacitor Selection vs. Inductor and VCC max (ref. AN938) Lomax (µH) 35 40 45 GAIN (dB) 50 Vi(V) Phase s= 68 56 nF nF D97IN663 50 Cs s= Cs 30 Figure 31: Open Loop Frequency and Phase of Error amplifier D97IN654 f sw = 200KHz 25 150 0 0 -50 45 Cs s= 47 nF GAIN 100 nF 3 =3 s Cs 90 -100 nF 50 2 =2 Phase s Cs 135 -150 0 -200 15 20 25 30 35 40 45 50 Vi(V) 10 102 103 104 105 106 107 108 f(Hz) Figure 32: 3.5A at VO< 3.3V (see part list fig. 1) VCC INH R2 7,8 SYNC 10 18 9 L4973V3.3 17 C2 C7 11 4,5,6 13,14,15 16 R5 C3 C5 R1 C6 C4 D97IN666A 12/16 R5 R3 1 3.6K 4.7K 1.5 2K 2K 2 4.7K 3.6K 2.5 7.5K 3.6K 3 5.1K 1K C8 1 C1 VP L1 2,3 Vo 12 D1 3x C0 R3 VO=3.36-1.74• R3 R5 L4973V3 - L4973V5 - L4973D3 - L4973D5 Figure 33: 12V to 3.3V High Performance Buck Converter (fsw = 200kHz) VCC 12V±5% R2 22k 7,8 INH SYNC 10 18 16 C1 560uF-25V HFQ Panasonic C2 220nF C3 33nF L4973V3.3 17 C7 1.2nF C4 1uF 4,5,6 13,14,15 11 C5 220pF η (%) C8 220nF 9 1 92 L1 2,3 90 12 Vo=3.33V Io=3.5A R1 9k1 D1 C6 22nF 88 86 C9 470uF-25V HFQ Panasonic 84 82 L1 D1 KoolMm 77120- 24 Turns- 0.9mm STPS1025 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Io(A) D97IN668A Figure 34: Synchronization Example V CC1 VCC2 7,8 1 VCC 7,8 18 L4973 18 4,5,6 13,14,15 7,8 L4973 1 1 4,5,6 13,14,15 18 18 L4973 7,8 L4973 4,5,6 13,14,15 4,5,6 13,14,15 1 D97IN669 Figure 35: Multioutput not Isolated (Pin out referred to DIP12+3+3) V CC INH SYNC 10 18 7,8 Vo2 D2 C8 R2 9 1 L4973 17 C1 C2 C7 C3 16 C4 C5 4,5,6 13,14,15 11 R1 n2 12 2,3 L1 Vo1 n1 D1 C9 C10 C11 C6 V O2 = VO1 n1 + n 2 n1 D97IN667A PO2 < 20% P O1 13/16 L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1 mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 20.32 0.800 F 7.10 0.280 I 5.10 0.201 L Z 14/16 OUTLINE AND MECHANICAL DATA 3.30 0.130 2.54 Powerdip 18 0.100 L4973V3 - L4973V5 - L4973D3 - L4973D5 mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 OUTLINE AND MECHANICAL DATA 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0° (min.)8° (max.) L h x 45° A B e A1 K C H D 20 11 E 1 0 1 SO20MEC 15/16 L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 16/16