STMICROELECTRONICS L6561D

L6561

POWER FACTOR CORRECTOR
VERY PRECISE ADJUSTABLE OUTPUT
OVERVOLTAGE PROTECTION
MICROPOWERSTART-UPCURRENT (50µATYP.)
VERY LOW OPERATING SUPPLY CURRENT
(4mA TYP.)
INTERNAL START-UP TIMER
CURRENT SENSE FILTER ON CHIP
DISABLE FUNCTION
1% PRECISION (@ T j = 25°C) INTERNAL
REFERENCE VOLTAGE
TRANSITION MODE OPERATION
TOTEM POLE OUTPUT CURRENT: ±400mA
DIP8/SO8 PACKAGES
Minidip
SO8
ORDERING NUMBERS:
L6561 (Minidip)
L6561D (SO8)
Realised in mixed BCD technology, the chip gives
the following benefits:
- micro power start up current
- 1% precision internal reference voltage
(Tj = 25°C)
- Soft Output Over Voltage Protection
- no need for external low pass filter onthe current
sense
- verylow operating quiescent current minimises
power dissipation
The totem pole output stage is capable of driving
a Power MOS or IGBT with source and sink currents of +/- 400mA. The device is operating in
transition mode and it is optimised for Electronic
Lamp Ballast application, AC-DC adaptors and
SMPS.
DESCRIPTION
L6561 is the improved version of the L6560
standard Power Factor Corrector. Fully compatible with the standard version, it has a superior
performant multiplier making the device capable
of working in wide input voltage range applications (from 85V to 265V) with an excellent THD.
Furthermore the start up current has been reduced at few tens of µA and a disable function
has been implemented on the ZCD pin, guaranteeing lower current consumption in stand by
mode.
BLOCK DIAGRAM
INV
1
2.5V
VOLTAGE
REGULATOR
VCC
COMP
MULT
2
3
-
CS
4
MULTIPLIER
+
OVER-VOLTAGE
DETECTION
+
40K
5pF
-
VCC
8
INTERNAL
SUPPLY 7V
R
R1
20V
Q
S
+
7
DRIVER
UVLO
GD
-
R2
VREF2
-
2.3V
1.8V
ZERO CURRENT
DETECTOR
STARTER
+
DISABLE
6
GND
April 1999
5
ZCD
D97IN547B
1/11
L6561
ABSOLUTE MAXIMUM RATINGS
Symbol
Pin
IVcc
8
ICC + IZ
Parameter
Value
Unit
30
IGD
7
Output Totem Pole Peak Current (2µs)
mA
±700
mA
INV, COMP
MULT
1, 2, 3
Analog Inputs & Outputs
-0.3 to 7
V
CS
4
Current Sense Input
-0.3 to 7
V
ZCD
5
Zero Current Detector
50 (source)
-10 (sink)
mA
mA
1
0.65
W
Junction Temperature Operating Range
-25 to 150
°C
Storage Temperature
-55 to 150
°C
Power Dissipation @Tamb = 50 °C
Ptot
Tj
Tstg
(Minidip)
(SO8)
PIN CONNECTION
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction-ambient
SO 8
MINIDIP
Unit
150
100
°C/W
PIN FUNCTIONS
N.
Name
Function
1
INV
2
COMP
Output of error amplifier. A feedback compensation network is placed between this pin and
the INV pin.
3
MULT
Input of the multiplier stage. A resistive divider connects to this pin the rectified mains. A
voltage signal, proportional to the rectified mains, appears on this pin.
4
CS
Inverting input of the error amplifier. A resistive divider is connected between the output
regulated voltage and this point, to provide voltage feedback.
Input to the comparator of the control loop. The current is sensed by a resistor and the
resulting voltage is applied to this pin.
5
ZCD
Zero current detection input. If it is connected to GND, the device is disabled.
6
GND
Current return for driver and control circuits.
7
GD
Gate driver output. A push pull output stage is able to drive the Power MOS with peak current
of 400mA (source and sink).
8
VCC
Supply voltage of driver and control circuits.
2/11
L6561
ELECTRICAL CHARACTERISTICS (VCC = 14.5V; T amb = -25°C to 125°C; unless otherwise specified)
SUPPLY VOLTAGE SECTION
Symbol
Pin
VCC
8
Operating Range
Parameter
Test Condition
after turn-on
Min.
Typ.
11
Max.
Unit
18
V
V
VCC ON
8
Turn-on Threshold
11
12
13
VCC OFF
8
Turn-off Threshold
8.7
9.5
10.3
V
Hys
8
Hysteresis
2.2
2.5
2.8
V
Min.
Typ.
Max.
Unit
20
50
90
µA
2.6
4
mA
mA
SUPPLY CURRENT SECTION
Symbol
Pin
ISTART-U
8
Start-up Current
Iq
8
Quiescent Current
Operating Supply Current
ICC
Quiescent Current
Iq
VZ
Parameter
8
Zener Voltage
Test Condition
before turn-on (VCC =11V)
4
5.5
in OVP condition Vpin1 = 2.7V
CL = 1nF @ 70KHz
1.4
2.1
mA
VPIN5 ≤ 150mV, VCC > VCC off
1.4
2.1
mA
VPIN5 ≤ 150mV, VCC < VCC off
20
50
90
ICC = 25mA
18
20
22
µA
V
ERROR AMPLIFIER SECTION
Symbol
Pin
VINV
1
IINV
1
GB
VCOMP
Parameter
Typ.
Max.
Unit
Tamb = 25°C
2.465
2.5
2.535
V
12V < VCC < 18V
2.44
Line Regulation
VCC = 12 to 18V
Test Condition
Input Bias Current
Voltage Gain
GV
ICOMP
Min.
Voltage Feedback Input
Threshold
2
5
mV
-0.1
-1
µA
Open loop
60
80
Source Current
VCOMP = 4V, VINV = 2.4V
-2
-4
Sink Current
VCOMP = 4V, VINV = 2.6V
2.5
4.5
Gain Bandwidth
2
2.56
2
dB
1
MHz
-8
mA
mA
Upper Clamp Voltage
ISOURCE = 0.5mA
5.8
V
Lower Clamp Voltage
ISink = 0.5mA
2.25
V
MULTIPLIER SECTION
Symbol
Pin
VMULT
3
∆VCS
∆Vmult
K
Parameter
Test Condition
Linear Operating Voltage
Min.
Typ.
Max.
0 to 3 0 to 3.5
Unit
V
Output Max. Slope
VMULT = from 0V to 0.5V
VCOMP = Upper Clamp Voltage
1.65
1.9
Gain
VMULT = 1V VCOMP = 4V
0.45
0.6
0.75
1/V
CURRENT SENSE COMPARATOR
Symbol
Pin
Test Condition
Min.
Typ.
Max.
Unit
VCS
4
Current Sense Reference
Clamp
Parameter
VMULT = 2.5V
VCOMP = Upper Clamp Voltage
1.6
1.7
1.8
V
ICS
4
Input Bias Current
VOS = 0
-0.05
-1
µA
td (H-L)
4
Delay to Output
200
450
ns
4
Current Sense Offset
0
15
mV
3/11
L6561
ELECTRICAL CHARACTERISTICS (continued)
ZERO CURRENT DETECTOR
Symbol
Pin
VZCD
5
VZCD
5
VZCD
Parameter
Test Condition
Min.
Typ.
Max.
2.1
Unit
Input Threshold Voltage
Rising Edge
(1)
V
Hysteresis
(1)
0.3
0.5
0.7
Upper Clamp Voltage
IZCD = 20µA
4.5
5.1
5.9
V
5
Upper Clamp Voltage
IZCD = 3mA
4.7
5.2
6.1
V
VZCD
5
Lower Clamp Voltage
IZCD = –3mA
0.3
0.65
1
V
IZCD
5
Sink Bias Current
1V ≤ VZCD ≤ 4.5V
V
IZCD
5
Source Current Capability
-3
-10
µA
mA
IZCD
5
Sink Current Capability
3
10
mA
VDIS
5
Disable threshold
IZCD
5
Restart Current After Disable
VZCD < Vdis; VCC > VCCOFF
2
150
200
250
mV
-100
-200
-300
µA
OUTPUT SECTION
VGD
7
Dropout Voltage
IGDsource = 200mA
1.2
2
V
IGDsource = 20mA
0.7
1
V
1.5
V
IGDsink = 200mA
IGDsink = 20mA
tr
7
Output Voltage Rise Time
C L = 1nF
tf
7
Output Voltage Fall Time
C L = 1nF
IGD off
7
IGD Sink Current
VCC =3.5V VGD = 1V
0.3
V
40
100
ns
40
100
ns
5
10
-
mA
OVP Triggering Current
35
40
45
µA
Static OVP Threshold
2.1
2.25
2.4
V
70
150
400
µs
OUTPUT OVERVOLTAGE SECTION
IOVP
2
RESTART TIMER
tSTART
Start Timer
(1) Parameter guaranteed by design, not tested in production.
OVER VOLTAGE PROTECTION OVP
The output voltage is expected to be kept by the
operation of the PFC circuit close to its nominal
value. This is set by the ratio of the two external
resistors R1 and R2 (see fig. 2), taking into consideration that the non inverting input of the error
amplifier is biased inside the L6561 at 2.5V.
In steady state conditions, the current through R1
and R2 is:
IR1sc =
Vout − 2.5
2.5V
= IR2 =
R1
R2
and, if the external compensation network is
made only with a capacitor Ccomp, the current
through Ccomp equals zero.
When the output voltage increases abruptly the
current through R1 becomes:
IR1 =
4/11
Voutsc + ∆VOUT − 2.5
= IR1sc + ∆IR1
R1
Since the current through R2 does not change,
∆IR1 must flow through the capacitor C comp and
enter the error amplifier.
This current is monitored inside the L6561 and when
reaches about 37µA the output voltage of the multiplier is forced to decrease, thus reducing the energy
drawn from the mains. If the current exceeds 40µA,
the OVP protection is triggered (Dynamic OVP), and
the external power transistor is switched off until the
current falls approximately below 10µA.
However, if the overvoltage persists, an internal
comparator (Static OVP) confirms the OVP condition keeping the external power switch turned off
(see fig. 1).
Finally, the overvoltage that triggers the OVP
function is:
∆Vout = R1 ⋅ 40µA.
Typical values for R1, R2 and C are shown in the
application circuits. The overvoltage can be set independently from the average output voltage. The precision in setting the overvoltage threshold is 7% of
L6561
the overvoltage value (for instance ∆V = 60V ±
4.2V).
for device disabling as well. By grounding the
ZCD voltage the device is disabled reducing the
supply current consumption at 1.4mA typical (@
14.5V supply voltage).
Releasing the ZCD pin the internal start-up timer
will restart the device.
Disable function
The zero current detector (ZCD) pin can be used
Figure 1.
OVER VOLTAGE
VOUT nominal
ISC
40µA
10µA
E/A OUTPUT
2.25V
DYNAMIC OVP
STATIC OVP
D97IN592A
Figure 2. Overvoltage Protection Circuit
Ccomp.
+Vo
∆I
R1
1
2
-
X
E/A
+
R2
PWM
DRIVER
2.5V
2.25V
+
∆I
40µA
D97IN591
5/11
L6561
Figure 3. Typical Application Circuit (80W, 110VAC)
D1 BYT03-400
R3 (*)
D3 1N4150
240K
R2
100
D2
1N5248B
BRIDGE
+ 4 x 1N4007
C1
1µF
250V
FUSE 4A/250V
T
C6
R7 (*)
950K
10nF
68K
5
8
3
Vac
(85V to 135V)
R10
10K
NTC
2
1
7
L6561
-
C2
22µF
25V
Vo=240V
Po=80W
C3 680nF
R1
R9 (*)
950K
+
R5
MOS
STP7NA40
10
4
6
C7
10nF
R6 (*)
0.31
1W
R8
10K
1%
C5
100µF
315V
-
D97IN549B
(*) R3 = 2 x 120KΩ
R6 = 0.619Ω/2
R7 = 2 x 475KΩ, 1%
R9 = 2 x 475KΩ
TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A7)
primary 90T of Litz wire 10 x 0.2mm
secondary 11T of #27 AWG (0.15mm)
gap 1.8mm for a total primary inductance of 0.7mH
Figure 4. Typical Application Circuit (120W, 220VAC)
D1 BYT13-600
R3 (*)
D3 1N4150
440K
BRIDGE
+ 4 x 1N4007
FUSE 2A/250V
R2
100
D2
1N5248B
C1
560nF
400V
T
C6
R7 (*)
998K
10nF
C3 1µF
R1
R9 (*)
1.82M
68K
5
8
Vac
(175V to 265V)
3
R10
10K
NTC
(*) R3 = 2 x 220KΩ
R6 = 0.82Ω/2
R7 = 2 x 499KΩ, 1%
R9 = 2 x 909KΩ
2
1
7
L6561
-
C2
22µF
25V
+
Vo=400V
Po=120W
R5
MOS
STP5NA50
10
4
6
C7
10nF
R6 (*)
0.41
1W
R8
6.34K
1%
C5
56µF
450V
-
D97IN550B
TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8)
primary 90T of Litz wire 10 x 0.2mm
secondary 7T of #27 AWG (0.15mm)
gap 1.25mm for a total primary inductance of 0.8mH
Figure 5. Wide-Range Application (80W)
D1 BYT13-600
R3 (*)
D3 1N4150
240K
BRIDGE
+ 4 x 1N4007
FUSE 4A/250V
R2
100
D2
1N5248B
C1
1µF
400V
C6
R7 (*)
998K
12nF
R9 (*)
1.24M
8
3
R10
10K
C2
22µF
25V
C7
10nF
5
2
6
1
7
R5
MOS
STP8NA50
10
4
R6 (*)
0.41
1W
R8
6.34K
1%
D97IN553B
(*) R3 = 2 x 120KΩ
R6 = 0.82Ω/2
R7 = 2 x 499KΩ, 1%
R9 = 2 x 620KΩ
6/11
Vo=400V
Po=80W
68K
L6561
Vac
(85V to 265V)
+
C3 1µF
R1
-
NTC
T
TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8)
primary 90T of Litz wire 10 x 0.2mm
secondary 7T of #27 AWG (0.15mm)
gap 1.25mm for a total primary inductance of 0.8mH
C5
47µF
450V
-
L6561
Figure 6. P.C. Board and Components Layout of the Figg. 3, 4 and 5 (1:1.25 scale)
C
O
M
P
O
N
E
N
T
S
S
I
D
E
S
O
L
D
E
R
S
I
D
E
Figure 7. OVP Current Threshold vs.
Temperature
D94IN047A
IOVP
(µA)
Figure 8. Undervoltage Lockout Threshold vs.
Temperature
VCC-ON
(V)
D94IN044A
13
41
12
40
11
VCC-OFF
(V)
10
39
9
38
-25
-50 -25
0
25
50
75
100 125 T (°C)
0
25
50
T (°C)
75
100
125
7/11
L6561
Figure 9. Supply Current vs. Supply Voltage
D97IN548A
ICC
(mA)
Figure 10. Voltage Feedback Input Threshold
vs. Temperature
VREF
(V)
D94IN048A
10
5
2.50
1
0.5
0.1
2.48
0.05
C L = 1nF
f = 70KHz
TA = 25°C
0.01
0.005
0
2.46
0
5
10
15
20
VCC(V)
Figure 11. Output Saturation Voltage vs. Sink
Current
VPIN7
(V)
D94IN046
VCC = 14.5V
-50
0
50
100
T (°C)
Figure 12. Output Saturation Voltage vs.
Source Current
VPIN7
(V)
D94IN053
VCC = 14.5V
SINK
2.0
VCC -0.5
1.5
VCC -1.0
1.0
VCC -1.5
0.5
VCC -2.0
SOURCE
0
0
0
100
200
300
400 IGD (mA)
Figure 13. Multiplier Characteristics Family
VCS(pin4)
(V) upper voltage
D97IN555A
VCOMP(pin2)
(V)
clamp
1.6
3.5
5.0
4.5
1.4
1.2
4.0
3.2
1.0
0.8
3.0
0.6
0.4
2.8
0.2
2.6
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VMULT(pin3) (V)
8/11
0
100
200
300
400 IGD (mA)
L6561
mm
DIM.
MIN.
A
TYP.
inch
MAX.
MIN.
3.32
TYP.
MAX.
0.131
a1
0.51
B
1.15
1.65
0.045
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
0.020
D
E
10.92
7.95
9.75
0.430
0.313
0.384
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
Z
3.18
OUTLINE AND
MECHANICAL DATA
3.81
1.52
0.125
0.150
Minidip
0.060
9/11
L6561
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.25
a2
MAX.
0.069
0.004
0.010
1.65
0.065
a3
0.65
0.85
0.026
0.033
b
0.35
0.48
0.014
0.019
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.020
c1
45° (typ.)
D (1)
4.8
5.0
0.189
0.197
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
3.81
0.150
F (1)
3.8
4.0
0.15
0.157
L
0.4
1.27
0.016
0.050
M
S
0.6
0.024
8 ° (max.)
(1) D and F do not include mold flash or protrusions. Mold flash or
potrusions shall not exceed 0.15mm (.006inch).
10/11
OUTLINE AND
MECHANICAL DATA
SO8
L6561
.Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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