STMICROELECTRONICS L6562AN

L6562A
Transition-mode PFC controller
Preliminary Data
Features
■
Proprietary multiplier design for minimum thd
■
Very accurate adjustable output overvoltage
protection
■
Ultra-low (30µA) Start-up current
■
Low (2.5mA) quiescent current
■
Digital leading-edge blanking on current sense
■
Disable function on E/A input
■
1.4% (@ TJ = 25 °C) internal reference voltage
■
-600/+800mA totem pole gate driver with active
pull-down during UVLO and voltage clamp
■
DIP-8
Applications
PFC pre-regulators for:
■
IEC61000-3-2 compliant SMPS (Flat TV,
desktop PC, games)
■
HI-END AC-DC adapter/charger up to 400W
■
Electronic ballast
■
Entry level server & web server
DIP-8/SO-8 packages
Figure 1.
March 2007
SO-8
Block diagram
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/20
www.st.com
20
Contents
L6562A
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2
Disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.3
THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.4
Operating with no auxiliary winding on the boost inductor . . . . . . . . . . . . 12
6.5
Comparison between the L6562A and the L6562 . . . . . . . . . . . . . . . . . . 13
7
Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
L6562A
1
Description
Description
The L6562A is a current-mode PFC controller operating in Transition Mode (TM). Coming
with the same pin-out as its predecessors L6561 and L6562, it offers improved performance.
The highly linear multiplier includes a special circuit, able to reduce AC input current
distortion, that allows wide-range-mains operation with an extremely low THD, even over a
large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and an accurate
(1.4% @TJ = 25°C) internal voltage reference.
The device features extremely low consumption (60µA max. before start-up and <5 mA
operating) and includes a disable function suitable for IC remote ON/OFF, which makes it
easier to comply with energy saving requirements (Blue Angel, EnergyStar, Energy2000,
etc.).
An effective two-step OVP enables to safely handle overvoltages either occurring at start-up
or resulting from load disconnection.
The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable
to drive high current MOSFETs or IGBTs. This, combined with the other features and the
possibility to operate with the proprietary Fixed-Off-Time control, makes the device an
excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W.
3/20
Pin settings
L6562A
2
Pin settings
2.1
Pin connection
Figure 2.
2.2
Pin connection (top view)
INV
1
8
Vcc
COMP
2
7
GD
MULT
3
6
GND
CS
4
5
ZCD
Pin description
Table 1. Pin description
4/20
Pin N°
Name
Description
1
INV
Inverting input of the error amplifier. The information on the output voltage of
the PFC pre-regulator is fed into this pin through a resistor divider. The pin
doubles as an ON/OFF control input.
2
COMP
Output of the error amplifier. A compensation network is placed between this
pin and INV to achieve stability of the voltage control loop and ensure high
power factor and low THD.
3
MULT
Main input to the multiplier. This pin is connected to the rectified mains
voltage via a resistor divider and provides the sinusoidal reference to the
current loop.
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor, the resulting voltage is applied to this pin and compared
with an internal sinusoidal-shaped reference, generated by the multiplier, to
determine MOSFET’s turn-off. The pin is equipped with 200 ns leading-edge
blanking for improved noise immunity.
4
CS
5
ZCD
Boost inductor’s demagnetization sensing input for transition-mode
operation. A negative-going edge triggers MOSFET’s turn-on.
6
GND
Ground. Current return for both the signal part of the IC and the gate driver.
7
GD
Gate driver output. The totem pole output stage is able to drive power
MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA
sink. The high-level voltage of this pin is clamped at about 12V to avoid
excessive gate voltages in case the pin is supplied with a high Vcc.
8
Vcc
Supply Voltage of both the signal part of the IC and the gate driver. The
supply voltage upper limit is extended to 22V min. to provide more headroom
for supply voltage changes.
L6562A
3
Maximum ratings
Maximum ratings
Table 2. Absolute maximum ratings
4
Symbol
Pin
VCC
8
IGD
7
---
1 to 4
IZCD
5
Parameter
Value
Unit
IC supply voltage (ICC ≤ 20mA)
Self-limited
V
Output totem pole peak current
Self-limited
A
-0.3 to 8
V
±10
mA
Analog inputs & outputs
Zero current detector max. current
Thermal data
Table 3. Thermal data
Value
Symbol
Parameter
Unit
SO8
DIP8
RthJA
Max. Thermal Resistance, Junction-toambient
150
100
°C/W
PTOT
Power Dissipation @TA = 50°C
0.65
1
W
TJ
TSTG
Junction Temperature Operating range
-40 to 150
°C
Storage Temperature
-55 to 150
°C
5/20
Electrical characteristics
5
L6562A
Electrical characteristics
Table 4. Electrical characteristics
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
22
V
Supply voltage
VCC
Operating range
VccOn
Turn-on threshold
VccOff
Turn-off threshold
Hys
Hysteresis
VZ
Zener Voltage
After turn-on
(1)
10.5
11.5
12.5
13.5
V
9.5
10
10.5
V
2.8
V
25
28
V
2.2
ICC = 20mA
22
Supply current
Istart-up
Iq
ICC
Iq
Start-up current
Before turn-on, VCC = 11V
30
60
µA
Quiescent current
After turn-on
2.5
3.75
mA
3.5
5
mA
1.7
2.2
mA
-1
µA
Operating supply current @ 70kHz
Quiescent current
During OVP (either static or dynamic)
or VINV ≤150mV
Multiplier input
IMULT
Input bias current
VMULT
Linear operation range
∆V cs
-------------------∆V MULT
K
VMULT = 0 to 4V
0 to 3
Output max. slope
VMULT = 0 to 1V,
VCOMP = Upper clamp
Gain (2)
V
1
1.1
V/V
VMULT = 1V, VCOMP= 4V,
0.32
0.38
0.44
TJ = 25 °C
2.465
2.5
2.535
10.5V < VCC < 22V (1)
2.44
V
Error amplifier
VINV
Line regulation
VCC = 10.5V to 22V
IINV
Input bias current
VINV = 0 to 3V
Gv
Voltage gain
Open loop
GB
Gain-bandwidth product
ICOMP
6/20
Voltage feedback input
threshold
V
2.56
2
60
5
mV
-1
µA
80
dB
1
MHz
Source current
VCOMP = 4V, VINV = 2.4V
-2
-3.5
Sink current
VCOMP = 4V, VINV = 2.6V
2.5
4.5
-5
mA
mA
L6562A
Electrical characteristics
Table 4. Electrical characteristics (continued)
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol
VCOMP
Parameter
Test condition
Min
Typ
Max
Unit
Upper clamp voltage
ISOURCE = 0.5mA
5.3
5.7
6
V
Lower clamp voltage
ISINK = 0.5mA (1)
2.1
2.25
2.4
V
150
200
250
mV
450
520
mV
27
30.5
µA
VINVdis
Disable threshold
VINVen
Restart threshold
Output overvoltage
IOVP
Dynamic OVP triggering
current
Hys
Hysteresis
(3)
Static OVP threshold
(1)
23.5
20
2.1
2.25
µA
2.4
V
-1
µA
300
ns
Current sense comparator
ICS
Input bias current
tLEB
Leading edge blanking
td(H-L)
VCS = 0
100
Delay to output
VCS
Current sense clamp
Vcsoffset
Current sense offset
200
175
VCOMP = Upper clamp
1.0
1.08
VMULT = 0
25
VMULT = 2.5V
5
ns
1.16
V
mV
Zero current detector
VZCDH
Upper clamp voltage
IZCD = 2.5mA
5.0
5.7
6.5
V
VZCDL
Lower clamp voltage
IZCD = - 2.5mA
-0.3
0
0.3
V
VZCDA
Arming voltage
(positive-going edge)
(3)
1.4
V
VZCDT
Triggering voltage
(negative-going edge)
(3)
0.7
V
IZCDb
Input bias current
VZCD = 1 to 4.5V
2
µA
IZCDsrc
Source current capability
-2.5
mA
IZCDsnk
Sink current capability
2.5
mA
Start timer period
75
Starter
tSTART
190
300
µs
7/20
Electrical characteristics
L6562A
Table 4. Electrical characteristics (continued)
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Gate driver
VOL
Output low voltage
Isink = 100mA
VOH
Output high voltage
Isource = 5mA
Isrcpk
Peak source current
-0.6
A
Isnkpk
Peak sink current
0.8
A
V
10.3
V
tf
Voltage fall time
30
ns
tr
Voltage rise time
85
ns
VOclamp
Output clamp voltage
Isource = 5mA; Vcc = 20 V
UVLO saturation
Vcc = 0 to VCCon, Isink = 2 mA
1. All the parameters are in tracking
2. The multiplier output is given by:
Vcs = K ⋅ VMULT ⋅ (VCOMP − 2.5 )
3. Parameters guaranteed by design, functionality tested in production.
8/20
9.8
1.0
10
12
15
V
1.1
V
L6562A
Application information
6
Application information
6.1
Overvoltage protection
Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a
PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output
divider. Neglecting ripple components, the current through R1, IR1, equals that through R2,
IR2. Considering that the non-inverting input of the error amplifier is internally referenced at
2.5V, also the voltage at pin INV will be 2.5V, then:
Equation 1
V O – 2.5
I R2 = I R1 = 2.5
-------- = --------------------R1
R2
If the output voltage experiences an abrupt change ∆Vo > 0 due to a load drop, the voltage
at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network
connected between pins INV and COMP that introduces a long time constant to achieve
high PF (this is why ∆Vo can be large). As a result, the current through R2 will remain equal
to 2.5/R2 but that through R1 will become:
Equation 2
V O – 2.5 + ∆V O
I' R1 = --------------------------------------R1
The difference current ∆IR1=I'R1-IR2=I'R1-IR1= ∆Vo/R1 will flow through the compensation
network and enter the error amplifier output (pin COMP). This current is monitored inside
the device and if it reaches about 24µA the output voltage of the multiplier is forced to
decrease, thus smoothly reducing the energy delivered to the output. As the current
exceeds 27µA, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch
off the external power transistor and the IC put in an idle state. This condition is maintained
until the current falls below approximately 7µA, which re-enables the internal starter and
allows switching to restart. The output ∆Vo that is able to trigger the Dynamic OVP function
is then:
Equation 3
∆VO = R1 · 20 · 10 - 6
An important advantage of this technique is that the OV level can be set independently of
the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the
individual value of R1. Another advantage is the precision: the tolerance of the detection
current is 13%, i.e. 13% tolerance on ∆Vo. Since ∆Vo << Vo, the tolerance on the absolute
value will be proportionally reduced.
9/20
Application information
L6562A
Example: Vo = 400V, ∆Vo = 40V. Then: R1 = 40V/27µA ≈ 1.5MΩ ;
R2 = 1.5 MΩ ·2.5/(400-2.5) = 9.43kΩ. The tolerance on the OVP level due to the L6562A will
be 40·0.13 = 5.3V, that is ± 1.2%.
When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily
above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs,
however, the error amplifier output will saturate low; hence, when this is detected the
external power transistor is switched off and the IC put in an idle state (Static OVP). Normal
operation is resumed as the error amplifier goes back into its linear region. As a result, the
device will work in burst-mode, with a repetition rate that can be very low.
When either OVP is activated the quiescent consumption of the IC is reduced to minimize
the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply
system.
6.2
Disable function
The INV pin doubles its function as a not-latched IC disable: a voltage below 0.2V shuts
down the IC and reduces its consumption at a lower value. To restart the IC, the voltage on
the pin must exceed 0.45 V. The main usage of this function is a remote ON/OFF control
input that can be driven by a PWM controller for power management purposes. However it
also offers a certain degree of additional safety since it will cause the IC to shutdown in case
the lower resistor of the output divider is shorted to ground or if the upper resistor is missing
or fails open.
6.3
THD optimizer circuit
The device is equipped with a special circuit that reduces the conduction dead-angle
occurring to the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
10/20
L6562A
Application information
Figure 3.
THD optimization: standard TM PFC controller (left side) and L6562A
(right side)
Input current
Input current
Rectified mains voltage
Imains
Input current
Rectified mains voltage
Imains
Input current
MOSFET's drainVdrain
voltage
MOSFET's drainVdrain
voltage
To overcome this issue the circuit embedded in the device forces the PFC pre-regulator to
process more energy near the line voltage zero-crossings as compared to that commanded
by the control loop. This will result in both minimizing the time interval where energy transfer
is lacking and fully discharging the high-frequency filter capacitor after the bridge. The effect
of the circuit is shown in figure 2, where the key waveforms of a standard TM PFC controller
are compared to those of the L6562A.
Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid.
To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after
the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - thus making the action of the
optimizer circuit little effective.
11/20
Application information
6.4
L6562A
Operating with no auxiliary winding on the boost inductor
To generate the synchronization signal on the ZCD pin, the typical approach requires the
connection between the pin and an auxiliary winding of the boost inductor through a limiting
resistor. When the device is supplied by the cascaded DC-DC converter, it is necessary to
introduce a supplementary winding to the PFC choke just to operate the ZCD pin.
Another solution could be implemented by simply connecting the ZCD pin to the drain of the
power MOSFET through an R-C network as shown in figure 3: in this way the highfrequency edges experienced by the drain will be transferred to the ZCD pin, hence arming
and triggering the ZCD comparator.
Also in this case the resistance value must be properly chosen to limit the current
sourced/sunk by the ZCD pin. Recommended values for these components are 22pF (or
33pF) for CZCD and 330k for RZCD. With these values proper operation is guaranteed even
with few volts difference between the regulated output voltage and the peak input voltage
Figure 4.
ZCD pin synchronization without auxiliary winding
RZCD
ZCD
5
L6562A
12/20
CZCD
L6562A
6.5
Application information
Comparison between the L6562A and the L6562
The L6562A is not a direct drop-in replacement of the L6562, even if both have the same
pin-out. One function (Disable) has been relocated.
Table 2 compares the two devices, i.e. those parameters that may result in different values
of the external components. The parameters that have the most significant impact on the
design, i.e. that definitely require external component changes when converting an L6562based design to the L6562A, are highlighted in bold.
Table 5. L6562A vs. L6562
Parameter
L6562
L6562A
12/9.5 V
12.5/10 V
Turn-off threshold spread (max.)
±0.8 V
±0.5 V
IC consumption before start-up (max.)
70 uA
60 uA
0.6
0.38
1.7 V
1.08 V
Current sense propagation delay (delay-to-output)
(typ.)
200 ns
175 ns
Dynamic OVP triggering current (typ.)
40 uA
27 uA
ZCD arm/trigger/clamp thresholds (typ.)
2.1/1.4/0.7 V
1.4/0.7/0 V
0.3 V (1)
0.45 V (2)
2.6 V
2.2 V
No
Yes
IC turn-on & turn-off thresholds (typ.)
Multiplier gain (typ.)
Current sense reference clamp (typ.)
Enable threshold (typ.)
Gate-driver internal drop (max.)
Leading-edge blanking on current sense
1. Function located on pin 5 (ZCD)
2. Function located on pin 1 (INV)
The lower value (-36%) for the clamp level of the current sense reference voltage allows the
use of a lower sense resistor for the same peak current, with a proportional reduction of the
associated power dissipation. Essentially, the advantage is the reduction of the power
dissipated in a single point (hotspot), which is a considerable benefit in applications where
heat removal is critical as in adapters closed/plastic case. The lower value for the Dynamic
OVP triggering current allows the use of a higher resistance value (+48%) for the upper
resistor of the divider sensing the output voltage of the PFC stage (keeping the same
overvoltage level) with no significant increase of noise sensitivity. This reduction goes in
favor of stand-by consumption in applications required to comply with energy saving
regulations.
13/20
Application examples and ideas
7
L6562A
Application examples and ideas
Figure 5.
Typical Application circuit (80W, wide-range mains)
Vo=400V
Po=80W
R4
R5
270 kW 270 kW
BRIDGE
Vac
88V
to
264V
DF06M
+
C1
0.47 µF
400V
T
D3
STTH1L06
R7
100 W
D2
1N5248B
R1
1 MW
FUSE
4A/250V
D1
1N4150 C5 12 nF
R8 22 kW
R6
47 kW
R11
750 kW
R12
750 kW
C6 3300 nF
C7
220 nF
R2
1 MW
-
8
5
2
1
3
L6562A
C2
10nF
C3
22 µF
25V
R9
33 W
C8
47 µF
450V
MOS1
STP8NM50
7
6
R3
15 kW
NTC
2.5 W
4
C4
100 nF
R10A
0.68W
0.25W
R10B
0.68W
0.25W
R13A
18 kW
R13B
20 kW
Boost Inductor Spec (ITACOIL E2543/E)
E25x13x7 core,N67 ferrite
1.5 mm gap for 0.7 mH primary inductance
Primary: 105 turns 20x0.1 mm
Secondary: 8 turns 0.1 mm
Figure 6.
Typical Application circuit (400W, wide-range mains, FOT-controlled)
D1
1N5406
L1
D2
STTH8R06
FUSE
8A/250V
Vac
88V
to
264V
B1
KBU8M +
R1B
1 MW
C1
1 µF
400V
8
2
1
D3 1N4148
C3
1 µF
L6562A
R7 6.8 W
3
-
5
R3
1.5 kW
R2
15 kW
C2
10nF
M1A
STP12NM50
C9
470 nF
630 V
7
TR1
BC857
R4
15 kW
L1: core PQ40-30,PC44 material
1 mm air gap on centre leg, for 0.5 mH inductance
65 T of 32 x AWG32 Æ
( 0.2 mm)
14/20
R11B
750 kW
R5
C5
47 kW 1 µF
Vcc
10.5 to 22 V
Vout = 400V
Pout = 400W
R11A
750 kW
C4
100 nF
R1A
1 MW
NTC1
2.5 W
6
R6
3.3 kW
C6 100 pF
C7
220 pF
D4
1N4148
4
D5
1N4148
C8
330 pF
C10
330 µF
450 V
M1B
STP12NM50
R8 6.8 W
R9 330 W
R10A,B,C,D
0.39 W
1W
R12A
18 kW
R12B
20 kW
L6562A
8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
15/20
Package mechanical data
L6562A
Table 6. DIP-8 mechanical data
mm
Inch
Dim.
Min
A
Typ
Min
3.32
Typ
Max
0.131
a1
0.51
0.020
B
1.15
1.65
0.045
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
D
E
10.92
7.95
9.75
0.430
0.313
0.384
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
3.18
Z
Figure 7.
16/20
Max
3.81
1.52
Package dimensions
0.125
0.150
0.060
L6562A
Package mechanical data
Table 7. SO-8 mechanical data
mm
inch
Dim.
Min.
Typ.
A
Min.
Typ.
1.10
A1
0.050
A2
0.750
b
Max.
0.043
0.150
0.002
0.950
0.03
0.250
0.400
0.010
0.016
c
0.130
0.230
0.005
0.009
D (1)
2.900
3.000
3.100
0.114
0.118
0.122
E
4.650
4.900
5.150
0.183
0.193
0.20
E1 (1)
2.900
3.000
3.100
0.114
0.118
0.122
e
L
L1
0.850
0.650
0.400
0.550
0.006
0.033
0.037
0.026
0.700
0.016
0.950
k
0.022
0.028
0.037
0° (min.) 6° (max.)
aaa
Note:
Max.
0.100
0.004
D and F does not include mold flash or protrusions. Mold flash or potrusions shall not
exceed 0.15mm (.006inch) per side.
Figure 8.
Package dimensions
17/20
Order codes
9
L6562A
Order codes
Table 8. Order codes
18/20
Part number
Package
Packaging
L6562AN
DIP-8
Tube
L6562AD
SO-8
Tube
L6562ADTR
SO-8
Tape & Reel
L6562A
10
Revision history
Revision history
Table 9. Revision history
Date
Revision
3-Mar-2007
1
Changes
First release
19/20
L6562A
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
20/20