FDD26AN06A0_F085 N-Channel PowerTrench® MOSFET 60V, 36A, 26mΩ Features Applications • rDS(ON) = 20mΩ (Typ.), VGS = 10V, ID = 36A • Motor / Body Load Control • Qg(tot) = 13nC (Typ.), VGS = 10V • ABS Systems • Low Miller Charge • Powertrain Management • Low QRR Body Diode • Injection Systems • UIS Capability (Single Pulse and Repetitive Pulse) • DC-DC converters and Off-line UPS • Qualified to AEC Q101 • Distributed Power Architectures and VRMs • RoHS Compliant • Primary Switch for 12V and 24V systems DRAIN (FLANGE) D GATE G SOURCE S TO-252AA FDD SERIES MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol VDSS Drain to Source Voltage Parameter Ratings 60 Units V VGS Gate to Source Voltage ±20 V Continuous (TC = 25oC, VGS = 10V) 36 A Continuous (TC = 100oC, VGS = 10V) 25 A Continuous (Tamb = 25oC, VGS = 10V, RθJA = 52oC/W) 7 A Drain Current ID Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy ( Note 1) Figure 4 A 35 mJ Power dissipation 75 W Derate above 25oC 0.5 W/oC -55 to 175 oC Operating and Storage Temperature Thermal Characteristics RθJC Thermal Resistance Junction to Case TO-252 2.0 o C/W RθJA Thermal Resistance Junction to Ambient TO-252 100 o C/W RθJA Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52 oC/W This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. ©2011 Fairchild Semiconductor Corporation FDD26AN06A0_F085 Rev. C1 PowerTrench® MOSFET FDD26AN06A0_F085 N-Channel " Aug 2011 Device Marking FDD26AN06A0 Device FDD26AN06A0_F085 Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units Electrical Characteristics TC = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units 60 - - - V - 1 - - 250 VGS = ±20V - - ±100 nA V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 50V VGS = 0V TC = 150oC µA On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250µA 2 - 4 ID = 36A, VGS = 10V - 0.020 0.026 ID = 36A, VGS = 10V, TJ = 175oC - 0.045 0.058 - 800 - - 155 - pF - 55 - pF nC Ω Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V Qg(TH) Threshold Gate Charge VGS = 0V to 2V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain “Miller” Charge Switching Characteristics VDS = 25V, VGS = 0V, f = 1MHz VDD = 30V ID = 36A Ig = 1.0mA pF - 13 17 - 1.7 2.2 nC - 4.3 - nC - 2.6 - nC - 4.6 - nC ns (VGS = 10V) tON Turn-On Time - - 123 td(ON) Turn-On Delay Time - 9 - ns tr Rise Time - 72 - ns td(OFF) Turn-Off Delay Time - 23 - ns tf Fall Time - 35 - ns tOFF Turn-Off Time - - 88 ns ISD = 36A - - 1.25 V ISD = 18A - - 1.0 V VDD = 30V, ID = 36A VGS = 10V, RGS = 25Ω Drain-Source Diode Characteristics VSD Source to Drain Diode Voltage trr Reverse Recovery Time ISD = 36A, dISD/dt = 100A/µs - - 43 ns QRR Reverse Recovered Charge ISD = 36A, dISD/dt = 100A/µs - - 50 nC Notes: 1: Starting TJ = 25°C, L = 83µH, IAS = 29A, VDD = 54V, VGS = 10V. ©2011 Fairchild Semiconductor Corporation FDD26AN06A0_F085 Rev. C1 FDD26AN06A0_F085 N-Channel PowerTrench® MOSFET Package Marking and Ordering Information 40 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 30 20 10 0.2 0 0 0 25 50 75 100 150 125 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Case Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 500 TC = 25oC IDM, PEAK CURRENT (A) TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V 100 30 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability ©2011 Fairchild Semiconductor Corporation FDD26AN06A0_F085 Rev. C1 FDD26AN06A0_F085 N-Channel PowerTrench® MOSFET Typical Characteristics TC = 25°C unless otherwise noted 1000 300 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10µs 100µs 10ms 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5. Forward Bias Safe Operating Area 100 100 ID, DRAIN CURRENT (A) VGS = 20V 60 -55oC TJ = 175oC 40 20 VGS = 10V VGS = 7V 80 60 VGS = 6V 40 20 0 VGS = 5V TC = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 3 4 5 6 7 8 9 0 1 2 3 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 19.5 19.0 18.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V VGS = 10V, ID = 36A 18.0 0 10 20 30 ID, DRAIN CURRENT (A) 40 Figure 9. Drain to Source On Resistance vs Drain Current ©2011 Fairchild Semiconductor Corporation 4 Figure 8. Saturation Characteristics 20.0 DRAIN TO SOURCE ON RESISTANCE(mΩ) 10 Figure 6. Unclamped Inductive Switching Capability TJ = 25oC TJ = 0.1 1 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 80 ID , DRAIN CURRENT (A) 1 0.01 100 0.5 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature FDD26AN06A0_F085 Rev. C1 ® FDD26AN06A0_F085 N-Channel PowerTrench MOSFET Typical Characteristics TC = 25°C unless otherwise noted 1.15 1.2 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250µA 1.0 0.8 0.6 0.4 -80 -40 0 40 80 12 TJ, JUNCTION TEMPERATURE 160 1.05 1.00 0.95 0.90 -80 200 -40 (oC) 0 40 80 120 TJ , JUNCTION TEMPERATURE Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 160 200 (oC) Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 2000 10 VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + CGD 1000 C, CAPACITANCE (pF) 1.10 COSS ≅ CDS + CGD CRSS = CGD 100 VGS = 0V, f = 1MHz 30 0.1 VDD = 30V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 36A ID = 7A 2 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs Drain to Source Voltage ©2011 Fairchild Semiconductor Corporation 60 0 2 4 6 8 10 12 14 Qg, GATE CHARGE (nC) Figure 14. Gate Charge Waveforms for Constant Gate Current FDD26AN06A0_F085 Rev. C1 FDD26AN06A0_F085 N-Channel PowerTrench® MOSFET Typical Characteristics TC = 25°C unless otherwise noted VDS BVDSS tP L VDS VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS RL VDD Qg(TOT) VDS VGS VGS VGS = 10V + Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 18. Gate Charge Waveforms Figure 17. Gate Charge Test Circuit VDS tON tOFF td(ON) td(OFF) RL tf tr VDS 90% 90% + VGS VDD - 10% 10% 0 DUT 90% RGS VGS VGS 0 Figure 19. Switching Time Test Circuit ©2011 Fairchild Semiconductor Corporation 50% 10% 50% PULSE WIDTH Figure 20. Switching Time Waveforms FDD26AN06A0_F085 Rev. C1 FDD26AN06A0_F085 N-Channel PowerTrench® MOSFET Test Circuits and Waveforms (T –T ) JM A P DM = ----------------------------RθJA (EQ. 1) In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 125 RθJA = 33.32+ 23.84/(0.268+Area) EQ.2 RθJA = 33.32+ 154/(1.73+Area) EQ.3 RθJA (oC/W) 100 75 50 25 0.01 (0.0645) 0.1 (0.645) 1 10 (6.45) (64.5) AREA, TOP COPPER AREA in2 (cm2) Figure 21. Thermal Resistance vs Mounting Pad Area 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. 23.84 ( 0.268 + Area ) R θ JA = 33.32 + ------------------------------------- (EQ. 2) Area in Inches Squared 154 ( 1.73 + Area ) R θ JA = 33.32 + ---------------------------------- (EQ. 3) Area in Centimeters Squared ©2011 Fairchild Semiconductor Corporation FDD26AN06A0_F085 Rev. C1 ® FDD26AN06A0_F085 N-Channel PowerTrench MOSFET Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I55