FDB070AN06A0_F085
N-Channel PowerTrench® MOSFET
60V, 80A, 7mΩ
Features
Applications
• r DS(ON) = 6.1mΩ (Typ.), V GS = 10V, ID = 80A
• Motor / Body Load Control
• Qg(tot) = 51nC (Typ.), VGS = 10V
• ABS Systems
• Low Miller Charge
• Powertrain Management
• Low QRR Body Diode
• Injection Systems
• UIS Capability (Single Pulse and Repetitive Pulse)
• DC-DC converters and Off-line UPS
• Qualified to AEC Q101
• Distributed Power Architectures and VRMs
• RoHS Compliant
• Primary Switch for 12V and 24V systems
Formerly developmental type 82567
D
GATE
G
SOURCE
TO-263AB
DRAIN
(FLANGE)
S
FDB SERIES
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
60
Units
V
VGS
Gate to Source Voltage
± 20
V
Continuous (TC < 97oC, VGS = 10V)
80
A
Continuous (TA = 25oC, VGS = 10V, R θJA = 43oC/W)
15
A
Drain Current
ID
Pulsed
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 1)
Figure 4
A
190
mJ
Power dissipation
175
W
Derate above 25oC
1.17
W/oC
Operating and Storage Temperature
o
-55 to 175
C
Thermal Characteristics
oC/W
RθJC
Thermal Resistance Junction to Case TO-220,TO-263
RθJA
Thermal Resistance Junction to Ambient TO-220,TO-263 (Note 2)
62
o
C/W
RθJA
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
43
o
C/W
0.86
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
May 2012
Device Marking
FDB070AN06A0
Device
FDB070AN06A0_F085
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
60
-
-
-
-
1
-
-
250
VGS = ±20V
-
-
±100
nA
V
V DS = 50V
VGS = 0V
TC = 150oC
µA
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
2
-
4
ID = 80A, VGS = 10V
-
0.0061
0.007
ID = 80A, VGS = 10V,
TJ = 175oC
-
0.0127
0.015
-
3000
-
-
510
-
pF
-
230
-
pF
51
66
nC
-
5.4
7
nC
-
17
-
nC
-
11.6
-
nC
-
16
-
nC
ns
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
V DS = 25V, VGS = 0V,
f = 1MHz
VDD = 30V
ID = 80A
Ig = 1.0mA
pF
Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
256
td(ON)
Turn-On Delay Time
-
12
-
ns
tr
Rise Time
-
159
-
ns
td(OFF)
Turn-Off Delay Time
-
27
-
ns
tf
Fall Time
-
35
-
ns
tOFF
Turn-Off Time
-
-
93
ns
V
V DD = 30V, ID = 80A
VGS = 10V, RGS = 5.6Ω
Drain-Source Diode Characteristics
ISD = 80A
-
-
1.25
ISD = 40A
-
-
1.0
V
Reverse Recovery Time
ISD = 75A, dISD/dt = 100A/µs
-
-
34
ns
Reverse Recovered Charge
ISD = 75A, dISD/dt = 100A/µs
-
-
35
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 93µH, I AS = 64A.
2: Pulse width = 100s.
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
Package Marking and Ordering Information
1.2
120
CURRENT LIMITED
BY PACKAGE
100
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
80
60
40
20
0
0
0
25
50
75
100
150
125
25
175
50
75
TC , CASE TEMPERATURE (o C)
100
125
TC, CASE TEMPERATURE
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
150
175
(oC)
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
TC = 25oC
FOR TEMPERATURES
1000
IDM, PEAK CURRENT (A)
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
VGS = 10V
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
1000
500
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
10µs
100µs
100
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
10ms
DC
1
SINGLE PULSE
TJ = MAX RATED
TC = 25o C
100
STARTING TJ = 25oC
10
STARTING TJ = 150 oC
1
0.01
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
160
VGS = 10V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
100
Figure 6. Unclamped Inductive Switching
Capability
120
80
TJ = 25 oC
40
VGS = 7V
120
VGS = 6V
80
TC = 25o C
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
40
TJ = -55oC
VGS = 5V
0
0
4.0
4.5
5.0
5.5
6.0
6.5
VGS , GATE TO SOURCE VOLTAGE (V)
0
7.0
0.5
1.0
1.5
2.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
16
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE(mΩ)
10
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 175oC
1
tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area
160
0.1
14
12
VGS = 6V
10
8
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
VGS = 10V, ID =80A
6
0
20
40
60
ID, DRAIN CURRENT (A)
80
Figure 9. Drain to Source On Resistance vs Drain
Current
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
0.5
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (o C)
160
200
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.10
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
1.05
1.00
0.95
0.90
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
80
120
160
200
10
CISS = C GS + CGD
C, CAPACITANCE (pF)
40
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
VGS , GATE TO SOURCE VOLTAGE (V)
10000
COSS ≅ C DS + C GD
1000
CRSS = CGD
VGS = 0V, f = 1MHz
100
0.1
0
TJ , JUNCTION TEMPERATURE (o C)
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 80A
ID = 15A
2
0
60
0
10
20
30
40
50
60
Qg, GATE CHARGE (nC)
Figure 14. Gate Charge Waveforms for Constant
Gate Current
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDD
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
VGS
VGS = 10V
+
Qgs2
VDD
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
10%
Figure 20. Switching Time Waveforms
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
Test Circuits and Waveforms
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (o C/W)
(T
–T )
JM
A
P D M = ----------------------------R θ JA
80
40
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2 )
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
R
θ JA
19.84
( 0.262 + Area )
= 26.51 + -------------------------------------
(EQ. 2)
Area in Inches Squared
R
θ JA
128
( 1.69 + Area )
= 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeters Squared
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
5
51
ESLC
EVTHRES
+ 19 8
+
LGATE
GATE
1
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
Ebreak 11 7 17 18 62
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
DRAIN
2
5
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
Lgate 1 9 4.8e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 3e-9
LSOURCE
CIN
8
7
SOURCE
3
RSOURCE
RLSOURCE
RLgate 1 9 48
RLdrain 2 5 10
RLsource 3 7 3
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
14
13
S1B
CA
15
17
18
RVTEMP
S2B
13
CB
6
8
5
8
EDS
-
19
VBAT
+
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.3e-3
Rgate 9 20 2.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.1e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RBREAK
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))}
.MODEL DbodyMOD D (IS=7.6E-12 N=1.04 RS=2.2e-3 TRS1=2.7e-3 TRS2=2e-7
+ CJO=1.6e-9 M=0.55 TT=5e-12 XTI=3.9)
.MODEL DbreakMOD D (RS=8e-1 TRS1=5e-4 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.05e-9 IS=1e-30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=3.7 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.7)
.MODEL MstroMOD NMOS (VTO=4.7 KP=100 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.01 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27 RS=0.1)
.MODEL RbreakMOD RES (TC1=7.1e-4 TC2=-5.5e-7)
.MODEL RdrainMOD RES (TC1=1.7e-2 TC2=4e-5)
.MODEL RSLCMOD RES (TC1=3e-3 TC2=1e-5)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.2e-3 TC2=-1.5e-5)
.MODEL RvtempMOD RES (TC1=-3e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
PSPICE Electrical Model
.SUBCKT FDB070AN06A0 2 1 3 ; rev March 2003
Ca 12 8 1.5e-9
Cb 15 14 1.5e-9
Cin 6 8 2.9e-9
spe.ebreak n11 n7 n17 n18 = 62
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 4.8e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 3e-9
S2A
S1B
CA
res.rlgate n1 n9 = 48
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 3
15
14
13
13
8
RBREAK
17
18
RVTEMP
S2B
13
CB
+
-
IT
14
+
6
8
EGS
19
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=7.1e-4,tc2=-5.5e-7
res.rdrain n50 n16 = 1.3e-3, tc1=1.7e-2,tc2=4e-5
res.rgate n9 n20 = 2.7
res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.1e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.2e-3,tc2=-1.5e-5
res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10))
}
}
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
SABER Electrical Model
rev March 2003
template FDB070AN06A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=7.6e-12,nl=1.04,rs=2.2e-3,trs1=2.7e-3,trs2=2e-7,cjo=1.6e-9,m=0.55,tt=5e-12,xti=3.9)
dp..model dbreakmod = (rs=8e-1,trs1=5e-4,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.05e-9,isl=10e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=3.7,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.7,kp=100,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.01,kp=0.03,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2)
DPLCAP 5
DRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4)
2
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=0.5)
RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.5)
RSLC1
51
c.ca n12 n8 = 1.5e-9
RSLC2
c.cb n15 n14 = 1.5e-9
ISCL
c.cin n6 n8 = 2.9e-9
th
JUNCTION
FDB070AN06A0T
CTHERM1 TH 6 3.5e-3
CTHERM2 6 5 1.7e-2
CTHERM3 5 4 1.8e-2
CTHERM4 4 3 1.9e-2
CTHERM5 3 2 4.7e-2
CTHERM6 2 TL 7e-2
CTHERM1
RTHERM1
6
RTHERM1 TH 6 2e-2
RTHERM2 6 5 7e-2
RTHERM3 5 4 1e-1
RTHERM4 4 3 1.5e-1
RTHERM5 3 2 1.6e-1
RTHERM6 2 TL 1.85e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDB070AN06A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.5e-3
ctherm.ctherm2 6 5 =1.7e-2
ctherm.ctherm3 5 4 =1.8e-2
ctherm.ctherm4 4 3 =1.9e-2
ctherm.ctherm5 3 2 =4.7e-2
ctherm.ctherm6 2 tl =7e-2
rtherm.rtherm1 th 6 =2e-2
rtherm.rtherm2 6 5 =7e-2
rtherm.rtherm3 5 4 =1e-1
rtherm.rtherm4 4 3 =1.5e-1
rtherm.rtherm5 3 2 =1.6e-1
rtherm.rtherm6 2 tl =1.85e-1
}
CTHERM3
RTHERM3
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
CASE
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
PSPICE Thermal Model
REV 23 March 2003
tm
tm
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2.
A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
www.Fairchildsemi.com, under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild
Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of
up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and
warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is
committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative / In Design
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Definition
Preliminary
First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
No Identification Needed
Full Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete
Not In Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I61
©2012 Fairchild Semiconductor Corporation
FDB070AN06A0_F085 Rev. B1
www.fairchildsemi.com
FDB070AN06A0_F085 N-Channel PowerTrench ® MOSFET
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
F-PFS™
The Power Franchise®
PowerTrench®
2Cool™
®
PowerXS™
FRFET®
AccuPower™
Programmable Active Droop™
Global Power ResourceSM
AX-CAP™*
Green Bridge™
QFET®
BitSiC®
TinyBoost™
Build it Now™
QS™
Green FPS™
TinyBuck™
CorePLUS™
Quiet Series™
Green FPS™ e-Series™
TinyCalc™
CorePOWER™
RapidConfigure™
Gmax™
TinyLogic®
CROSSVOLT™
GTO™
™
TINYOPTO™
CTL™
IntelliMAX™
TinyPower™
Saving our world, 1mW/W/kW at a time™
Current Transfer Logic™
ISOPLANAR™
TinyPWM™
DEUXPEED®
Marking Small Speakers Sound Louder SignalWise™
TinyWire™
Dual Cool™
SmartMax™
and Better™
TranSiC®
EcoSPARK®
SMART START™
MegaBuck™
TriFault Detect™
EfficentMax™
Solutions for Your Success™
MICROCOUPLER™
TRUECURRENT®*
ESBC™
SPM®
MicroFET™
μSerDes™
STEALTH™
MicroPak™
®
SuperFET®
MicroPak2™
SuperSOT™-3
MillerDrive™
Fairchild®
UHC®
SuperSOT™-6
MotionMax™
Fairchild Semiconductor®
Ultra FRFET™
SuperSOT™-8
Motion-SPM™
FACT Quiet Series™
UniFET™
SupreMOS®
mWSaver™
FACT®
VCX™
SyncFET™
OptoHiT™
FAST®
VisualMax™
Sync-Lock™
OPTOLOGIC®
FastvCore™
VoltagePlus™
OPTOPLANAR®
®*
FETBench™
XS™
FlashWriter® *
®
FPS™