M48Z09
M48Z19
CMOS 8K x 8 ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
POWER-FAIL INTERRUPT
CHOICE of TWO WRITE PROTECT
VOLTAGES:
– M48Z09: 4.5V ≤ VPFD ≤ 4.75V
– M48Z19: 4.2V ≤ VPFD ≤ 4.5V
SELF CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
11 YEARS of DATA RETENTION in the
ABSENCE of POWER
PIN and FUNCTION COMPATIBLE with the
MK48Z09, 19 and JEDEC STANDARD 8K x 8
SRAMs
DESCRIPTION
The M48Z09,19 ZEROPOWER® RAM is an 8K x 8
non-volatile static RAM which is pin and function
compatible with the MK48Z09,19.
A special 28 pin 600mil DIP CAPHAT package
houses the M48Z09,19 silicon with a long life lithium button cell to form a highly integrated battery
backed-up memory solution.
28
1
PCDIP28 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
VCC
13
8
A0-A12
DQ0-DQ7
W
Table 1. Signal Names
E1
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
INT
Power Fail Interrupt
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
November 1994
M48Z09
M48Z19
INT
E2
G
VSS
AI01184
1/13
M48Z09, M48Z19
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature (VCC Off)
–40 to 85
°C
VIO
Input or Output Voltages
–0.3 to 7
V
VCC
Supply Voltage
–0.3 to 7
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability.
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode
VCC
E1
E2
G
W
DQ0-DQ7
Power
VIH
X
X
X
High Z
Standby
X
VIL
X
X
High Z
Standby
VIL
VIH
X
VIL
DIN
Active
Read
VIL
VIH
VIL
VIH
DOUT
Active
Read
VIL
VIH
VIH
VIH
High Z
Active
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
Deselect
Write
Deselect
VSO to VPFD (min)
X
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO
X
X
X
X
High Z
Battery Back-up Mode
Note: X = VIH or VIL
Figure 2A. DIP Pin Connections
INT
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
27
2
26
3
25
4
24
5
23
6
7
M48Z09 22
M49Z19 21
8
20
9
19
10
18
11
17
12
13
16
14
15
AI01185
2/13
DESCRIPTION (cont’d)
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
The M48Z09,19 button cell has sufficient capacity
and storage life to maintain data for an accumulated time period of at least 11 years in the absence
of power over the operating temperature range.
The M48Z09,19 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z09,19 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
M48Z09, M48Z19
Figure 3. Block Diagram
A0-A12
DQ0-DQ7
LITHIUM
CELL
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8K x 8
SRAM ARRAY
E1
E2
VPFD
W
G
VCC
INT
READ MODE
The M48Z09,19 is in the Read Mode whenever W
(Write Enable) is high, E1 (Chip Enable 1) is low,
and E2 (Chip Enable 2) is high. The device architecture allows ripple- through access of data from
eight of 65,536 locations in the static storage array.
Thus, the unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be available at the Data I/O pins within tAVQV (Address
Access Time) after the last address input signal is
stable, providing that the E1, E2, and G access
times are also satisfied. If the E1, E2 and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tE1LQV
or tE2HQV) or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Address
Inputs are changed while E1, E2 and G remain
active, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until
the next Address Access.
VSS
AI01397
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL includes JIG capacitance
CL = 100pF or 30pF
AI01398
3/13
M48Z09, M48Z19
Table 4. Capacitance (1) (TA = 25 °C)
Symbol
CIN
CIO
(2)
Parameter
Test Condition
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
Notes: 1. Effective capacitance calculated from the equation C = I∆t/∆V with ∆V = 3V and power supply at 5V.
2. Outputs deselected
Table 5. DC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±5
µA
Outputs open
80
mA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
E1 = VIH, E2 = VIL
3
mA
ICC2
Supply Current (Standby) CMOS
E1 = VCC – 0.2V,
E2 = VSS + 0.2V
3
mA
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
IOL = 2.1mA
0.4
V
IOL = 0.5mA
0.4
V
VOL
Output Low Voltage
Output Low Voltage (INT)
VOH
(1)
Output High Voltage
IOH = –1mA
2.4
V
Note: 1. The INT pin is Open Drain.
Table 6. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C)
Symbol
Parameter
Typ
Max
Unit
VPFD
Power-fail Deselect Voltage (M48Z09)
4.5
4.6
4.75
V
VPFD
Power-fail Deselect Voltage (M48Z19)
4.2
4.3
4.5
V
VSO
Battery Back-up Switchover Voltage
tDR
Expected Data Retention Time
Note: 1. All voltages referenced to VSS.
4/13
Min
3.0
11
V
YEARS
M48Z09, M48Z19
Table 7. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C)
Symbol
Parameter
Min
Max
Unit
0
µs
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
VPFD (min) to VSO VCC Fall Time
10
µs
tR
VPFD(min) to VPFD (max) VCC Rise Time
0
µs
tRB
VSO to VPFD (min) VCC Rise Time
1
µs
tREC
E1 or W at VIH or E2 at VIL after Power Up
1
ms
tPFX
INT Low to Auto Deselect
10
E1 or W at VIH or E2 at VIL before Power Down
tPD
tF
(1)
tFB (2)
(3)
tPFH
VPFD (max) to INT High
40
µs
120
µs
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
3. INT may go high anytime after VCC exceeds VPFD (min) and is guaranteed to go high tPFH after VCC exceeds VPFD (max).
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tDR
tF
tPD
tR
tRB
tFB
tPFX
tPFH
INT
tREC
INPUTS
RECOGNIZED
DON'T CARE
NOTE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00566
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD(min).
Some systems may performs inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begins. Even
though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running.
5/13
M48Z09, M48Z19
Table 8. Read Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z09 / 19
Symbol
Parameter
Min
tAVAV
Unit
-100
Read Cycle Time
Max
100
ns
tAVQV
(1)
Address Valid to Output Valid
100
ns
tE1LQV
(1)
Chip Enable 1 Low to Output Valid
100
ns
tE2HQV
(1)
Chip Enable 2 High to Output Valid
100
ns
Output Enable Low to Output Valid
50
ns
(1)
tGLQV
tE1LQX (2)
tE2HQX
(2)
Chip Enable 1 Low to Output Transition
10
ns
Chip Enable 2 High to Output Transition
10
ns
tGLQX
(2)
Output Enable Low to Output Transition
5
ns
tE1HQZ
(2)
Chip Enable 1 High to Output Hi-Z
50
ns
tE2LQZ
(2)
Chip Enable 2 Low to Output Hi-Z
50
ns
tGHQZ
(2)
Output Enable High to Output Hi-Z
40
ns
tAXQX
(1)
Address Transition to Output Transition
5
ns
Notes: 1. CL= 100pF (see Figure 4).
2. CL= 30pF (see Figure 4)
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A12
tAVQV
tAXQX
tE1LQV
tE1HQZ
E1
tE1LQX
tE2HQV
tE2LQZ
E2
tE2HQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00962
6/13
M48Z09, M48Z19
Table 9. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z09 / 19
Symbol
Parameter
Min
tAVAV
Write Cycle Time
tAVWL
Unit
-100
Max
100
ns
Address Valid to Write Enable Low
0
ns
tAVE1L
Address Valid to Chip Enable 1 Low
0
ns
tAVE2H
Address Valid to Chip Enable 2 High
0
ns
tWLWH
Write Enable Pulse Width
80
ns
tE1LE1H
Chip Enable 1 Low to Chip Enable 1 High
80
ns
tE2HE2L
Chip Enable 2 High to Chip Enable 2 Low
80
ns
tWHAX
Write Enable High to Address Transition
10
ns
tE1HAX
Chip Enable 1 High to Address Transition
10
ns
tE2LAX
Chip Enable 2 Low to Address Transition
10
ns
tDVWH
Input Valid to Write Enable High
50
ns
tDVE1H
Input Valid to Chip Enable 1 High
50
ns
tDVE2L
Input Valid to Chip Enable 2 Low
50
ns
tWHDX
Write Enable High to Input Transition
5
ns
tE1HDX
Chip Enable 1 High to Input Transition
5
ns
tE2LDX
Chip Enable 2 Low to Input Transition
5
ns
tWLQZ
(1, 2)
Write Enable Low to Output Hi-Z
50
ns
tAVWH
Address Valid to Write Enable High
80
ns
tAVE1H
Address Valid to Chip Enable 1 High
80
ns
tAVE2L
Address Valid to Chip Enable 2 Low
80
ns
Write Enable High to Output Transition
10
ns
tWHQX
(1, 2)
Notes: 1. CL= 30pF (see Figure 4).
2. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
7/13
M48Z09, M48Z19
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
VALID
A0-A12
tAVWH
tWHAX
tAVE1L
E1
tAVE2H
E2
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00963
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVE1H
tAVE1L
tE1LE1H
tE1HAX
E1
tAVE2L
tAVE2H
tE2HE2L
tE2LAX
E2
tAVWL
W
tE1HDX
tE2LDX
DQ0-DQ7
DATA INPUT
tDVE1H
tDVE2L
8/13
AI00964B
M48Z09, M48Z19
WRITE MODE
The M48Z09,19 is in the Write Mode whenever W,
E1, and E2 are active. The start of a write is referenced from the latter occurring falling edge of W or
E1, or the rising edge of E2. A write is terminated
by the earlier rising edge of W or E1, or the falling
edge of E2. The addresses must be held valid
throughout the cycle. E1 or W must return high or
E2 low for minimum of tE1HAX or tE2LAX from Chip
Enable or tWHAX from Write Enable prior to the
initiation of another read or write cycle. Data-in
must be valid tDVWH prior to the end of write and
remain valid for tWHDX afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E1 and G and a high on E2, a low on W will
disable the outputs tWLQZ after W falls.
DATA RETENTION MODE
With valid VCC applied, the M48Z09,19 operates as
a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself
when VCC falls within the VPFD(max), VPFD(min)
window. All outputs become high impedance, and
all inputs are treated as "don’t care."
Note: A power failure during a write cycle may
corrupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD(min), the user can be assured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48Z09,19 may respond to transient noise spikes
on VCC that reach into the deselect window during
the time the device is sampling VCC. Therefore,
decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which preserves data and powers the clock. The internal
button cell will maintain data in the M48Z09,19 for
an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches
VPFD(min). E1 should be kept high or E2 low as
VCC rises past VPFD(min) to prevent inadvertent
write cycles prior to processor stabilization. Normal
RAM operation can resume tREC after VCC exceeds
VPFD(max).
POWER FAIL INTERRUPT PIN
The M48Z09,19 continuously monitors VCC. When
VCC falls to the power-fail detect trip point, an
interrupt is immediately generated. An internal
clock provides a delay of between 10µs and 40µs
before automatically deselecting the M48Z09,19.
The INT pin is an open drain output and requires
an external pull up resistor, even if the interrupt
output function is not being used.
SYSTEM BATTERY LIFE
The useful life of the battery in the M48Z09,19 is
expected to ultimately come to an end for one of
two reasons: either because it has been discharged
while providing current to the RAM in the battery
back-up mode, or because the effects of aging
render the cell useless before it can actually be
completely discharged. The two effects are virtually
unrelated allowing discharge, or Capacity Consumption, and the effects of aging, or Storage Life,
to be treated as two independent but simultaneous
mechanisms. The earlier occurring failure mechanism defines the battery system life of the
M48Z09,19.
Cell Storage Life
Storage life is primarily a function of temperature.
Figure 9 illustrates the approximate storage life of
the M48Z09,19 battery over temperature. The results in Figure 9 are derived from temperature
accelerated life test studies performed at SGSTHOMSON. For the purpose of the testing, a cell
failure is defined as the inability of a cell stabilized
at 25°C to produce a 2.4V closed circuit voltage
across a 250 kΩ load resistor. The two lines, t1%
and t50%, represent different failure rate distributions for the cell’s storage life. At 70°C, for example,
the t1% line indicates that an M48Z09,19 has a 1%
chance of having a battery failure 28 years into its
life while the t50% shows the part has a 50% chance
of failure at the 50 year mark. The t1% line represents the practical onset of wear out and can be
considered the worst case Storage Life for the cell.
The t50% can be considered the normal or average
life.
9/13
M48Z09, M48Z19
Calculating Storage Life
The following formula can be used to predict storage life:
1
{[(TA1/TT)/SL1]+[(TA2/TT)/SL2]+...+[(TAN/TT)/SLN]}
where,
– TA1, TA2, TAN = time at ambient temperature
1, 2, etc.
– TT = total time = TA1+TA2+...+TAN
– SL1, SL2, SLN = storage life at temperature 1,
2, etc.
For example an M48Z09,19 is exposed to temperatures of 55°C or less for 8322 hrs/yr, and temperatures greater than 60°C but less than 70°C for the
remaining 438 hrs/yr. Reading predicted t1% values
from Figure 9,
– SL1 ≅ 200 yrs, SL2 = 28 yrs
– TT = 8760 hrs/yr
– TA1 = 8322 hrs/yr, TA2 = 438 hrs/yr
Predicted storage life ≥
1
{[(8322/8760)/200]+[(431/8760)/28]}
or 154 years.
As can be seen from these calculations and the
results, the expected life time of the M48Z09, 19
should exceed most system requirements.
Estimated System Life
Since either storage life or capacity consumption
can end the battery’s life, the system life is marked
by which ever occurs first.
Reference for System Life
Each M48Z09,19 is marked with a nine digit manufacturing date code in the form of H99XXYYZZ. For
example, H995B9431 is:
H = fabricated in Carrollton, TX
9 = assembled in Muar, Malaysia,
9 = tested in Muar, Malaysia,
5B = lot designator,
9431 = assembled in the year 1994, work week 31.
Figure 9. Predicted Battery Storage Life versus Temperature
AI01399
50
40
t50% (AVERAGE)
30
t1%
20
YEARS
10
8
6
5
4
3
2
1
20
30
40
50
60
TEMPERATURE (Degrees Celsius)
10/13
70
80
90
M48Z09, M48Z19
ORDERING INFORMATION SCHEME
Example:
M48Z09
Supply Voltage and Write
Protect Voltage
09
VCC = 4.75V to 5.5V
VPFD = 4.5V to 4.75V
19
VCC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
-100 PC
1
Speed
-100
100ns
Package
PC
PCDIP28
Temp. Range
1
0 to 70 °C
For a list of available options (Supply Voltage, Speed, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
11/13
M48Z09, M48Z19
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
mm
Symb
Typ
inches
Min
Max
A
8.89
A1
Typ
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
29.72
36.32
1.170
1.430
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
28
PCDIP28
A2
A1
B1
B
e1
A
L
C
eA
e3
D
N
E
1
Drawing is not to scale
12/13
PCDIP
M48Z09, M48Z19
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1994 SGS-THOMSON Microelectronics - All Rights Reserved
® ZEROPOWER is a registered trademark of SGS-THOMSON Microelectronics
CAPHAT and BYTEWIDE are trademarks of SGS-THOMSON Microelectronics
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
13/13