SG2525A SG3525A .. .. .. .. . . REGULATING PULSE WIDTH MODULATORS 8 TO 35 V OPERATION 5.1 V REFERENCE TRIMMED TO ± 1 % 100 Hz TO 500 KHz OSCILLATOR RANGE SEPARATE OSCILLATOR SYNC TERMINAL ADJUSTABLE DEADTIME CONTROL INTERNAL SOFT-START PULSE-BY-PULSE SHUTDOWN INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LATCHING PWM TO PREVENT MULTIPLE PULSES DUAL SOURCE/SINK OUTPUT DRIVERS DESCRIPTION The SG3525Aseries of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to ± 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor betweenthe CT andthe dischargeterminals provide a wide range of dead time ad- justment. Thesedevicesalso featurebuilt-insoft-startcircuitry with only an external timing capacitor required. A shutdownterminal controls both the soft-start circuity and the output stages, providing instantaneous DIP16 16(Narrow) turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltagelockoutwhich keepsthe outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includesapproximately 500 mV of hysteresisfor jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525Aoutputstage features NOR logic, giving a LOW output for an OFF state. PIN CONNECTIONS AND ORDERING NUMBERS (top view) June 2000 Type Plastic DIP SO16 SG2525A SG2525AN SG2525AP SG3525A SG3525AN SG3525AP 1/12 SG2525A-SG3525A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V Vi Supply Voltage 40 VC Collector Supply Voltage 40 V Oscillator Charging Current 5 mA mA IOSC Io Output Current, Source or Sink 500 IR Reference Output Current 50 mA IT Current through CT Terminal Logic Inputs Analog Inputs 5 – 0.3 to + 5.5 – 0.3 to Vi mA V V 1000 mW P tot Total Power Dissipation at Tamb = 70 °C Tj Junction Temperature Range – 55 to 150 °C Tstg Storage Temperature Range – 65 to 150 °C Top Operating Ambient Temperature : SG2525A SG3525A – 25 to 85 0 to 70 °C °C THERMAL DATA Symbol Rth j-pins Rth j-amb R th j-alumina Parameter Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Thermal Resistance Junction-alumina (*) SO16 Max Max Max 50 DIP16 Unit 50 80 °C/W °C/W °C/W * Thermalresistance junction-alumina with the device soldered on themiddle ofan alumina supporting substrate measuring 15 × 20 mm ; 0.65mm thickness with infinite heatsink. BLOCK DIAGRAM 2/12 SG2525A-SG3525A ELECTRICAL CHARACTERISTICS (V# i = 20 V, and over operating temperature, unless otherwise specified) Symbol Parameter SG2525A Test Conditions SG3525A Unit Min. Typ. Max. Min. Typ. Max. 5.05 5.1 5.15 5 5.1 5.2 V REFERENCE SECTION VREF Output Voltage Tj = 25 °C ∆V REF Line Regulation Vi = 8 to 35 V 10 20 10 20 mV ∆V REF Load Regulation IL = 0 to 20 mA 20 50 20 50 mV Over Operating Range 20 50 20 50 mV 5.25 V ∆VREF/∆T* Temp. Stability * * ∆VREF* Total Output Variation Line, Load and Temperature 5 5.2 4.95 Short Circuit Current VREF = 0 Tj = 25 °C 80 100 80 100 mA Output Noise Voltage 10 Hz ≤f ≤ 10 kHz, Tj = 25 °C 40 200 40 200 µVrms Long Term Stability Tj = 125 °C, 1000 hrs 20 50 20 50 mV OSCILLATOR SECTION * * *, • Initial Accuracy Tj = 25 °C *, • Voltage Stability Vi = 8 to 35 V ∆f/∆T* Temperature Stability Over Operating Range fMIN Minimum Frequency RT = 200 KΩ CT = 0.1 µF fMAX Maximum Frequency RT = 2 KΩ CT = 470 pF 400 Current Mirror IRT = 2 mA 1.7 2 3 3.5 0.3 0.5 1.2 2 1 2.5 *, • *, • Clock Amplitude Clock Width Tj = 25 °C Sync Threshold Sync Input Current ±2 ±6 ±2 ±6 % ± 0.3 ±1 ±1 ±2 % ±6 ±3 ±3 120 Sync Voltage = 3.5 V ±6 % 120 Hz 400 2.2 KHz 1.7 2 3 3.5 2.2 mA 1 0.3 0.5 1 µs 2.8 1.2 2 2.8 V 1 2.5 mA V ERROR AMPLIFIER SECTION (VCM = 5.1 V) VOS Ib Ios * *, ❚ Input Offset Voltage Input Bias Current 0.5 5 2 10 mV 1 10 1 10 µA 1 µA Input Offset Current 1 DC Open Loop Gain RL ≥ 10 MΩ Gain Bandwidth Product Gv = 0 dB DC Transconduct. 30 KΩ ≤ RL ≤ 1 MΩ Tj = 25 °C T j = 25 °C 60 75 60 75 dB 1 2 1 2 MHz 1.1 1.5 1.1 1.5 ms Output Low Level 0.2 Output High Level 0.5 0.2 0.5 V 3.8 5.6 3.8 5.6 V CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB PSR Supply Voltage Rejection Vi = 8 to 35 V 50 60 50 60 dB 3/12 SG2525A-SG3525A ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter SG2525A Test Conditions Min. Typ. SG3525A Max. Min. Typ. Unit Max. PWM COMPARATOR Minimum Duty-cycle • Maximum Duty-cycle • Input Threshold * Input Bias Current 0 Zero Duty-cycle 0 % 45 49 45 49 % 0.7 0.9 0.7 0.9 V Maximum Duty-cycle 3.3 3.6 3.3 3.6 V 0.05 1 0.05 1 µA 50 80 50 80 µA 0.4 0.7 0.4 0.7 V 0.8 1 0.8 1 V SHUTDOWN SECTION Soft Start Current VSD = 0 V, VSS = 0 V Soft Start Low Level VSD = 2.5 V Shutdown Threshold To outputs, VSS = 5.1 V Tj = 25 °C 25 0.6 Shutdown Input Current VSD = 2.5 V * Shutdown Delay VSD = 2.5 V Tj = 25 °C 25 0.6 0.4 1 0.4 1 mA 0.2 0.5 0.2 0.5 µs 0.2 0.4 0.2 0.4 V 1 2 1 2 V OUTPUT DRIVERS (each output) (VC = 20 V) Output Low Level Isink = 20 mA Isink = 100 mA Output High Level Under-Voltage Lockout Isource = 20 mA 18 19 Isource = 100 mA 17 18 Vcomp and Vss = High 6 7 8 18 19 17 18 6 7 V V 8 V IC Collector Leakage VC = 35 V 200 µA tr* Rise Time C L = 1 nF, Tj = 25 °C 100 600 100 600 ns t f* Fall Time C L = 1 nF, Tj = 25 °C 50 300 50 300 ns 14 20 14 20 mA 200 TOTAL STANDBY CURRENT Is Supply Current Vi = 35 V * These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production. • Tested at fosc = 40 KHz (RT = 3.6 KΩ, CT = 10nF, RD = 0 Ω). Approximate oscillator frequency is defined by : f= 1 CT (0.7 RT + 3 RD) . DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : G v = gM RL whereRL is the resistance from pin 9 to ground. The minimum g M specification is used to calculate minimum G v when the error amplifier output is loaded. 4/12 SG2525A-SG3525A TEST CIRCUIT 5/12 SG2525A-SG3525A RECOMMENDED OPERATING CONDITIONS (•) Parameter Value Input Voltage (Vi) 8 to 35 V Collector Supply Voltage (VC) 4.5 to 35 V Sink/Source Load Current (steady state) 0 to 100 mA Sink/Source Load Current (peak) 0 to 400 mA Reference Load Current 0 to 20 mA Oscillator Frequency Range 100 Hz to 400 KHz Oscillator Timing Resistor 2 KΩ to 150 KΩ 0.001 µF to 0.1 µF 0 to 500 Ω Oscillator Timing Capacitor Dead Time Resistor Range • ⋅ ( ) Range over which the device is functional and parameter limits are guaranteed. Figure 1 : Oscillator Charge Time vs. RT and C T . Figure 2 : Oscillator Discharge Time vs. RD and C T . Figure 3 : Output Saturation Characteristics. Figure 4 : Error Amplifier Voltage Gain and Phase vs. Frequency. 6/12 SG2525A-SG3525A Figure 5 : Error Amplifier. PRINCIPLES OF OPERATION SHUTDOWN OPTIONS (see Block Diagram) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100 µA to turn off the outputs.This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternateapproachis the useof the shutdowncircuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions : the PWM latch is immedi- ately set providing the fastest turn-off signal to the outputs ; and a 150 µA current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. 7/12 SG2525A-SG3525A Figure 6 : Oscillator Schematic. Figure 7 : Output Circuit (1/2 circuit shown). 8/12 SG2525A-SG3525A Figure 8. Figure 9. For single-ended supplies, the driver outputs are grounded.The VC terminal is switched to groundby the totem-pole source transistors on alternate oscillator cycles. In conventional push-pull bipolar designs, forward base drive is controlled by R1 - R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2. Figure 10. Figure 11. Thelow source impedanceof the outputdrivers provides rapid charging of Power Mos input capacitance while minimizing external components. Low power transformers can be driven directly. Automaticresetoccurs duringdeadtime, whenboth ends of the primary winding are switched to ground. 9/12 SG2525A-SG3525A mm DIM. MIN. a1 0.51 B 0.77 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 10/12 OUTLINE AND MECHANICAL DATA 3.3 0.130 1.27 DIP16 0.050 SG2525A-SG3525A mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.009 0.004 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 c1 0.020 45° (typ.) D (1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M S OUTLINE AND MECHANICAL DATA 0.62 0.024 SO16 Narrow 8°(max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 11/12 SG2525A-SG3525A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 12/12