ST3L01 TRIPLE VOLTAGE REGULATOR ■ ■ ■ ■ ■ ■ ■ DUAL INPUT VOLTAGE (12V AND 5V) TRIPLE OUTPUT VOLTAGE (2.6V, 3.3V, 8V) 2.6V GUARANTEED IOUT UP TO 1.2A 3.3V GUARANTEED IOUT UP TO 1.0A 8V GUARANTEED IOUT UP TO 200mA THERMAL AND SHORT CIRCUIT PROTECTION GUARANTEED OPERATING TEMPERATURE RANGE (0°C to 125°C) DESCRIPTION This device contains three voltage regulators, all fixed output voltage, in one 7 pin surface mount package. The first is a 2.6 V regulator to power the integrated controller/µP. The second is a 3.3V regulator to power the read channel chip, and memory chips requiring 3.3V The last is an 8V regulator to power the preamp chip. The bandgap reference, the 8V ground, and the substrate are all tied to a common ground pin, while the 2.6V and 3.3V ground is tied to a separate ground pin.This SPAK-7L (PowerFlex) grounding scheme allows for improved noise isolation between the 8V regulator and the 2.6V and 3.3V regulators.The 2.6V and 3.3V regulators shall be respectively capable of 1.0A and 1.2A. The 8V regulator shall be capable of 200mA. It is housed in the SPAK (PowerFlex) SCHEMATIC DIAGRAM V2.6 March 2002 1/12 ST3L01 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage 18 V VDD ISupply Voltage 18 V VESD ESD Tolerance (Human Body Model) Tstg Storage Temperature Range TJ Operating Junction Temperature Range 4 KV -65 to +150 °C 0 to +150 °C Value Unit GENERAL OPERATING CONDITION Symbol VCC ∆VCC Parameter VCC Supply Voltage VCC Ripple 4.75 to 5.25 V ±0.15 V tr Rise Time (10% to 90%) referred to VCC 1 V tf Fall Time (90% to 10%) referred to VCC VDD Supply Voltage 1 V VDD ∆VDD VDD Ripple 10.8 to 13.2 V ±0.3 V tr Rise Time (10% to 90%) referred to VDD 1 V tf Fall Time (90% to 10%) referred to VDD Operating Ambient Temperature Range 1 V 0 to 70 µs SPAK-7L Unit 2 °C/W TAl THERMAL DATA Symbol Rthj-case Parameter Thermal Resistance Junction-case CONNECTION DIAGRAM (top view) PIN DESCRIPTION Pin N° Symbol 1 SPAK-7L Name and Function GND1,2 VO1 and VO2 regulators GND pin 2 VO2 3 VCC 4 GND3 5 VO3 6 VDD 7 VO1 Second Output Pin: Bypass with a 0.1µF capacitor to GND Input Pin: Bypass with a 0.1µF capacitor to GND VO3 regulators GND pin Third Output Pin: Bypass with a 0.1µF capacitor to GND Input Pin: Bypass with a 0.1µF capacitor to GND First Output Pin: Bypass with a 0.1µF capacitor to GND ORDERING INFORMATION TYPE SPAK (Power Flex) 7 leads (*) ST3L01 ST3L01K7 (*) Available in Tape & Reel with the suffix "R" 2/12 ST3L01 TYPICAL APPLICATION CIRCUIT Note: To improve noise figure of the 8V VREG connect this capacitor to the GND8V pin. CCC, CDD, CO1, CO2 and CO3 capacitors must be located not more than 0.5" from the output pins of the device. Form more details about Capacitors read the "Application Hints" ELECTRICAL CHARACTERISTICS (VCC=5V, VDD=12V, CCC=1µF (Tantalum), C DD=0.1µF (X7R), CO1=CO2=C O3=0.11µF (X7R) Tj=0 to 125°C unless otherwise specified. Typical values are referred at Tj=25°C, IFL1 =1.2A, IFL2 =1.0A, IFL3 =0.2A, Symbol VO1 VO2 VO3 Parameter Output Voltage 1 Output Voltage 2 Output Voltage 3 Test Conditions Min. Typ. Max. Unit IO1 = 10mA Tj = 25°C 2.575 2.6 2.626 V IO1 = 0 to IFL1 Tj = 0 to 125°C VCC = 4.75 to 5.25V 2.55 2.6 2.65 VDD = 0 to 10.8V IO1 = 0.5A 2.2 IO2 = 10mA Tj = 25°C 3.23 3.3 3.37 IO2 = 0 to IFL2 Tj = 0 to 125°C VCC = 4.75 to 5.25V 3.2 3.3 3.4 2.65 VDD = 0 to 10.8V IO2 = 0.5A 2.92 IO3 = 10mA Tj = 25°C 7.84 8 8.16 IO3 = 0 to IFL3 Tj = 0 to 125°C VDD = 10.8 to 13.2V 7.76 8 8.24 V 3.4 V ∆VO Line Regulation 1 ∆VO Load Regulation 1 IO = 0.01 to IFL VD1 Dropout Voltage 1 (Note 2) 1.3 1.9 V VD2 Dropout Voltage 2 IO1 = IFL1 IO2 = IFL2 (Note 2) 1.13 1.4 V VD3 Dropout Voltage 3 (Note 2) 1.6 2.2 V tTR Transient Response IO3 = IFL3 (Note 3, 7) IOL1 Output 1 Current Limit ∆VO = 125mV 1.5 2.1 2.5 A IOL2 Output 2 Current Limit ∆VO = 165mV 1.1 1.7 2.5 A IOL3 Output 3 Current Limit ∆VOUT = 400mV 0.25 0.4 0.5 A IO1 Output 1 Minimum Load Current Output 2 Minimum Load Current Output 3 Minimum Load Current (Note 4, 7) 0 mA (Note 4, 7) 0 mA (Note 4, 7) 0 mA IO2 IO3 IO = 10mA VCC =±5% VDD =±10% <0.2 (Note 1) %VO <0.4 %VO µs <1 3/12 ST3L01 Symbol Parameter Test Conditions Min. Typ. Max. Unit CO Output Capacitor (Note 5, 7) 0.1 µF CCC Input Capacitor (Note 5) 1.0 µF CDD Input Capacitor (Note 5) 0.1 RegTherm Therma Regulation SVR1 Supply Voltage Rejection (VCC to Output 1) IOUT = IFL, tPULSE = 30ms (Note 7) B = 100Hz to 100KHz IO1 = IFL1/10 VCC = 4.75 to 5.25V (Note 7) SVR2 Supply Voltage Rejection (VCC to Output 2) B = 100Hz to 100KHz VCC = 4.75 to 5.25V SVR3 Supply Voltage Rejection (VDD to Output 3) B = 100Hz to 100KHz VDD = 10.8 to 13.2V VCC Quiescent Current VDD Quiescent Current IO1 = IO2 = IO3 = 0 IO1 = IO2 = IO3 = 0 Output Noise B = 10Hz to 10KHz (Note 7) IVCC IVDD eN ∆VO Temperature Stability IO = 10mA ∆VO Long Term Stability Tj = 125°C, 1000Hrs µF 0.1 0.3 %/W 30 >40 dB IO2 = IFL2/10 (Note 7) 30 >40 dB IO3 = IFL3/10 (Note 7) 40 >50 dB (Note 6, 7) (Note 7) 7 10 13 20 0.003 mA mA %VOUT 0.5 %VOUT 0.3 %VOUT Note 1: Low duty cycle pulse testing with Kelvin connections are required in order to maintain accurate data Note 2: Dropout Voltage is defined as the minimum differential voltage between V I and VO required to mantain regulation at VO. It is measured when the output voltage drops 100mV below its nominal value. Note 3: Transient response is defined with a step change in load from 10mA to IFL /2 as the time from the load step until the output voltage reaches it’s minimum value. Note 4: Minimum load current is defined as the minimum current required at the output in order to maintain regulation for the output voltage. Note 5: The regulator shall withstand 100000 reverse bias discharges of the maximum output capacitance, with no degradation, when the input voltage is switched to ground in 1 µs. Note 6: Temperature stability is the change in output from nominal over the operating temperature range. Note 7: Guaranteed by design, not tested in production. APPLICATION HINTS EXTERNAL CAPACITORS The ST3L01 requires external capacitors for stability. We suggest to solder both capacitors as close as possible to the relative pins. INPUT CAPACITORS An input capacitor, whose value is at least 0.1µF, is required on the VDD input; the amount of the input capacitance can be increased without limit. Any good quality tantalum or ceramic low ESR capacitor may be used at the VDD input. Any input capacitor, whose value is at least 1mF is instead required on the VCC input; the amount of this input capacitance can be increased without limit. Tantalum or aluminum electrolitic capacitor can be used at the VCC input; ceramic, low ESR capacitor are not recommended. Both capacitors must be located at a distance of not modre than 0.5" from the input pins of the device and returned to a clean analog ground. OUTPUT CAPACITOR The ST3L01 is designed specifically to work with Ceramic and Tantalum capacitors. 4/12 The test results of the ST3L01 stability using multilayer ceramic capacitors show that a minimum value of 0.1µF is needed for the three regulators. This value can be increased for even better transient response and noise performance. Surface-mountable solid tantalum capacitors offer a good combination of small physical size for the capacitance value and ESR in the range need by the ST3L01. The test results show good stability for both outputs with values of at least 0.1µF. Also this capacitor value can be increased without limit for even better performance such a transient response and noise. IMPORTANT; The output capacitor must maintain its ESR in the stable region over the full operating temperature to assure stability. Also , capacitor tolerance and variation with temperature must be considered to assure that the minimum amount of capacitance is provided at all times. For this reason, when a caramic multilayer capacitor is used, the better choise for temperature coefficent is the X7R type, which holds the capacitance within ±15% . The output capacitor should be located not more than 0.5" from the output pins of the device and returned to a clean analog ground. ST3L01 TYPICAL CHARACTERISTICS (CCC=1µF (tant), CDD=100nF (X7R), All C O=100nF (X7R)) Figure 1 : Output Voltage vs Temperature Figure 4 : Load Regulation vs Temperature Figure 2 : Output Voltage vs Temperature Figure 5 : Load Regulation vs Temperature Figure 3 : Output Voltage vs Temperature Figure 6 : Load Regulation vs Temperature 5/12 ST3L01 Figure 7 : Dropout Voltage vs Temperature Figure 10 : Dropout Voltage vs Output Current Figure 8 : Dropout Voltage vs Temperature Figure 11 : Dropout Voltage vs Output Current Figure 9 : Dropout Voltage vs Temperature Figure 12 : Dropout Voltage vs Output Current 6/12 ST3L01 Figure 13 : Current Limit vs Temperature Figure 16 : Output Voltage vs Output Current Figure 14 : Current Limit vs Temperature Figure 17 : Output Voltage vs Output Current Figure 15 : Current Limit vs Temperature Figure 18 : Output Voltage vs Output Current 7/12 ST3L01 Figure 19 : Quiescent Current vs Temperature Figure 22 : Supply Voltage Rejection vs Frequency Figure 20 : Quiescent Current vs Temperature Figure 23 : Supply Voltage Rejection vs Frequency Figure 21 : Supply Voltage Rejection vs Frequency Figure 24 : Supply Voltage Rejection vs Output Current 8/12 ST3L01 Figure 25 : Supply Voltage Rejection vs Output Current Figure 28 : Line Transient VCC=4.75 to 5.25V, VDD=12V, IO1=IO2 =10mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) Figure 26 : Supply Voltage Rejection vs Output Current Figure 29 : Line Transient VCC=4.75 to 5.25V, VDD=12V, IO1=IO2 =10mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) Figure 27 : Supply Voltage Rejection vs Temperature Figure 30 : Line Transient VCC=4.75 to 5.25V, VDD=12V, IO1=IO2 =10mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) 9/12 ST3L01 Figure 31 : Line Transient Figure 34 : Load Transient VCC=5V, V DD=10.7 to 13.2V, IO3=10mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) VCC=5V, V DD=12V, IO1=10 to 600mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) Figure 32 : Line Transient Figure 35 : Load Transient VCC=5V, V DD=10.7 to 13.2V, IO3=10mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) VCC=5V, V DD=12V, IO1=10 to 600mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) Figure 33 : Line Transient Figure 36 : Load Transient VCC=5V, V DD=10.7 to 13.2V, IO3=10mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) VCC=5V, V DD=12V, IO1=10 to 600mA, CCC=1µF (tant), CDD=100nF (X7R), All CO=100nF (X7R) 10/12 ST3L01 SPAK-7L MECHANICAL DATA DIM. mm. MIN. A 1.78 A2 0.03 C TYP inch MAX. MIN. 2.03 0.070 0.13 0.001 0.25 C1 TYP. MAX. 0.080 0.005 0.010 0.25 0.010 D 1.02 1.27 0.040 0.050 D1 7.87 F 0.63 8.13 0.310 0.320 0.79 0.025 0.031 G 1.27 0.050 G1 7.62 0.3 H1 5.59 0.220 H2 9.27 9.52 0.365 0.375 H3 8.89 9.14 0.350 0.360 L 10.41 10.67 0.410 L1 7.49 0.420 0.295 L2 8.89 9.14 0.350 0.360 M 0.79 1.04 0.031 0.041 6˚ 3˚ N V 0.25 3˚ 0.010 6˚ PO13F2/A 11/12 ST3L01 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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