STB100NH02L N-CHANNEL 24V - 0.0052 Ω - 60A D²PAK STripFET™ III POWER MOSFET TYPE STB100NH02L ■ ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID 24 V < 0.006 Ω 60 A (2) TYPICAL RDS(on) = 0.0052 Ω @ 10 V TYPICAL RDS(on) = 0.007 Ω @ 5 V RDS(ON) * Qg INDUSTRY’s BENCHMARK CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE SURFACE-MOUNTING D2PAK (TO-263) POWER PACKAGE IN TUBE (NO SUFFIX) OR IN TAPE & REEL (SUFFIX “T4”) 3 1 D²PAK TO-263 (Suffix “T4”) DESCRIPTION The STB100NH02L utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable fot the most demanding DC-DC converter applications where high efficiency is to be achieved. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol Vspike(1) VDS VDGR Parameter Value Unit Drain-source Voltage Rating 30 V Drain-source Voltage (VGS = 0) 24 V Drain-gate Voltage (RGS = 20 kΩ) 24 V ± 20 V Drain Current (continuous) at TC = 25°C 60 A Drain Current (continuous) at TC = 100°C 60 A Drain Current (pulsed) 240 A VGS Gate- source Voltage ID(2) ID(2) IDM(3) Ptot EAS (4) Tstg Tj Total Dissipation at TC = 25°C 100 W Derating Factor 0.67 W/°C Single Pulse Avalanche Energy 600 mJ -55 to 175 °C Storage Temperature Max. Operating Junction Temperature September 2003 1/11 STB100NH02L THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 1.5 62.5 300 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Drain-source Breakdown Voltage ID = 25 mA, VGS = 0 Zero Gate Voltage Drain Current (VGS = 0) VDS = 20 V VDS = 20 V Gate-body Leakage Current (VDS = 0) VGS = ± 20 V Min. Typ. Max. 24 Unit V TC = 125°C 1 10 µA µA ±100 nA Max. Unit ON (5) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 5 V ID = 30 A ID = 15 A Min. Typ. 1 1.8 V 0.0052 0.007 0.006 0.011 Ω Ω Typ. Max. Unit DYNAMIC Symbol Test Conditions gfs (5) Forward Transconductance VDS = 10 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 15V f = 1 MHz VGS = 0 Gate Input Resistance f=1 MHz Gate DC Bias=0 Test Signal Level =20 mV Open Drain RG 2/11 Parameter ID = 30 A Min. 40 S 2850 800 120 pF pF pF 1 Ω STB100NH02L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time ID =30 A VDD = 10 V RG = 4.7 Ω VGS = 10 V (Resistive Load, Figure 3) 13 75 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=10 V ID=60 A VGS=10 V 47.5 10 7 64 nC nC nC Typ. Max. Unit 50 18 24.3 ns ns Typ. Max. Unit 60 240 A A 1.3 V ns ns SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. ID = 30 A VDD = 10 V RG = 4.7Ω, VGS = 10 V (Resistive Load, Figure 3) SOURCE DRAIN DIODE Symbol Parameter ISD ISDM Source-drain Current Source-drain Current (pulsed) VSD (5) trr Qrr IRRM Test Conditions Forward On Voltage ISD = 30 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100A/µs ISD = 60 A VDD = 16 V Tj = 150°C (see test circuit, Figure 5) Min. VGS = 0 35 35 2 (1) Garanted when external Rg=4.7 Ω and tf < tfmax. (2) Value limited by wire bonding (3) Pulse width limited by safe operating area. (4) Starting Tj = 25 oC, ID = 30A, VDD = 15V (5) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (6) Q oss = Coss*∆ Vin , Coss = Cgd + Cds . See Appendix A (7) Gate charge for synchronous operation Safe Operating Area Thermal Impedance ns nC A 3/11 STB100NH02L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/11 STB100NH02L Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature. . . 5/11 STB100NH02L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/11 STB100NH02L D2PAK MECHANICAL DATA DIM. mm. MIN. TYP. inch. MAX. MIN. TYP. TYP. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.028 0.037 B2 1.14 1.7 0.045 0.067 C 0.45 0.6 0.018 0.024 C2 1.21 1.36 0.048 0.054 D 8.95 9.35 0.352 0.368 10.4 0.394 D1 E 8 10 E1 G 0.315 8.5 0.409 0.334 4.88 5.28 0.192 0.208 L 15 15.85 0.591 0.624 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.069 M 2.4 3.2 0.094 0.126 4° 0° R V2 0.4 0° 0.015 4° 7/11 STB100NH02L D2PAK FOOTPRINT TUBE SHIPMENT (no suffix)* TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. mm MIN. A DIM. mm MAX. MIN. MAX. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0075 0.082 R 50 1.574 T 0.25 0.35 .0.0098 0.0137 W 23.7 24.3 0.933 0.956 * on sales type 8/11 inch MIN. MIN. 330 B 1.5 C 12.8 D 20.2 G 24.4 N 100 T TAPE MECHANICAL DATA inch MAX. MAX. 12.992 0.059 13.2 0.504 0.520 0.795 26.4 0.960 1.039 3.937 30.4 1.197 BASE QTY BULK QTY 1000 1000 STB100NH02L APPENDIX A Buck Converter: Power Losses Estimation SW1 SW2 The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is er moved to allow for a safer working junction temperature. The low side (SW2) device requires: • • • • • Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; The high side (SW1) device requires: • Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate • Small Qg to have a faster commutation and to reduce gate charge losses • Low RDS(on) to reduce the conduction losses. 9/11 STB100NH02L Pconduction Pswitching R DS(on)SW1 * I 2L * d R DS(on)SW2 * I 2L * (1 − d ) Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * IL Ig Zero Voltage Switching Not Applicable Conduction Not Applicable Vf(SW2) * I L * t deadtime * f Pgate(Q G ) Q g(SW1) * Vgg * f Q gls(SW2) * Vgg * f PQoss Vin * Q oss(SW1) * f Vin * Q oss(SW2) * f 2 2 Parameter d Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss 10/11 Low Side Switch (SW2) Recovery Pdiode 1 High Side Switch (SW1) 1 Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses Dissipated by SW1 during turn-on Vin * Q rr(SW2) * f STB100NH02L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. 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