STD70NH02L N-CHANNEL 24V - 0.0062Ω - 60A - DPAK STripFET™ III POWER MOSFET TARGET DATA TYPE STD70NH02L ■ ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID 24 V < 0.008Ω 60 A (*) TYPICAL RDS(on) = 0.0062Ω @ 10 V TYPICAL RDS(on) = 0.008Ω @ 5 V RDS(ON) * Qg INDUSTRY’s BENCHMARK CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX ”T4”) DESCRIPTION The STD70NH02L utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable for the most demanding DC-DC converter application where high efficiency is to be achieved. 3 1 DPAK TO-252 (Suffix “T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTERS ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STD70NH02LT4 D70NH02L DPAK TAPE & REEL August 2003 1/8 STD70NH02L ABSOLUTE MAXIMUM RATINGS Symbol Vspike(1) VDS VDGR Parameter Drain-source Voltage Rating 30 V 30 V Drain-gate Voltage (RGS = 20 kΩ) 24 V ± 20 V 60 A Gate- source Voltage I D (* ) Drain Current (continuous) at TC = 25°C ID PTOT EAS (2) Tstg Tj Unit Drain-source Voltage (VGS = 0) VGS IDM (5) Value Drain Current (continuous) at TC = 100°C 50 A Drain Current (pulsed) 240 A Total Dissipation at TC = 25°C 70 W Derating Factor 0.47 W/°C Single Pulse Avalanche Energy TBD mJ Storage Temperature °C -55 to 175 Max. Operating Junction Temperature °C THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 2.14 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W Thermal Resistance Junction-pcb Max 43 °C/W Maximum Lead Temperature for Soldering Purpose 275 °C Rthj-pcb (#) Tl 2 (#) When Mounted on 1inch FR-4 board, 2oz of Cu ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol 2/8 Parameter Test Conditions Drain-source Breakdown Voltage ID = 25 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 30 A VGS = 5 V, ID =30 A V(BR)DSS Min. Typ. Max. 24 Unit V 1 10 µA µA ±100 nA 0.008 0.014 Ω Ω 1 0.0062 0.008 STD70NH02L ELECTRICAL CHARACTERISTICS (CONTINUED) DYNAMIC Symbol gfs (3) Parameter Forward Transconductance Test Conditions Min. VDS = 10 V , ID = 30 A VDS = 10V, f = 1 MHz, VGS = 0 Typ. Max. Unit TBD S Ciss Input Capacitance 2000 pF Coss Output Capacitance 420 pF Crss Reverse Transfer Capacitance 210 pF RG Gate Input Resistance 1 Ω f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Test Conditions Min. VDD = 10V, ID = 30 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) Typ. Max. Unit TBD ns TBD ns Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 10 V, ID = 60 A, VGS = 10 V 35 TBD TBD Qoss (4) Output Charge VDS = 16 V, VGS = 0 V TBD nC Qgls (6) Third-Quadrant Gate Charge VDS = 0 V, VGS = 10 V TBD nC Qg Qgs Qgd 47 nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off-Delay Time Fall Time Test Conditions Min. VDD = 10 V, ID = 30 A, RG = 4.7 Ω, VGS = 6.3 V (see test circuit, Figure 3) Typ. Max. TBD TBD Unit ns ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 60 A ISDM (5) Source-drain Current (pulsed) 240 A VSD (3) Forward On Voltage ISD = 30A, VGS = 0 1.3 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 30A, di/dt = 100A/µs, VDD = 15V, Tj = 150°C (see test circuit, Figure 5) ISD trr Qrr IRRM Parameter Test Conditions Min. Typ. TBD TBD TBD ns nC A (*) Value Limited by Wire Bonding 1. Garanted when external Rg = 4.7 Ω and tf < t f max 2. Starting T j = 25°C, I D = 25A, VDD = 15V 3. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 4. Qoss = Coss*∆ Vin, Coss = Cgd+Cds. See Appendix A 5. Pulse width limited by safe operating area 6. Gate charge for Syncronous Operation 3/8 STD70NH02L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/8 STD70NH02L TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. A 2.20 2.40 0.087 TYP. MAX. 0.094 A1 0.90 1.10 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.90 0.025 0.035 B2 5.20 5.40 0.204 0.213 C 0.45 0.60 0.018 0.024 C2 0.48 0.60 0.019 0.024 D 6.00 6.20 0.236 0.244 E 6.40 6.60 0.252 0.260 G 4.40 4.60 0.173 0.181 H 9.35 10.10 0.368 0.398 L2 0.8 0.031 L4 0.60 1.00 0.024 0.039 V2 0o 8o 0o 0o P032P_B 5/8 STD70NH02L DPAK FOOTPRINT TUBE SHIPMENT (no suffix)* All dimensions are in millimeters All dimensions are in millimeters TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. mm MIN. A DIM. mm MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 D 1.5 D1 1.5 E 1.65 MIN. MAX. 12.1 0.476 1.6 0.059 0.063 0.059 1.85 0.065 0.073 F 7.4 7.6 0.291 0.299 K0 2.55 2.75 0.100 0.108 P0 3.9 4.1 0.153 0.161 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 R W 40 15.7 16.3 1.574 0.618 * on sales type 6/8 inch 0.641 MIN. 330 B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA MAX. inch MAX. 12.992 0.059 13.2 0.504 0.520 0.795 18.4 0.645 0.724 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 STD70NH02L Appendix A: Buck Converter Power Losses Estimation DESCRIPTION The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires: - Very low RDS(on) to reduce conduction losses - Small Qgls to reduce the gate charge losses - Small Coss to reduce losses due to output capaci tance - Small Qrr to reduce losses on SW1 during its turn-on - The Cgd/C gs ratio lower than Vth /VGG ratio especially with low drain to source voltage to avoid the cross conduction phenomenon Pswitching Parameter δ Qgsth Qgls Pconduction Pswitching Pdiode Pdiode PQoss Low Side Switch (SW2) RDS(on)SW1* I *δ RDS(on)SW2* I2L *(1− δ ) Vin *(Qgsth(SW1)+ Qgd(SW1)) *f * IL Ig Zero Voltage Switching Recovery Not Applicable Conduction Not Applicable Vf(SW2) * IL * t deadtime*f Pgate(QG ) Qg(SW1)* Vgg * f Qgls(SW2)* Vgg * f PQoss Vin *Qoss(SW1)*f Vin *Qoss(SW2)*f 2 2 Pdiode The high side (SW1) device requires: - Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate - Small Qg to have a faster commutation and to reduce gate charge losses - Low RDS(on) to reduce the conduction losses High Side Switch (SW1) 2 L Pconduction 1 Vin * Qrr(SW2)*f Meaning Duty-Cycle Post Threshold Gate Charge Third Quadrant Gate Charge On State Losses On-off Transition Losses Conduction and Reverse Recovery Diode Losses Gate Drive Losses Output Capacitance Losses 1 Dissipated by SW1 during turn-on 7/8 STD70NH02L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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