STB11NB40 STB11NB40-1 N-CHANNEL 400V - 0.48 Ω - 10.7A D2PAK/I2PAK PowerMESH™ MOSFET Figure 1. Package Table 1. General Features Type VDSS RDS(on) ID STB11NB40 400 V < 0.55 Ω 10.7 A STB11NB40-1 400 V < 0.55 Ω 10.7 A FEATURES SUMMARY ■ TYPICAL RDS(on) = 0.48 Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ VERY LOW INTRINSIC CAPACITANCES ■ GATE CHARGE MINIMIZED 3 3 12 I2PAK TO-262 DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. 1 D2PAK TO-263 Figure 2. Internal Schematic Diagram APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITCH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE Table 2. Order Codes Part Number Marking Package Packaging STB11NB40T4 B11NB40 D2PAK TAPE & REEL STB11NB40-1 B11NB40 I2PAK TUBE REV. 2 April 2004 1/11 STB11NB40/STB11NB40-1 Table 3. Absolute Maximum Ratings Symbol Value Unit Drain-source Voltage (VGS = 0) 400 V Drain- gate Voltage (RGS = 20 kΩ) 400 V Gate-source Voltage ± 30 V ID Drain Current (cont.) at TC = 25 °C 10.7 A ID Drain Current (cont.) at TC = 100 °C 6.7 A Drain Current (pulsed) 42.8 A Total Dissipation at TC = 25 °C 125 W Derating Factor 1.0 W°/C dv/dt (2) Storage Temperature 4.5 V/ns Tstg Storage Temperature -65 to 150 °C 150 °C Value Unit VDS VDGR VGS IDM (1) Ptot Tj Parameter Max. Operating Junction Temperature Note: 1. Pulse width limited by safe operating area 2. ISD ≤ 11A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Table 4. Thermal Data Symbol Parameter Rthj-case Thermal Resistance Junction-case Max 1.0 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W 300 °C Max Value Unit Tl Maximum Lead Temperature For Soldering Purpose Table 5. Avalanche Characteristics Symbol 2/11 Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) 10.7 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C; ID = IAR; VDD = 50 V) 530 mJ STB11NB40/STB11NB40-1 ELECTRICAL CHARACTERISTICS (Tcase = 25°C unless otherwise specified) Table 6. Off Symbol Parameter V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA; VGS = 0 IDSS Zero Gate Voltage VDS = Max Rating 1 µA Drain Current (VGS = 0) VDS = Max Rating Tc = 125 °C 50 µA Gate-body Leakage Current (VDS = 0) VGS = ± 30 V ± 100 nA IGSS Test Conditions Min. Typ. Max. 400 Unit V Table 7. On (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS; ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10V; ID = 5.3 A Min. Typ. Max. Unit 3 4 5 V 0.48 0.55 Ω Min. Typ. Max. Unit 5 6.5 Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % Table 8. Dynamic Symbol Parameter Test Conditions gfs (1) Forward Transconductance VDS > ID(on) x RDS(on)max; ID = 5.3 A Ciss Input Capacitance VDS = 25 V; f = 1 MHz; VGS = 0 Coss Crss S 1115 1450 pF Output Capacitance 210 280 pF Reverse Transfer Capacitance 22 30 pF Typ. Max. Unit Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % Table 9. Switching On Symbol Parameter Test Conditions Min. Turn-on Time VDD = 200 V; ID = 5.3 A; RG = 4.7 Ω 17 25 ns Rise Time VGS = 10 V (see test circuit, Figure 16) 10 15 ns Qg Total Gate Charge VDD = 320 V; ID = 10.7 A; VGS = 10 V 29.5 43 nC Qgs Gate-Source Charge 10.6 nC Qgd Gate-Drain Charge 11.8 nC td(on) tr Table 10. Switching Off Symbol Parameter Test Conditions Min. Typ. Max. Unit Off-voltage Rise Time VDD = 320 V; ID = 10.7 A; RG = 4.7 Ω 10 14 ns tf Fall Time VGS = 10 V; (see test circuit, Figure 18) 10 14 ns tc Cross-over Time 17 25 ns tr(Voff) 3/11 STB11NB40/STB11NB40-1 Table 11. Source Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 10.7 A ISDM (1) Source-drain Current (pulsed) 42.8 A VSD (2) Forward On Voltage ISD = 10.7 A; VGS = 0 1.6 V trr Reverse Recovery Time ISD = 10.7 A; di/dt = 100 A/µs 400 ns Qrr Reverse RecoveryCharge VDD = 100 V; Tj = 150 °C (see test circuit, Figure 18) 3.4 µC IRRAM Reverse RecoveryCharge 17 A Note: 1. Pulse width limited by safe operating area 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % Figure 3. Safe Operating Area Figure 4. Thermal Impedance Figure 5. Output Characteristics Figure 6. Transfer Characteristics 4/11 STB11NB40/STB11NB40-1 Figure 7. Transconductance Figure 8. Static Drain-source On Resistance Figure 9. Gate Charge vs Gate-source Voltage Figure 10. Capacitance Variations Figure 11. Normalized Gate Thresold Voltage vs Temperature Figure 12. Normalized On Resistance vs Temperature 5/11 STB11NB40/STB11NB40-1 Figure 13. Source-drain Diode Forward Characteristics 6/11 STB11NB40/STB11NB40-1 Figure 14. Unclamped Inductive Load Test Circuit Figure 15. Unclamped Inductive Waveforms Figure 16. Switching Times Test Circuits For Resistive Load Figure 17. Gate Charge Test Circuit Figure 18. Test Circuit For Inductive Load Switching And Diode Recovery Times 7/11 STB11NB40/STB11NB40-1 PACKAGE MECHANICAL Table 12. I2PAK Mechanical Data Symbol millimeters Min Typ Max Min A 4.40 4.60 0.173 0.181 A1 2.40 2.72 0.094 0.107 b 0.61 0.88 0.024 0.349 b1 1.14 1.70 0.045 0.067 c 0.49 0.70 0.019 0.027 c2 1.23 1.32 0.048 0.052 D 8.95 9.35 0.352 0.368 Typ Max e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.195 0.203 E 10.00 10.40 0.394 0.409 L 13.00 14.00 0.511 0.551 L1 3.50 3.93 0.138 0.154 L2 1.27 1.40 0.050 0.055 Figure 19. I2PAK Package Dimensions Note: Drawing is not to scale. 8/11 inches STB11NB40/STB11NB40-1 Table 13. D2PAK Mechanical Data Symbol millimeters Min Typ inches Max Min Typ Max A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 10.4 0.393 D1 E 8 0.315 10 E1 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 R V2 0.4 0.126 0.015 0° 4° 3 Figure 20. D2PAK Package Dimensions Note: Drawing is not to scale. 9/11 STB11NB40/STB11NB40-1 REVISION HISTORY Table 14. Revision History 10/11 Date Revision Description of Changes March-1998 1 First Issue 14-Apr-2004 2 Stylesheet update. No content change. STB11NB40/STB11NB40-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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