STP9NB50 STP9NB50FP N-CHANNEL 500V - 0.75 Ω - 8.6 A TO-220/TO-220FP PowerMesh MOSFET ■ ■ ■ ■ ■ TYPE VDSS RDS(on) ID STP9NB50 500 V < 0.85 Ω 8.6 A STP9NB50FP 500 V < 0.85 Ω 4.9 A TYPICAL RDS(on) = 0.75 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAY process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprieraty edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. 3 1 3 2 1 2 TO-220FP TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value STP9NB50 VDS VDGR VGS Unit STP9NB50FP Drain-source Voltage (VGS = 0) 500 V Drain-gate Voltage (RGS = 20 kΩ) 500 V Gate- source Voltage ±30 V ID Drain Current (continuos) at TC = 25°C 8.6 4.9 A ID Drain Current (continuos) at TC = 100°C 5.4 3.1 A Drain Current (pulsed) 34.4 34.4 A Total Dissipation at TC = 25°C 125 40 W IDM (●) PTOT Derating Factor dv/dt (1) Peak Diode Recovery voltage slope VISO Insulation Withstand Voltage (DC) Tstg Storage Temperature Tj Max. Operating Junction Temperature (•)Pulse width limited by safe operating area May 2000 1 0.32 W/°C 4.5 4.5 V/ns - 2000 V –65 to 150 °C 150 °C (1)ISD<9A, di/dt<200A/µ, VDD<V(BR)DSS,TJ<TJMAX 1/9 STP9NB50/FP THERMAL DATA TO-220 TO-220FP 1 3.13 °C/W Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tl AVALANCHE CHARACTERISTICS Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 8.6 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 520 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (V GS = 0) VDS = Max Rating 1 µA VDS = Max Rating, TC = 125 °C 50 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA Max. Unit V(BR)DSS 500 V ON (1) Symbol Parameter Test Conditions Gate Threshold Voltage VDS = VGS, ID = 250 µA R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 4.3 A ID(on) On State Drain Current VGS(th) VDS > ID(on) x RDS(on)max, VGS = 10V Min. 3 Typ. 4 5 V 0.75 0.85 Ω 8.6 A DYNAMIC Symbol gfs (1) 2/9 Parameter Forward Transconductance C iss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 4.3 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. Max. Unit 5.7 S 1250 pF 175 pF 20 pF STP9NB50/FP ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Parameter Turn-on Delay Time Rise Time Test Conditions Min. VDD = 250 V, ID = 4.3 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) Total Gate Charge Qgs Gate-Source Charge Q gd Gate-Drain Charge Typ. Unit 19 ns 11 ns 32 VDD = 400V, I D = 8.6 A, VGS = 10V Max. 45 nC 10.6 nC 13.7 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Condit ions Min. VDD = 400V, ID = 8.6 A, R G = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Typ. Max. Unit 11.5 ns 11 ns 20 ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Min. Typ. Source-drain Current ISDM (2) Source-drain Current (pulsed) VSD (1) Forward On Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge IRRM Reverse Recovery Current ISD = 8.6 A, VGS = 0 ISD = 8.6 A, di/dt = 100A/µs, VDD = 100V, T j = 150°C (see test circuit, Figure 5) Max. Unit 8.6 A 34.4 A 1.6 V 420 ns 3.5 µC 16.5 A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Safe Operating Area for TO-220FP 3/9 STP9NB50/FP Thermal Impedence for TO-220 Thermal Impedence for TO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 STP9NB50/FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP9NB50/FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP9NB50/FP TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 L2 0.027 0.409 16.4 0.645 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L4 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/9 STP9NB50/FP TO-220FP MECHANICAL DATA mm DIM. MIN. inch MAX. MIN. A 4.4 TYP. 4.6 0.173 TYP. MAX. 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 L2 16 0.630 B D A E L3 L3 L6 F F1 L7 F2 H G G1 ¯ 1 2 3 L2 L4 8/9 STP9NB50/FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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