STD15NF10 N - CHANNEL 100V - 0.073Ω - 15A TO-252 LOW GATE CHARGE STripFET POWER MOSFET PRELIMINARY DATA TYPE STD15NF10 ■ ■ ■ ■ ■ V DSS R DS( on ) ID 100 V < 0.08 Ω 15 A TYPICAL RDS(on) = 0.073 Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX ”T4”) DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency, high-frequency isolated DC-DC converters for Telecom and Computer applications. It is also intended for any applications with low gate drive requirements. 3 1 DPAK TO-252 (Suffix ”T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH-EFFICIENCY DC-DC CONVERTERS ■ UPS AND MOTOR CONTROL ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR Value Unit Drain-source Voltage (VGS = 0) Parameter 100 V Drain- gate Voltage (R GS = 20 kΩ) 100 V G ate-source Voltage ± 20 V ID Drain Current (continuous) at Tc = 25 oC 15 A ID Drain Current (continuous) at Tc = 100 o C 10 A Drain Current (pulsed) 60 A VGS I DM (•) P tot dv/dt( 1 ) E AS ( 2 ) T st g o T otal Dissipation at Tc = 25 C 45 W Derating Factor 0.3 W /o C Peak Diode Recovery voltage slope 9 V/ns Single Pulse Avalanche Energy 75 mJ Storage Temperature Max. Operating Junction Temperature Tj (•) Pulse width limited by safe operating area ( 2) starting Tj = 25 oC, ID =24A , VDD = 50V April 2000 -65 to 175 o C 175 o C (1) I SD ≤ 80 A, di/dt ≤ 300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMA 1/6 STD15NF10 THERMAL DATA R thj -case R thj -amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature F or Soldering Purpose o 3.33 62.5 300 o C/W C/W o C ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA V GS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 100 Unit V T c =125 oC V GS = ± 20 V 1 10 µA µA ± 100 nA ON (∗) Symbo l Parameter Test Con ditions ID = 250 µA V GS(th) Gate Threshold Voltage V DS = V GS R DS(on) Static Drain-source On Resistance V GS = 10 V I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. Typ. Max. Unit 2 3 4 V 0.073 0.08 Ω ID = 7.5 A 15 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/6 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D =7.5 A V GS = 0 Min. Typ. Max. Unit 20 S 870 125 52 pF pF pF STD15NF10 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Delay T ime Rise Time V DD = 50 V I D = 12 A R G = 4.7 Ω V GS = 10 V (Resistive Load, see fig. 3) 58 45 ns ns Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 80 V ID = 15 A V GS = 10 V 30 6 10 nC nC nC SWITCHING OFF Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(of f) tf Turn-off Delay T ime Fall T ime V DD = 27 V I D = 12 A V GS = 10 V R G = 4.7 Ω (Resistive Load, see fig. 3) 49 17 ns ns t d(of f) tf tc Off-voltage Rise T ime Fall T ime Cross-over Time Vclamp = 80 V I D = 15 A V GS = 10 V R G = 4.7 Ω (Induct ive Load, see fig. 5) 43 36 39 ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 15 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 15 A di/dt = 100 A/µs T j = 150 o C V DD = 50 V (see test circuit, fig. 5) t rr Q rr I RRM Min. Typ. V GS = 0 Max. Unit 15 60 A A 1.5 V 100 ns 375 nC 7.5 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operatingarea 3/6 STD15NF10 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STD15NF10 TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL ”A” L2 D = 1 = G 2 = = = E = B2 3 B DETAIL ”A” L4 0068772-B 5/6 STD15NF10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6