STD40NE03L N - CHANNEL 30V - 0.012 Ω - 40A TO-252 STripFET POWER MOSFET TYPE V DSS R DS(o n) ID STD40NE03L 30 V < 0.016 Ω 40 A ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.012 Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW GATE CHARGE APPLICATION ORIENTED CHARACTERIZATION ADD SUFFIX ”T4” FOR ORDERING IN TAPE & REEL 3 1 DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. DPAK TO-252 (Suffix ”T4”) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SOLENOID AND RELAY DRIVERS ■ MOTOR CONTROL, AUDIO AMPLIFIERS ■ DC-DC & DC-AC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR Value Unit Drain-source Voltage (VGS = 0) Parameter 30 V Drain- gate Voltage (R GS = 20 kΩ) 30 V G ate-source Voltage ± 20 V ID Drain Current (continuous) at Tc = 25 oC 20** A ID o Drain Current (continuous) at Tc = 100 C 20** A Drain Current (pulsed) 160 A VGS I DM (•) P tot T otal Dissipation at Tc = 25 o C Derating Factor dv/ dt (1 ) Peak Diode Recovery voltage slope T st g Tj Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area (**) Value limi ted only by the package September 1999 55 W 0.37 W /o C 7 V/ns -65 to 175 o C 175 o C ( 1) ISD ≤20A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/8 STD40NE03L THERMAL DATA R th j-pc b R thj -amb R t hj-s ink Tl Thermal Resistance Junction-PC Board Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink T yp Maximum Lead Temperature F or Soldering Purpose o 2.7 100 1.5 275 C/W C/W o C/W o C o AVALANCHE CHARACTERISTICS Symbo l Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 40 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 15 V) 100 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA V GS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 30 Unit V T c = 125 oC V GS = ± 20 V 1 10 µA µA ± 100 nA Max. Unit ON (∗) Symbo l Parameter Test Con ditions ID = 250 µA V GS(th) Gate Threshold Voltage V DS = V GS R DS(on) Static Drain-source On Resistance V GS = 10 V V GS = 5 V I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. 1 ID = 20 A I D = 20 A Typ. 1.7 2.5 V 0.012 0.016 0.022 Ω Ω 40 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/8 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D = 20 A V GS = 0 V Min. Typ. Max. Unit 15 28 S 2200 570 200 pF pF pF STD40NE03L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Delay T ime Rise Time V DD = 15 V I D = 30 A R G = 4.7 Ω V GS = 5 V (Resistive Load, see fig. 3) 38 260 Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 24 V ID = 64 A V GS = 5 V 35 18 13 45 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbo l Parameter Test Con ditions Min. t d(of f) tf Turn-off Delay T ime Fall T ime V DD = 15 V I D = 30 A V GS = 5 V R G = 4.7 Ω (Resistive Load, see fig. 3) 75 50 ns ns tr (Voff) tf tc Off-voltage Rise T ime Fall T ime Cross-over Time V DD = 24 V I D = 64 A V GS = 5 V R G = 4.7 Ω (Induct ive Load, see fig. 5) 35 120 175 ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 40 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 64 A di/dt = 100 A/µs T j = 150 o C V DD = 15 V (see test circuit, fig. 5) t rr Q rr I RRM Min. Typ. V GS = 0 Max. Unit 40 160 A A 1.5 V 55 ns 0.1 µC 3.5 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STD40NE03L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STD40NE03L Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STD40NE03L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STD40NE03L TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL ”A” L2 D = 1 = G 2 = = = E = B2 3 B DETAIL ”A” L4 0068772-B 7/8 STD40NE03L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all information previously supplied. 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