STMICROELECTRONICS STE38NB50F

STE38NB50F

N - CHANNEL 500V - 0.11 Ω - 38A - ISOTOP
PowerMESH MOSFET
TYPE
STE38NB50F
■
■
■
■
■
■
■
V DSS
R DS(on)
ID
500 V
< 0.14 Ω
38 A
TYPICAL RDS(on) = 0.11 Ω
EXTREMELY HIGH dv/dt CAPABILITY
± 30V GATE TO SOURCE VOLTAGE RATING
100% AVALANCHE TESTED
LOW INTRINSIC CAPACITANCE
GATE CHARGE MINIMIZED
REDUCED VOLTAGE SPREAD
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip
layout coupled with the Company’s proprietary
edge termination structure, gives the lowest
RDS(on) per area, exceptional avalanche and
dv/dt capabilities and unrivalled gate charge and
switching characteristics.
ISOTOP
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITCH MODE POWER SUPPLY (SMPS)
■ DC-AC CONVERTER FOR WELDING
EQUIPMENT AND UNINTERRUPTABLE
POWER SUPPLY AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symb ol
V DS
V DGR
V GS
Value
Un it
Drain-source Voltage (V GS = 0)
Parameter
500
V
Drain- gate Voltage (R GS = 20 kΩ)
500
V
± 30
V
G ate-source Voltage
o
ID
Drain Current (continuous) at Tc = 25 C
38
A
ID
Drain Current (continuous) at Tc = 100 C
o
24
A
Drain Current (pulsed)
152
A
T otal Dissipation at Tc = 25 C
400
W
Derating Factor
3.2
W /o C
Peak Diode Recovery voltage slope
4.5
V/ns
I DM (•)
P tot
dv/dt (1)
T s tg
Tj
o
Storage T emperature
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
December 1999
-65 to 150
o
C
150
o
C
( 1) ISD ≤38 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
1/8
STE38NB50F
THERMAL DATA
R thj -case
R thj -amb
R thc-sink
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Thermal Resistance Case-sink
Maximum Lead Temperature F or Soldering Purpose
Max
Max
T yp
o
0.31
30
0.1
300
C/W
C/W
o
C/W
o
C
o
AVALANCHE CHARACTERISTICS
Symbo l
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
E AS
Single Pulse Avalanche Energy
(starting Tj = 25 o C, ID = IAR , V DD = 50 V)
Max Value
Unit
38
A
1200
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V GS = 0
I DSS
V DS = Max Rating
Zero Gate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
Min.
Typ.
Max.
500
Unit
V
T c = 125 oC
V GS = ± 30 V
10
100
µA
µA
± 100
nA
Max.
Unit
ON (∗)
Symbo l
Parameter
Test Con ditions
ID = 250 µA
V GS(th)
Gate Threshold Voltage V DS = V GS
R DS(on)
Static Drain-source On
Resistance
V GS = 10 V
I D(o n)
On State Drain Current
V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
Min.
3
I D = 19 A
Typ.
4
5
V
0.11
0.14
Ω
38
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/8
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS = 25 V
f = 1 MHz
I D = 19 A
V GS = 0
Min.
Typ.
Max.
Unit
27
S
5900
880
80
pF
pF
pF
STE38NB50F
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
Typ.
Max.
Unit
t d(on)
tr
Turn-on Time
Rise Time
V DD = 250 V
I D = 19 A
R G = 4.7 Ω
V GS = 10 V
(see test circuit, figure 3)
45
35
Qg
Q gs
Q gd
Total G ate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 400 V I D = 38 A V GS = 10 V
140
38
61
196
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbo l
tr (Voff)
tf
tc
Parameter
Off-voltage Rise T ime
Fall T ime
Cross-over Time
Test Con ditions
Min.
28
30
60
V DD = 400 V
I D = 38 A
V GS = 10 V
R G = 4.7 Ω
(see test circuit, figure 5)
ns
ns
ns
SOURCE DRAIN DIODE
Symbo l
Parameter
Test Con ditions
ISD
I SDM (•)
Source-drain Current
Source-drain Current
(pulsed)
V SD (∗)
Forward On Voltage
I SD = 38 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 38 A
di/dt = 100 A/µs
o
T j = 150 C
V DD = 100 V
(see test circuit, figure 5)
t rr
Q rr
I RRM
Min.
Typ.
V GS = 0
Max.
Unit
38
152
A
A
1.6
V
715
ns
11.8
µC
33
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/8
STE38NB50F
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STE38NB50F
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
STE38NB50F
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STE38NB50F
ISOTOP MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
11.8
12.2
0.466
0.480
B
8.9
9.1
0.350
0.358
C
1.95
2.05
0.076
0.080
D
0.75
0.85
0.029
0.033
E
12.6
12.8
0.496
0.503
F
25.15
25.5
0.990
1.003
G
31.5
31.7
1.240
1.248
H
4
J
4.1
4.3
0.161
0.169
K
14.9
15.1
0.586
0.594
L
30.1
30.3
1.185
1.193
M
37.8
38.2
1.488
1.503
N
4
O
7.8
0.157
0.157
8.2
0.307
0.322
A
G
B
O
F
E
H
D
N
J
C
K
L
M
7/8
STE38NB50F
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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