STP7NB30 STP7NB30FP N - CHANNEL 300V - 0.75Ω - 7A - TO-220/TO-220FP PowerMESH MOSFET TYPE ST P7NB30 ST P7NB30FP ■ ■ ■ ■ ■ V DSS R DS(on) ID 300 V 300 V < 0.90 Ω < 0.90 Ω 7 A 4 A TYPICAL RDS(on) = 0.75 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED 3 DESCRIPTION Using the latest high voltage MESH OVERLAY process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. 1 3 2 2 1 TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITCH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value ST P7NB30 V DS V DGR V GS 300 V Drain- gate Voltage (R GS = 20 kΩ) 300 V ± 30 G ate-source Voltage Drain Current (continuous) at Tc = 25 o C ID o P tot dv/dt( 1) V ISO Ts tg Tj STP7NB30F P Drain-source Voltage (VGS = 0) ID I DM (•) Un it V 7 4 A Drain Current (continuous) at Tc = 100 C 4.4 2.5 A Drain Current (pulsed) 28 28 A o T otal Dissipation at Tc = 25 C 85 30 W Derating Factor 0.68 0.24 W /o C Peak Diode Recovery voltage slope 5.5 5.5 V/ns Insulation W ithstand Voltage (DC) 2000 Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area August 1999 V -65 to 150 o C 150 o C ( 1) ISD ≤ 7A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/9 STP7NB30/STP7NB30FP THERMAL DATA R thj -case Thermal Resistance Junction-case R thj -amb R thc-sink Tl Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature F or Soldering Purpose TO-220 TO-220FP 1.47 4.17 Max 62.5 0.5 300 o C/W o C/W C/W o C o AVALANCHE CHARACTERISTICS Symbo l Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 50 V) Max Value Unit 7 A 150 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA Typ. Max. 300 V GS = 0 V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) Min. Unit V o T c = 125 C V GS = ± 30 V 1 10 µA µA ± 100 nA ON (∗) Symbo l Parameter Test Con ditions V GS(th) Gate Threshold Voltage V DS = V GS ID = 250 µA R DS(on) Static Drain-source On Resistance V GS = 10V ID = 3.5 A I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. Typ. Max. Unit 3 4 5 V 0.75 0.9 Ω 7 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/9 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D = 3.5 A V GS = 0 Min. Typ. 1.5 Max. Unit S 500 100 15 pF pF pF STP7NB30/STP7NB30FP ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Time Rise Time V DD = 150 V I D = 3.5 A V GS = 10 V R G = 4.7 Ω (see test circuit, figure 3) 13 8 Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 240 V 17 7.5 6.5 25 nC nC nC Typ. Max. Unit I D = 7.0 A VGS = 10 V ns ns SWITCHING OFF Symbo l tr (Voff) tf tc Parameter Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions Min. 8 15 7 V DD = 240 V I D = 7.0 A R G = 4.7 Ω VGS = 10 V (see test circuit, figure 5) ns ns ns SOURCE DRAIN DIODE Symbo l ISD I SDM (•) V SD (∗) t rr Q rr I RRM Parameter Test Con ditions Min. Typ. Max. Unit 7.0 28 A A Source-drain Current Source-drain Current (pulsed) Forward On Voltage I SD = 7.0 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 7.0 A di/dt = 100 A/µs T j = 150 o C V DD = 100 V (see test circuit, figure 5) V GS = 0 1.6 V 190 ns 1.1 µC 11.5 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area for TO-220 Safe Operating Area for TO-220FP 3/9 STP7NB30/STP7NB30FP Thermal Impedance for TO-220 Thermal Impedance forTO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 STP7NB30/STP7NB30FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP7NB30/STP7NB30FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP7NB30/STP7NB30FP TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 L2 16.4 L4 0.645 13.0 0.551 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/9 STP7NB30/STP7NB30FP TO-220FP MECHANICAL DATA mm DIM. MIN. A 4.4 inch TYP. MAX. MIN. TYP. MAX. 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L3 L3 L6 F F1 L7 F2 H G G1 ¯ 1 2 3 L2 8/9 L4 STP7NB30/STP7NB30FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all information previously supplied. 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