STP40NF12 N-CHANNEL 120V - 0.028Ω - 40A TO-220 LOW GATE CHARGE STripFET™ II POWER MOSFET TYPE VDSS RDS(on) ID STP40NF12 120 V < 0.032 Ω 40 A ■ ■ ■ ■ TYPICAL RDS(on) = 0.028Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION 3 1 2 TO-220 DESCRIPTION This Power MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer application. It is also intended for any application with low gate charge drive requirements. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS HIGH-EFFICIENCY DC-DC CONVERTERS ■ UPS AND MOTOR CONTROL ■ ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Drain-source Voltage (VGS = 0) Value Unit 120 V Drain-gate Voltage (RGS = 20 kΩ) 120 V Gate- source Voltage ± 20 V ID Drain Current (continuous) at TC = 25°C 40 A ID Drain Current (continuous) at TC = 100°C 28 A IDM () PTOT Drain Current (pulsed) 160 A Total Dissipation at TC = 25°C 150 W 1 W/°C Derating Factor dv/dt (1) Peak Diode Recovery voltage slope 14 V/ns EAS (2) Single Pulse Avalanche Energy 150 mJ – 55 to 175 °C Tstg Tj Storage Temperature Operating Junction Temperature (● ) Pulse width limited by safe operating area October 2003 (1) ISD ≤40A, di/dt ≤600A/µs, VDD ≤ V(BR)DSS, Tj ≤ T JMAX. (2) Starting Tj = 25°C, ID = 40A, VDD = 50V 1/8 STP40NF12 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthj-amb Tl 1 °C/W Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Min. Typ. Max. 120 Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 V Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1 µA VDS = Max Rating, TC = 125 °C 10 µA Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 20 A Min. Typ. Max. Unit 2 2.8 4 V 0.028 0.032 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) 2/8 Parameter Forward Transconductance Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Test Conditions VDS = 25V, ID = 20 A VDS = 25V, f = 1 MHz, VGS = 0 Min. 40 S 1880 pF 265 pF 110 pF STP40NF12 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit 28 ns Rise Time VDD = 50 V, ID = 20 A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) 63 ns Qg Total Gate Charge VDD = 80V, ID =40A,VGS = 10V 60 Qgs Gate-Source Charge 11 nC Qgd Gate-Drain Charge 21 nC td(on) tr Turn-on Delay Time 80 nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off-Delay Time Fall Time Test Conditions Min. VDD = 50 V, ID = 20 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 3) Typ. Max. 84 28 Unit ns ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 40 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100A/µs, VDD = 25V, Tj = 150°C (see test circuit, Figure 5) IRRM Typ. Source-drain Current ISDM (2) trr Qrr Min. 114 456 8 Max. Unit 40 A 160 A 1.3 V ns nC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STP40NF12 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP40NF12 Normalized Gate Threshold Voltage vs Temperature Source-drain Diode Forward Characteristics Normalized On Resistance vs Temperature Normalized Drain-Source Breakdown vs Temperature 5/8 STP40NF12 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP40NF12 TO-220 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. 4.60 0.173 TYP. MAX. A 4.40 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 L 13 14 0.511 0.551 L1 3.50 3.93 0.137 0.154 L20 16.40 L30 28.90 0.645 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 7/8 STP40NF12 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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