STP40N03L-20 N - CHANNEL ENHANCEMENT MODE ”ULTRA HIGH DENSITY” POWER MOS TRANSISTOR PRELIMINARY DATA TYPE V DSS R DS(on) ID ST P40N03L-20 30 V < 0.02 Ω 40 A ■ ■ ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.016 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED HIGH CURRENT CAPABILITY 175oC OPERATING TEMPERATURE HIGH dV/dt CAPABILITY APPLICATION ORIENTED CHARACTERIZATION 1 2 3 TO-220 APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ POWER MOTOR CONTROL ■ DC-DC & DC-AC CONVERTERS ■ SYNCRONOUS RECTIFICATION INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (V GS = 0) 30 V V DGR Drain- gate Voltage (R GS = 20 kΩ) 30 V V GS Gate-source Voltage V DS Parameter ± 15 V ID Drain Current (continuous) at Tc = 25 C 40 A ID o Drain Current (continuous) at Tc = 100 C 28 A Drain Current (pulsed) 160 A I DM (•) P to t dV/dt( 1 ) T st g Tj o o Total Dissipation at T c = 25 C 90 W Derating Factor 0.6 W/ C 6 V/ns Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature o -65 to 175 o C 175 o C (•) Pulse width limited by safe operating area March 1996 1/7 STP40N03L-20 THERMAL DATA R t hj-ca se R t hj- amb R thc- si nk Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Thermal Resistance Case-sink Maximum Lead T emperature For Soldering Purpose Max Max Typ o 1.66 62.5 0.5 300 C/W C/W o C/W o C o AVALANCHE CHARACTERISTICS Symb ol Parameter Max Valu e Unit 40 A 300 mJ I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) E AS Single Pulse Avalanche Energy o (starting Tj = 25 C, ID = I AR , V DD = 25 V) E AR Repetitive Avalanche Energy (pulse width limited by Tj max, δ < 1%) 75 mJ I AR Avalanche Current, Repetitive or Not-Repetitive o (T c = 100 C, pulse width limited by Tj max, δ < 1%) 28 A ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol V (BR)DSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 250 µA VGS = 0 Min. Typ . Max. 30 Un it V I DSS Zero Gate Voltage V DS = Max Rating Drain Current (V GS = 0) V DS = Max Rating x 0.8 T c = 125 o C 250 1000 µA µA I GSS Gate-body Leakage Current (V DS = 0) V GS = ± 15 V ± 100 nA ON (∗) Symb ol Parameter Test Cond ition s V GS(th) Gate T hreshold Voltage V DS = VGS R DS( on) Static Drain-source On Resistance ID(o n) On State Drain Current ID = 250 µA V GS = 10V I D = 20 A V GS = 10V ID = 20 A V GS = 5V I D = 20 A Min. Typ . Max. Un it 1 1.6 2 V 0.016 0.02 0.04 0.023 Ω Ω Ω T c = 100 o C 0.019 40 V DS > I D(on) x R DS(on) max V GS = 10 V A DYNAMIC Symb ol g fs (∗) C iss C oss C rss 2/7 Parameter Test Cond ition s Forward Transconductance V DS > I D(on) x R DS(on) max Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D = 20 A VGS = 0 Min. Typ . 15 22 1800 450 180 Max. Un it S 2300 580 230 pF pF pF STP40N03L-20 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symb ol t d(on) tr (di/dt) on Qg Q gs Q gd Typ . Max. Un it Turn-on T ime Rise Time Parameter V DD = 15 V ID = 10 A VGS = 5 V R G = 4.7 Ω (see test circuit, figure 3) Test Cond ition s 20 80 30 100 ns ns Turn-on Current Slope V DD = 24 V ID = 20 A R G = 50 Ω V GS = 5 V (see test circuit, figure 5) 200 Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 24 V ID = 20 A Min. V GS = 5 V A/µs 40 10 20 60 nC nC nC Typ . Max. Un it 42 45 76 55 60 100 ns ns ns Typ . Max. Un it 40 160 A A 1.5 V SWITCHING OFF Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall T ime Cross-over T ime Test Cond ition s Min. V DD = 24 V I D = 20 A R G = 4.7 Ω V GS = 5 V (see test circuit, figure 5) SOURCE DRAIN DIODE Symb ol Parameter Test Cond ition s I SD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward O n Voltage I SD = 40 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 20 A di/dt = 100 A/µs o Tj = 150 C V DD = 24 V (see test circuit, figure 5) t rr Q rr I RRM Min. V GS = 0 65 ns 0.12 µC 4 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area ( 1) ISD ≤ 40 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 3/7 STP40N03L-20 PSPICE PARAMETERS SUBCIRCUIT COMPONENTS Symb ol Parameter Valu e S1 (V14_16<0) (See Power Mosfet Model Subcircuit) ON S2 (V16_11<0) (See Power Mosfet Model Subcircuit) ON Unit LD Drain Inductance 8 nH LG Gate Inductance 10 nH LS Source Inductance 10 RDRAIN Drain Resistance RG ATE Gate Resistance 1.9E nH -2 Ω 1 Ω CG D Gate Drain Capacitance 3.92 nF CGS Gate Source Capacitance 1.9 nF ALFA Drift Coeficient RG N Negative Bias Resistance 1E -3 V -1 10 KΩ Valu e Unit Zero Bias p-n Capacitance 2.7 nF VJ p-n Potential 0.35 V M p-n G rading Coefficient 0.55 DIODE DRAIN GATE (Depletion Capacitance) Symb ol CJO Parameter DIODE DRAIN SOURCE Symb ol CJO Parameter Zero Bias p-n Capacitance Valu e Unit 10 nF V VJ p-n Potential 0.35 M p-n G rading Coefficient 0.55 TT Transit Time 20 nsec Valu e Unit N MOSFET Symb ol Parameter L Channel Length 1 µMeter W Channel Width 1 µMeter LEVEL Model Index 3 TO X Oxide Thickness 1 VT O Zero Bias Threshold Voltage U0 THETA Vmax KP 3.25 V 600 2 cm /VS 0.005 V -1 Maximum Drift Velocity 0 Meter/sec Trans Conductance Coefficient 15 Amp/V Surface Mobility Mobility Modulation For Transient Simulation Applicate U.I.C. (Use Initial Condition) Option 4/7 Meter 2 STP40N03L-20 PSPICE NETLIST OF THE SUBCIRCUIT .SUBCKT STP40N03L-20 1 2 3 *VALUE OF THE PACKAG E INDUCTANCES LS 1 11 10n LG 2 12 10n LD 3 13 7n *RESISTA NCE O F T HE G AT E POLYSILICON RG 12 16 1 *EPY AND DRIF T RESISTANCES RD 13 14 1.9e-02 EDRI 14 15 POLY(2) (13 14) (13 11) 0 0 0 0 1e-3 *CAPACITANCE G ATE SO URCE CGS 16 11 1.90n *OPT IO NAL FO R NEGAT IVE GATE BIAS *S2 51 11 11 16 SWITCH *CGN 51 16 3.92n *RGN 51 16 10k *MILLER CAPACITANCE CGD 16 17 3.92n * DEPLET ION CAPACIT ANCE DGD 17 14 DGD S1 17 14 16 14 SW ITCH .MODEL DGD D +IS= +CJO =2.6n +Vj=.1 +M=.6 .MODEL SWITCH VSW IT CH +RON=1m +ROF F=1MEG +VON=0.1 * OUTPUT CAPACITANCE AND BODY DRAIN DIODE DBD 11 14 DBD .MODEL DBD D +TT=20n +CJO =7.8n +VJ=.1 +M=.6 * MO DEL OF THE MO SF ET MMAI N 15 16 11 11 MMAIN L=1u W =1u .MODEL MMAIN NMO S +LEVEL=3 +TOX=1 +VTO =3.25 +uo=600 +THETA=0.005 +VMAX=5e7 +KP=28 .ENDS Power Mosfet Model Subcircuit 5/7 STP40N03L-20 TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 0.551 L2 16.4 L4 0.645 13.0 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 6/7 L4 P011C STP40N03L-20 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A ... 7/7