STW9NC80Z N-CHANNEL 800V - 0.82Ω - 9.4A TO-247 Zener-Protected PowerMESH™III MOSFET TYPE STW9NC80Z n n n n n n VDSS RDS(on) ID 800 V <0.9Ω 9.4 A TYPICAL RDS(on) = 0.82Ω EXTREMELY HIGH dv/dt CAPABILITY GATE-TO-SOURCE ZENER DIODES 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED TO-247 DESCRIPTION The third generation of MESH OVERLAY™ Power MOSFETs for very high voltage exhibits unsurpassed on-resistance per unit area while integrating back-to-back Zener diodes between gate and source. Such arrangement gives extra ESD capability with higher ruggedness performance as requested by a large variety of single-switch applications. APPLICATIONS n SINGLE-ENDED SMPS IN MONITORS, COMPUTER AND INDUSTRIAL APPLICATION n WELDING EQUIPMENT ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR Parameter Drain-source Voltage (VGS = 0) Value Unit 800 V Drain-gate Voltage (RGS = 20 kΩ) 800 V Gate- source Voltage ±25 V ID Drain Current (continuous) at TC = 25°C 9.4 A ID Drain Current (continuous) at TC = 100°C 5.9 A Drain Current (pulsed) 38 A VGS IDM (1) PTOT IGS VESD(G-S) Total Dissipation at TC = 25°C 190 W Derating Factor 1.52 W/°C Gate-source Current ±50 mA Gate source ESD(HBM-C=100pF, R=15KΩ) 4 KV dv/dt(●) Peak Diode Recovery voltage slope 3 V/ns VISO Insulation Winthstand Voltage (DC) -- V Tstg Storage Temperature –65 to 150 °C 150 °C Tj Max. Operating Junction Temperature (•)Pulse width limited by safe operating area September 2002 (1)ISD ≤9.4A, di/dt ≤100A/µs, VDD ≤ V (BR)DSS, Tj ≤ T JMAX 1/8 STW9NC80Z THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max Rthc-sink Tl 0.66 °C/W 30 °C/W Thermal Resistance Case-sink Typ 0.1 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Max Value Unit AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 9.4 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 350 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS Parameter Drain-source Breakdown Voltage ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient IDSS IGSS Test Conditions ID = 250 µA, VGS = 0 Min. Typ. Max. 800 ID = 1 mA, VGS = 0 Unit V 1 V/°C Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1 µA VDS = Max Rating, TC = 125 °C 50 µA Gate-body Leakage Current (VDS = 0) VGS = ±20V ±10 µA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 4.7A ID(on) On State Drain Current VDS > ID(on) x RDS(on)max, VGS = 10V Min. Typ. Max. Unit 3 4 5 V 0.82 0.9 Ω 9.4 A DYNAMIC Symbol 2/8 Parameter gfs Forward Transconductance Ciss Input Capacitance Coss Crss Test Conditions VDS > ID(on) x RDS(on)max, ID =4.7A Min. Typ. Max. Unit 13 S 3500 pF Output Capacitance 230 pF Reverse Transfer Capacitance 25 pF VDS = 25V, f = 1 MHz, VGS = 0 STW9NC80Z ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON (RESISTIVE LOAD) Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. VDD = 400V, ID = 4.5A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 640V, ID = 9 A, VGS = 10V Typ. Max. Unit 35 ns 16 ns 72.2 101 nC 19.5 nC 24.3 nC SWITCHING OFF (INDUCTIVE LOAD) Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min. VDD = 640V, ID = 9 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Typ. Max. Unit 32 ns 42 ns 67 ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Min. Typ. Source-drain Current ISDM (2) Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 9 A, VGS = 0 trr Reverse Recovery Time Qrr Reverse Recovery Charge ISD = 9 A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) IRRM Reverse Recovery Current Max. Unit 9.4 A 38 A 1.6 V 730 ns 7.2 µC 19.5 A GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Test Conditions Min. Typ. 25 Max. Unit Gate-Source Breakdown Voltage Igs=± 1mA (Open Drain) V αT Voltage Thermal Coefficient T=25°C Note(3) 1.3 10-4/°C Rz Dynamic Resistance IGS = 50 mA, VGS = 0 90 Ω Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. ∆VBV = αT (25°-T) BVGSO(25°) PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the 25V Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 3/8 STW9NC80Z Safe Operating Area For TO-247 Thermal Impedance For TO-247 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/8 STW9NC80Z Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STW9NC80Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STW9NC80Z TO-247 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 4.7 5.3 0.185 0.209 D 2.2 2.6 0.087 0.102 E 0.4 0.8 0.016 0.031 F 1 1.4 0.039 0.055 F3 2 2.4 0.079 0.094 F4 3 3.4 0.118 0.134 G 10.9 0.429 H 15.3 15.9 0.602 0.626 L 19.7 20.3 0.776 0.779 L3 14.2 14.8 0.559 0.582 L4 34.6 1.362 L5 5.5 0.217 M 2 3 0.079 0.118 P025P 7/8 STW9NC80Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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