TDA7375 2 x 35W DUAL/QUAD POWER AMPLIFIER FOR CAR RADIO HIGH OUTPUT POWER CAPABILITY: 2 x 40W max./4Ω 2 x 35W/4Ω EIAJ 2 x 35W/4Ω EIAJ 2 x 25W/4Ω @14.4V, 1KHz, 10% 4 x 7W/4Ω @14.4V, 1KHz, 10% 4 x 12W/2Ω @14.4V, 1KHz, 10% MINIMUM EXTERNAL COMPONENTS COUNT: – NO BOOTSTRAP CAPACITORS – NO BOUCHEROT CELLS – INTERNALLY FIXED GAIN (26dB BTL) ST-BY FUNCTION (CMOS COMPATIBLE) NOAUDIBLE POPDURING ST-BYOPERATIONS DIAGNOSTICS FACILITY FOR: – CLIPPING – OUT TO GND SHORT – OUT TO VS SHORT – SOFT SHORT AT TURN-ON – THERMAL SHUTDOWN PROXIMITY Protections: OUPUT AC/DC SHORT CIRCUIT MULTIWATT15V MULTIWATT15H ORDERING NUMBERS: TDA7375V TDA7375H – TO GND – TO VS – ACROSS THE LOAD SOFT SHORT AT TURN-ON OVERRATING CHIP TEMPERATURE WITH SOFT THERMAL LIMITER LOAD DUMP VOLTAGE SURGE VERY INDUCTIVE LOADS FORTUITOUS OPEN GND REVERSED BATTERY ESD BLOCK DIAGRAM DIAGNOSTICS September 1998 1/15 TDA7375 DESCRIPTION The TDA7375 is a new technology class AB car radio amplifier able to work either in DUAL BRIDGE or QUAD SINGLE ENDED configuration. The exclusive fully complementary structure of the output stage and the internally fixed gain guaran- tees the highest possible power performances with extremely reduced component count. The on-board clip detector simplifies gain compression operation. The fault diagnostics makes it possible to detect mistakes during car radio set assembly and wiring in the car. GENERAL STRUCTURE ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vop Operating Supply Voltage 18 V VS DC Supply Voltage 28 V Peak Supply Voltage (for t = 50ms) 50 V IO Output Peak Current (not repetitive t = 100µs) 4.5 A IO Output Peak Current (repetitive f > 10Hz) 3.5 A Power Dissipation (Tcase = 85°C) 36 W -40 to 150 °C Vpeak Ptot Tstg, Tj Storage and Junction Temperature THERMAL DATA Symbol Rth j-case Description Thermal Resistance Junction-case Max PIN CONNECTION (Top view) DIAGNOSTICS 2/15 Value Unit 1.8 °C/W TDA7375 ELECTRICAL CHARACTERISTICS (Refer to the test circuit, VS = 14.4V; RL = 4Ω; f = 1KHz; T amb = 25°C, unless otherwise specified Symbol Parameter VS Supply Voltage Range Id Total Quiescent Drain Current VOS Output Offset Voltage PO Output Power PO max PO EIAJ THD CT Test Condition Min. Typ. 8 RL = ∞ Max. Unit 18 V 150 mA 150 mV THD = 10%; RL = 4Ω Bridge Single Ended Single Ended, RL = 2Ω 23 6.5 25 7 12 W W W VS = 14.4V, Bridge 36 40 W EIAJ Output Power (***) VS = 13.7V, Bridge 32 35 W Distortion R L = 4Ω Single Ended, PO = 0.1 to 4W Bridge, PO = 0.1 to 10W Max. Output Power (***) Cross Talk 0.02 0.03 f = 1KHz Single Ended f = 10KHz Single Ended f = 1KHz Bridge f = 10KHz Bridge 55 dB dB 60 dB dB KΩ KΩ Input Impedance Single Ended Bridge 20 10 30 15 GV Voltage Gain Single Ended Bridge 19 25 20 26 GV Voltage Gain Match EIN Input Noise Voltage Bridge Rg = 0; 22Hz to 22KHz SVR Supply Voltage Rejection R g = 0; f = 300Hz 50 A SB Stand-by Attenuation PO = 1W 80 ISB ST-BY Current Consumption VST-BY = 0 to 1.5V V SB ST-BY In Threshold Voltage V SB ST-BY Out Threshold Voltage Ipin7 ST-BY Pin Current % % 70 60 R IN R g = 0; ”A” weighted, S.E. Non Inverting Channels Inverting Channels 0.3 21 27 dB dB 0.5 dB 2 5 µV µV 3.5 µV 90 dB dB 1.5 µA V Play Mode V pin7 = 5V 50 µA Max Driving Current Under Fault (*) 5 mA 100 3.5 V Icd off Clipping Detector Output Average Current d = 1% (**) 90 µA Icd on Clipping Detector Output Average Current d = 5% (**) 160 µA Voltage Saturation on pin 10 Sink Current at Pin 10 = 1mA Vsat pin10 0.7 V (*) See built-in S/C protection description (**) Pin 10 Pulled-up to 5V with 10KΩ; RL = 4Ω (***) Saturated square wave output. 3/15 TDA7375 STANDARD TEST AND APPLICATION CIRCUIT Figure 1: Quad Stereo 10K R1 VS C5 1000µF ST-BY C7 10µF 7 4 IN FL C6 100nF 13 3 1 C1 0.22µF IN FR 5 12 C4 0.22µF IN RR C9 2200µF OUT FR C11 2200µF OUT RL C12 2200µF OUT RR 15 11 Note: C9, C10, C11, C12 could be reduced if the 2Ω operation is not required. OUT FL 2 C2 0.22µF IN RL C10 2200µF C3 0.22µF 6 14 8 9 10 C8 47µF DIAGNOSTICS D94AU063A Figure 2: Double Bridge 10K R1 ST-BY C5 10µF IN L 7 4 C1 0.47µF IN R 13 3 1 5 OUT L 2 12 C2 0.47µF 15 11 OUT R 6 C8 47µF VS C3 1000µF C4 100nF 14 8 9 10 DIAGNOSTICS D94AU064A Figure 3: Stereo/Bridge 10K ST-BY VS 10µF IN L 100nF 13 7 4 3 1 5 2 0.22µF IN BRIDGE 2200µF 12 0.47µF OUT L 2200µF 0.22µF IN L 1000µF 15 OUT BRIDGE 11 6 8 OUT R 9 10 14 47µF DIAGNOSTICS 4/15 D94AU065A TDA7375 Figure 4: P.C. Board and Component Layout of the fig.1 (1:1 scale). Figure 5: P.C. Board and Component Layout of the fig.2 (1:1 scale). 5/15 TDA7375 Figure 6: Quiescent Drain Current vs. Supply Voltage (Single Ended and Bridge). RL = 4Ω Vi = 0 Figure 8: Output Power vs. Supply Voltage S.E. RL = 2Ω f = 1KHz Figure 10: Output Power vs. Supply Voltage BTL RL = 4Ω f = 1KHz Figure 7: Quiescent Output Voltage vs. Supply Voltage (Single Ended and Bridge). RL = 4Ω Vi = 0 Figure 9: Output Power vs. Supply Voltage S.E. RL = 4Ω f = 1KHz Figure 11: Distortion vs. Output Power S.E. VS = 14.4V RL = 2Ω f = 15KHz f = 1KHz 6/15 TDA7375 Figure 12: Distortion vs. Output Power Figure 13: Distortion vs. Output Power S.E. VS = 14.4V RL = 4Ω f = 15KHz f = 15KHz f = 1KHz f = 1KHz Figure 14: Cross-talk vs. Frequency S.E. VS = 14.4V RL = 4Ω Rg = 10Ω Figure 16: SupplyVoltage Rejection vs. Frequency S.E. Rg = 0 CSVR = 47µF Vripple = 1Vrms BTL VS = 14.4V RL = 4Ω Figure 15: Supply Voltage Rejection vs. Frequency BTL Rg = 0 CSVR = 47µF Vripple = 1Vrms Figure 17: Stand-byAttenuation vs. Threshold Voltage BTL & S.E. VS = 14.4V RL = 4Ω 0 dB = 1W 7/15 TDA7375 Figure 18: Total Power Dissipation and Efficiency vs. Output Power Figure 19: Total Power Dissipation and Efficiency vs. Output Power. Ptot S.E. VS = 14.4V RL = 4 x 4Ω f = 1KHz 8/15 Ptot BTL VS = 14.4V RL = 2 x 4Ω f = 1KHz TDA7375 High Application Flexibility The availability of 4 independent channels makes it possible to accomplish several kinds of applications ranging from 4 speakers stereo (F/R) to 2 speakers bridge solutions. In case of working in single ended conditions the polarity of the speakers driven by the inverting amplifier must be reversed respect to those driven by non inverting channels. This is to avoid phase inconveniences causing sound alterations especially during the reproduction of low frequencies. Easy Single Ended to Bridge Transition The change from single ended to bridge configurations is made simply by means of a short circuit across the inputs, that is no need of further external components. Gain Internally Fixed to 20dB in Single Ended, 26dB in Bridge Advantages of this design choice are in terms of: components and space saving output noise, supply voltage rejection and distortion optimization. Silent Turn On/Off and Muting/Stand-by Function The stand-by can be easily activated by means of a CMOS level applied to pin 7 through a RC filter. Under stand-by condition the device is turned off completely (supply current = 1µA typ.; output attenuation= 80dB min.). Every ON/OFF operation is virtually pop free. Furthemore, at turn-on the device stays in muting condition for a time determined by the value assigned to the SVR capacitor. While in muting the device outputs becomes insensitive to any kinds of signal that may be present at the input terminals. In other words every transient coming from previous stages produces no unplesant acoustic effect to the speakers. STAND-BY DRIVING (pin 7) Some precautions have to be taken in the definition of stand-by driving networks: pin 7 cannot be directly driven by a voltage source whose current capability is higher than 5mA. In practical cases a series resistance has always to be inserted, having it the double purpose of limiting the current at pin 7 and to smooth down the stand-by ON/OFF transitions - in combination with a capacitor - for output pop prevention. In any case, a capacitor of at least 100nF from pin 7 to S-GND, with no resistance in between, is necessary to ensure correct turn-on. OUTPUT STAGE The fully complementary output stage was made possible by the development of a new component: the ST exclusive power ICV PNP. A novel design based upon the connection shown in fig. 20 has then allowed the full exploitation of its possibilities. The clear advantages this new approach has over classical output stages are as follows: Rail-to-Rail Output Voltage Swing With No Need of Bootstrap Capacitors. The output swing is limited only by the VCEsat of the output transistors, which is in the range of 0.3Ω (Rsat) each. Classical solutions adopting composite PNPNPN for the upper output stage have higher saturation loss on the top side of the waveform. This unbalanced saturation causes a significant power reduction. The only way to recover power consists of the addition of expensive bootstrap capacitors. Absolute Stability Without Any External Compensation. Referring to the circuit of fig. 20 the gain VOut/VIn is greater than unity, approximately 1+ R2/R1. The DC output (VCC/2) is fixed by an auxiliary amplifier common to all the channels. By controlling the amount of this local feedback it is possible to force the loop gain (A*β) to less than unity at frequency for which the phase shift is 180°. This means that the output buffer is intrinsically stable and not prone to oscillation. Most remarkably, the above feature has been achieved in spite of the very low closed loop gain of the amplifier. In contrast, with the classical PNP-NPN stage, the solution adopted for reducing the gain at high frequencies makes use of external RC networks, namely the Boucherot cells. BUILT–IN SHORT CIRCUIT PROTECTION Figure 20: The New Output Stage 9/15 TDA7375 Reliable and safe operation, in presence of all kinds of short circuit involving the outputs is assured by BUILT-IN protectors. Additionally to the AC/DC short circuit to GND, to VS, across the speaker, a SOFT SHORT condition is signalled out during the TURN-ON PHASE so assuring correct operation for the device itself and for the loudspeaker. This particular kind of protection acts in a way to avoid that the device is turned on (by ST-BY) when a resistive path (less than 16 ohms) is present between the output and GND. As the involved circuitry is normally disabled when a current higher than 5mA is flowing into the ST-BY pin, it is important, in order not to disable it, to have the external current source driving the STBY pin limited to 5mA. This extra function becomes particularly attractive when, in the single ended configuration, one capacitor is shared between two outputs (see fig. 21). Figure 22: Clipping Detection Waveforms Figure 21. A current sinking at pin 10 is triggered when a certain distortion level is reached at any of the outputs. This function allows gain compression possibility whenever the amplifier is overdriven. Supposing that the output capacitor C out for any reason is shorted, the loudspeaker will not be damaged being this soft short circuit condition revealed. Diagnostics Facility The TDA7375 is equipped with a diagnostic circuitry able to detect the following events: Clipping in the output signal Thermal shutdown Output fault: – short to GND – short to VS – soft short at turn on The information is available across an open collector output (pin 10) through a current sinking when the event is detected 10/15 Thermal Shutdown In this case the output 10 will signal the proximity of the junction temperature to the shutdown threshold. Typically current sinking at pin 10 will start ~10°C before the shutdown threshold is reached. HANDLING OF THE DIAGNOSTICS INFORMAFigure 23: Output Fault Waveforms (see fig. 24) TDA7375 TDA7375 Figure 24: Fault Waveforms ST-BY PIN VOLTAGE 2V t OUT TO Vs SHORT OUTPUT WAVEFORM SOFT SHORT t OUT TO GND SHORT Vpin 10 CORRECT TURN-ON FAULT DETECTION t CHECK AT TURN-ON (TEST PHASE) TION As various kinds of information is available at the same pin (clipping detection, output fault, thermal proximity), this signal must be handled properly in D94AU149A SHORT TO GND OR TO Vs order to discriminate each event. This could be done by taking into account the different timing of the diagnostic output during each case. Figure 25: Waveforms ST-BY PIN VOLTAGE t Vs OUTPUT WAVEFORM t Vpin 10 WAVEFORM t CLIPPING D94AU150 SHORT TO GND OR TO Vs THERMAL PROXIMITY 11/15 TDA7375 Normally the clip detector signalling produces a low level at pin 10 that is shorter than that present under faulty conditions; based on this assumption an interface circuitry to differentiate the information is represented in the schematic of fig. 26. Figure 26. TDA7375 PCB-LAYOUT GROUNDING (general rules) The device has 2 distinct ground leads, P-GND (POWER GROUND) and S-GND (SIGNAL GROUND) which are practically disconnected from each other at chip level. Proper operation requires that P-GND and S-GND leads be connected together on the PCB-layout by means of reasonably low-resistance tracks. As for the PCB-ground configuration, a star-like arrangement whose center is represented by the supply-filtering electrolytic capacitor ground is highly advisable. In such context, at least 2 separate paths have to be provided, one for P-GND and one for S-GND. The correct ground assign- 12/15 ments are as follows: STANDBY CAPACITOR, pin 7 (or any other standby driving networks): on S-GND SVR CAPACITOR (pin 6): on S-GND and to be placed as close as possible to the device. INPUT SIGNAL GROUND (from active/passive signal processor stages): on S-GND. SUPPLY FILTERING CAPACITORS (pins 3,13): on P-GND. The (-) terminal of the electrolytic capacitor has to be directly tied to the battery (-) line and this should represent the starting point for all the ground paths. TDA7375 DIM. mm MIN. TYP. A B inch MAX. MIN. TYP. 5 2.65 C MAX. 0.197 0.104 1.6 0.063 D E 0.49 0.55 0.019 F 0.66 0.75 0.026 G G1 1.02 17.53 1.27 17.78 1.52 18.03 0.040 0.690 1 0.039 H1 19.6 21.9 22.2 20.2 22.5 L1 21.7 22.1 L2 17.65 L3 L4 17.25 10.3 L7 M 0.022 0.030 0.050 0.700 0.060 0.710 0.862 0.874 0.795 0.886 22.5 0.854 0.870 0.886 18.1 0.695 17.5 10.7 17.75 10.9 0.679 0.406 0.689 0.421 0.699 0.429 2.65 4.25 4.55 2.9 4.85 0.104 0.167 0.179 0.114 0.191 M1 4.63 5.08 5.53 0.182 0.200 0.218 S S1 1.9 1.9 2.6 2.6 0.075 0.075 0.102 0.102 Dia1 3.65 3.85 0.144 0.152 H2 L OUTLINE AND MECHANICAL DATA 0.772 0.713 Multiwatt15 V 13/15 TDA7375 mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 5 0.197 B 2.65 0.104 C 1.6 0.063 E 0.49 0.55 0.019 0.022 F 0.66 0.75 0.026 0.030 G 1.14 1.27 1.4 0.045 0.050 0.055 G1 17.57 17.78 17.91 0.692 0.700 0.705 H1 19.6 0.772 H2 20.2 0.795 L 20.57 0.810 L1 18.03 0.710 L2 2.54 0.100 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 L5 5.28 L6 0.208 2.38 0.094 L7 2.65 2.9 0.104 0.114 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 14/15 OUTLINE AND MECHANICAL DATA Multiwatt15 H TDA7375 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics MULTIWATT is a Registered Trademark of the STMicroelectronics 1998 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 15/15