STMICROELECTRONICS TSH321ID

TSH321

WIDE BANDWIDTH AND MOS INPUTS
SINGLE OPERATIONAL AMPLIFIER
LOW DISTORTION
GAIN BANDWIDTH PRODUCT : 300MHz
GAIN OF 2 STABILITY
SLEW RATE : 400V/µs
VERY FAST SETTLING TIME : 60ns (0.1%)
VERY HIGH INPUT IMPEDANCE
DESCRIPTION:
The TSH321 is a wideband monolithic operational
amplifier, requiring a minimum close loop gain of 2
for stability.
The TSH321 features extremely high input impedance (typically greater than 1012Ω) allowing direct
interfacing with high impedance sources.
Low distortion, wide bandwidth and high linearity
make this amplifier suitable for RF and video applications. Short circuit protection is provided by an
internal current-limiting circuit.
The TSH321 has internal electrostatic discharge
(ESD) protection circuits and fulfills MILSTD883CClass2.
N
DIP8
(Plastic Package)
D
SO8
(Plastic Micropackage)
ORDER CODES
Part
Number
Temperature
Range
TSH321I
-40 C, 125 C
o
o
Package
N
D
•
•
321-01.TBL
..
..
..
PIN CONNECTIONS (top view)
Offset Null 1
1
8
Inverting Input
2
7 VCC+
Non-inverting Input
3
6
Output
4
5
N.C.
321-01.EPS
V CC
Offset Null 2
June 1998
1/6
TSH321
SCHEMATIC DIAGRAM
7 V CC +
Internal
Vref
non inverting
input
3
6
output
Cc
2
inverting
input
1
Offset N1
8
Offset N2
321-02.EPS
4
VCC-
INPUT OFFSET VOLTAGE NULL CIRCUIT
TSH321
N2
N1
321-03.EPS
100kΩ
V CC
Symbol
Value
Unit
VCC
Supply Voltage
±7
V
Vid
Differential Input Voltage
±5
V
Vi
Input Voltage Range
±5
V
Iin
Current On Offset Null Pins
± 20
mA
Toper
Parameter
Operating Free-Air Temperature Range
TSH321I
-40oC, 125oC
o
C
321-02.TBL
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
2/6
Parameter
VCC
Supply Voltage
Vic
Common Mode Input Voltage Range
Value
Unit
± 3 to ± 6
V
VCC- to VCC+ -3
V
321-03.TBL
Symbol
TSH321
ELECTRICAL CHARACTERISTICS
VCC = ± 5V, Tamb = 25oC (unless otherwise specified)
DV io
Iib
Iio
ICC
Avd
Vicm
CMR
SVR
Vo
Parameter
Input Offset Voltage
Tmin ≤ Tamb ≤ Tmax.
Input Offset Voltage Drift
Tmin ≤ Tamb ≤ Tmax.
Input Bias Current
Input Offset Current
Supply Current, no load
Tmin ≤ Tamb ≤ Tmax.
Large Signal Voltage Gain
Vo = ±2.5V
GBP
SR
en
Kov
ts
tr, tf
td
∅m
THD
FPB
VCC = ± 5V
VCC = ± 3V
VCC = ±6V
VCC = ± 5V
See test waveform figure
Note 2 :
Full power bandwidth =
23
21
25
Max.
10
12
Unit
mV
µV/oC
300
200
pA
pA
mA
30
28
40
32
V/V
800
300
200
-5 to +2
60
1300
850
650
-5.5 to +2.5
100
50
±3
70
+3.5
-3.7
+3.3
-3.5
RL = 50Ω
± 2.8
RL = 100Ω
RL = 50Ω
± 2.9
± 2.7
Output Short Circuit Current
Vid = ±1V, Vo = 0V
Gain Bandwidth Product
AVCL = 100, R L = 100Ω, CL = 15pF, f = 7.5MHz
Slew Rate
Vin = ± 1V, AVCL = 2 RL = 100Ω, CL = 15pF
Equivalent Input Voltage Noise
R S = 50Ω
fo = 1kHz
fo = 10kHz
fo = 100kHz
fo = 1MHz
Overshoot
Vin = ± 1V AVCL = 2, RL = 100Ω, CL = 15pF
Settling Time 0.1% - (note 1)
Vin = ± 1V, AVCL = -1
Rise and Fall Time - (note 1)
Vin = ±100mV, AVCL = 2
Delay Time - (note 1)
Vin = ±100mV, AVCL = 2
Phase Margin
AVM = 2, RL = 100Ω, CL = 15pF
Total Harmonic Distortion
AVCL = 10, f = 1KHz, Vo = ± 2.5V, no load
Full Power Bandwidth - (note 2)
Vo = 5Vpp, R L = 100Ω
Vo = 2Vpp, R L = 100Ω
Note 1 :
Typ.
0.5
10
2
2
RL = ∞
RL= 100Ω
RL = 50Ω
Input Common Mode Voltage Range
Common Mode Rejection Ratio
Vic = Vicm min.
Supply Voltage Rejection Ratio
VCC = ± 5V to ± 3V
Output Voltage
RL = 100Ω
Tmin ≤ Tamb ≤ Tmax.
Io
Min.
± 50
± 100
V
dB
dB
V
mA
MHz
300
V/µs
200
400
20
18.2
18.1
18.2
nV
√

Hz
%
15
ns
60
ns
2
ns
2
Degrees
45
%
0.02
MHz
321-04.TBL
Symbol
Vio
26
64
SR
Π Vopp
3/6
TSH321
TEST WAVEFORM
EVALUATION CIRCUIT
+5V
10µF
50Ω
10nF
ts
Input
0.1% of edge amplitude
50Ω
Output
90%
50%
1kΩ
td
10nF
tr
10%
Vin
10µF
1kΩ
CF
PRINTED CIRCUIT LAYOUT
As for any high frequency device, a few rules must
be observed when designing the PCB to get the best
performances from this high speed op amp.
From the most to the least important points :
• Each power supply lead has to be bypassed
to ground with a 10nF ceramic capacitor very
close to the device and a 10µF tantalum capacitor.
• Use small resistor values to decrease time
constant with parasitic capacitance.
• Choose component sizes as small as possible
(SMD).
• On output, decrease capacitor load so as to
common return, use a ground plane or common point return for power and signal.
avoid circuit stability being degraded which
may cause oscillation. One can also add a
serial resistor in order to minimise its influence.
• All leads must be wide and as short as possi-
• One can add in parallel with feedback resistor
ble especially for op amp inputs. This is in
order to decrease parasitic capacitance and
a few pF ceramic capacitor CF adjusted to
optimize the settling time.
• To provide low inductance and low resistance
4/6
inductance.
321-05.EPS
321-04.EPS
-5V
TSH321
PM-DIP8.EPS
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC DIP
A
a1
B
b
b1
D
E
e
e3
e4
F
i
L
Z
Min.
Millimeters
Typ.
3.32
0.51
1.15
0.356
0.204
Max.
1.65
0.55
0.304
10.92
9.75
7.95
Min.
0.020
0.045
0.014
0.008
Max.
0.065
0.022
0.012
0.430
0.384
0.313
2.54
7.62
7.62
3.18
Inches
Typ.
0.131
0.100
0.300
0.300
6.6
5.08
3.81
1.52
0.125
0260
0.200
0.150
0.060
DIP8.TBL
Dimensions
5/6
TSH321
PM-SO8.EPS
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC MICROPACKAGE (SO)
A
a1
a2
a3
b
b1
C
c1
D
E
e
e3
F
L
M
S
Min.
Millimeters
Typ.
0.1
0.65
0.35
0.19
0.25
Max.
1.75
0.25
1.65
0.85
0.48
0.25
0.5
Min.
Inches
Typ.
0.026
0.014
0.007
0.010
Max.
0.069
0.010
0.065
0.033
0.019
0.010
0.020
0.189
0.228
0.197
0.244
0.004
o
45 (typ.)
4.8
5.8
5.0
6.2
1.27
3.81
3.8
0.4
0.050
0.150
4.0
1.27
0.6
0.150
0.016
0.157
0.050
0.024
o
8 (max.)
SO8.TBL
Dimensions
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ORDER CODE :
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