VIPer20B VIPer20BSP SMPS PRIMARY I.C. PRELIMINARY DATA T YPE V DSS In R DS(on) VIPer20B/ SP 400V 1.3 A 8.7 Ω 10 1 FEATURE ■ ADJUSTABLE SWITCHING FREQUENCY UP TO 200KHZ ■ CURRENT MODE CONTROL ■ SOFT START AND SHUT DOWN CONTROL ■ AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET ”BLUE ANGEL” NORM (1W TOTAL POWER CONSUMPTION) ■ INTERNALLY TRIMMED ZENER REFERENCE ■ UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS ■ INTEGRATED START-UP SUPPLY ■ AVALANCHE RUGGED ■ OVERTEMPERATURE PROTECTION ■ LOW STAND-BY CURRENT ■ ADJUSTABLE CURRENT LIMITATION PENTAWATT HV Power SO-10 DESCRIPTION VIPer20B combines on the same silicon chip a state-of-the-art PWM circuit together with an optimized high voltage avalanche rugged Vertical Power MOSFET (400V 1.3A). Typical applications cover off line power supplies with a secondary max power capability of 30W. It is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. Burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components. BLOCK DIAGRAM DRAIN OSC ON/OFF OSCILLATOR SECURITY LATCH UVLO LOGIC VDD R/S PWM LATCH FF Q S R1 S FF Q R2 R3 OVERTEMP. DETECTOR 0.5 V + _ _ 13 V 2 µs delay 300 ns Blanking + 0.5V _ + 6 V/A _ CURRENT AMPLIFIER ERROR AMPLIFIER + COMP September 1999 SOURCE FC00490 4.5 V 1/17 VIPer20B / VIPer20BSP ABSOLUTE MAXIMUM RATING Symb ol V DS ID VDD V OSC V COMP I COMP V esd I D(AR) P tot Tj T s tg Parameter o Continuous Drain-Source Voltage (T j = 25 to 125 C) Maximum Current Supply Voltage Voltage Range Input Voltage Range Input Maximum Continuous Current Electrostatic discharge (R = 1.5 KΩ C = 100pF) Avalanche Drain-Source Current, Repetitive or Not-Repetitive (T C = 100 o C, Pulse W idth Limited by T J max, δ <1%) o Power Dissipation at Tc = 25 C Junction Operating Temperature Storage Temperature Value -0.3 to 400 Internally Limited 0 to 15 0 to V DD 0 to 5 ±2 2000 T BD Unit V A V V V mA V A 57 -40 to 140 -65 to 150 W C o C o THERMAL DATA R t hj-ca se R th j-a mb. Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max 2.0 o C/W 70 o C/W CONNECTION DIAGRAMS (Top View) PENTAWATT HV PowerSO-10 CURRENT AND VOLTAGE CONVENTIONS IDD ID VD D IOSC DR AIN OSC 13V + COMP SOURCE VDD VDS ICOMP VOSC VCOMP FC00020 2/17 VIPer20B / VIPer20BSP ORDERING NUMBERS PENT AW ATT HV PowerSO -10 VIPer20B VIPer20BSP PINS FUNCTIONAL DESCRIPTION DRAIN PIN: Integrated power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. SOURCE PIN: Power MOSFET source pin. Primary side circuit common ground connection. VDD PIN : This pin provides two functions : - It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below 8V, the start-up current source is activated and the output power MOSFET is switched off until the VDD voltage reaches 11V. During this phase, the internal current consumption is reduced, the VDD pin is sourcing a current of about 1mA and the COMP pin is shorted to ground. After that, the current source is shut down, and the device tries to start up by switching again. - This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to stuck the output of the transconductance amplifier to the high state. The COMP pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage will be somewhat higher than the nominal one, but still under control. COMP PIN : This pin provides two functions : - It is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. Its bandwidth can be easily adjusted to the needed value with usual components value. As stated above, secondary regulation configurations are also implemented through the COMP pin. - When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (whatever is the configuration) to provide a burst mode operation in case of negligible output power or open load condition. OSC PIN : An RT-CT network must be connected on that pin to define the switching frequency. Note that despite the connection of RT to VDD, no significant frequency change occurs for VDD varying from 8V to 15V. It provides also a synchronisation capability, when connected to an external frequency source. 3/17 VIPer20B / VIPer20BSP ELECTRICAL CHARACTERISTICS (TJ = 25 oC, VDD = 13 V, unless otherwise specified) POWER SECTION Symb ol BV DSS I DSS Parameter Drain-Source Voltage Test Cond ition s I D = 10 mA I D = 0.9 A I D = 0.9 A tf Fall Time I D = 0.1 A (see fig. 3) tr Rise Time I D = 0.9 A (see fig. 3) Output Capacitance V DS = 25 V C OSS Typ . Max. 400 TJ = 125 C 7.3 o TJ= 100 C Vin = 300 V (1) V i n = 300 V (1) Un it V o Off-State Drain Current V DS = 300 V V COMP = 0 V Static Drain Source on Resistance R DS( on) Min. V COMP = 0 V 0.6 mA 8.7 15.7 Ω Ω 80 ns 50 ns 90 pF (1) On Inductive Load, Clamped. SUPPLY SECTION Symb ol Parameter Test Cond ition s Min. Typ . Max. Un it I DDch Start-up Charging Current V DD = 0 to VDDon (see fig. 2) I DD0 Operating Supply Current V DD = 12 V, F SW = 0 KHz (see fig. 2) 12 I DD1 Operating Supply Current V DD = 12 V, F SW = 100 KHz 13 mA I DD2 Operating Supply Current V DD = 12 V, F SW = 200 KHz 14 mA V DDo ff Undervoltage Shutdown (see fig. 2) 8 V V DDo n Undervoltage Reset (see fig. 2) 11 VDDhyst Hysteresis Start-up (see fig. 2) V DS = 70 V -2 mA T BD 12 mA V 2.4 3 V Min. Typ . Max. Un it 90 100 110 KHz 80 100 120 KHz OSCILLATOR SECTION Symb ol Parameter Test Cond ition s F SW1 Oscillator Frequency Initial Accuracy R T = 8.2 KΩ (see fig.7) F SW2 Oscillator Frequency Total Variation C T =2.4 nF R T = 8.2 KΩ V DD = 9 to15 V TJ = 0 to 100 o C C T =2.4 nF V OSCih Oscillator Peak Voltage 7.1 V V OSCi l Oscillator Valley Voltage 3.7 V 4/17 VIPer20B / VIPer20BSP ELECTRICAL CHARACTERISTICS (continued) ERROR AMPLIFIER SECTION Symb ol V DDreg ∆V DDreg Parameter VDD Regulation Point Test Cond ition s I COMP = 0 mA (see fig.1) Min. Typ . Max. Un it 12.6 13 13.4 V o Total Variation T J = 0 to 100 C GBW Unity G ain Bandwidth From Input = VDD to Output = V COMP CO MP pin is open (see fig. 8) A VOL Open Loop Voltage Gain CO MP pin is open (see fig. 8) DC T ransconductance V COMP = 2.5 V V COMPL O Output Low Level I COMP = -400 µA V DD = 14 V V COMPHI Output High Level I COMP = 400 µA V DD = 12 V 4.5 V I COMPLO Output Low Current Capability V COMP = 2.5 V V DD = 14 V -600 µA I COMPHI Output High Current Capability V COMP = 2.5 V V DD = 12 V 600 µA Gm (see fig. 1) 2 % 150 KHz TBD 50 dB TBD 1.5 T BD 0.2 mA/V V PWM COMPARATOR SECTION Symb ol H ID V COMPof f I Dpeak Parameter Test Cond ition s ∆V COMP /∆IDpea k V COMP = 1 to 3 V V COMP offset I Dp eak = 10 mA Peak Current Limitation V DD = 12 V td Current Sense Delay to turn-off tb Blanking Time COMP pin open Min. Typ . Max. Un it TBD 2.3 T BD V/A 0.5 1.3 I D = 0.4 A V T BD A 250 ns 300 ns SHUTDOWN AND OVERTEMPERATURE SECTION Symb ol Parameter V COMPth Restart threshold (see fig. 4) t DI Ssu Test Cond ition s Disable Set Up T ime (see fig. 4) T t sd Thermal Shutdown Temperature (see fig. 6) T hyst Thermal Shutdown Hysteresis (see fig. 6) Min. Typ . Max. 0.5 1.7 140 Un it V 5 µs 160 o C 34 o C 5/17 VIPer20B / VIPer20BSP Figure 1: VDD Regulation Point ICOMP Figure 2: Undervoltage Lockout IDD Slope = Gm in mA/V ICOMPHI IDD0 VDD VDS = 70 V Fsw = 0 VDDhyst 0 VDDoff ICOMPLO VDD VDDon IDDch VDDreg FC00150 Figure 3: Transition Time FC00170 Figure 4: Shut Down Action VOSC ID t VCOMP 10% Ipeak VDS t tDISsu VCOMPth t 90% VD ID 10% VD t tf t tr ENABLE FC00160 ENABLE DISABLE FC00060 6/17 VIPer20B / VIPer20BSP Figure 5: Start-up Waveforms Figure 6: Overtemperature Protection Ttsd Tj Thyst t ID t VDD VDDon t VCOMP t FC10192 7/17 VIPer20B / VIPer20BSP Figure 7: Oscillator VDD Rt For RT > 1.2 KΩ: 2.3 FSW = D RT CT MAX OSC CLK ~360Ω Ct DMAX = 1 − 550 RT − 150 Recommended DMAX values: 100KHz: > 80% 200KHz: > 70% FC00050 Maximum duty cycle vs Rt FC00040 1 0.9 Dmax 0.8 0.7 0.6 0.5 1 2 3 5 10 20 30 50 Rt (kΩ) Oscillator frequency vs Rt and Ct FC00030 1,000 Ct = 1.5 nF 500 Frequency (kHz) Ct = 2.7 nF 300 Ct = 4.7 nF 200 Ct = 10 nF 100 50 30 1 2 3 5 Rt (kΩ) 8/17 10 20 30 50 VIPer20B / VIPer20BSP Figure 8: Error Amplifier Frequency Response FC00200 60 RCOMP = +∞ Voltage Gain (dB) RCOMP = 270k 40 RCOMP = 82k RCOMP = 27k 20 RCOMP = 12k 0 (20) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 Figure 9: Error Amplifier Phase Response FC00210 200 RCOMP = +∞ 150 RCOMP = 270k Phase (°) RCOMP = 82k RCOMP = 27k 100 RCOMP = 12k 50 0 (50) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 9/17 VIPer20B / VIPer20BSP Figure 10: Off Line Power Supply With Auxliary Supply Feedback F1 C1 BR1 TR2 TR1 D2 ACIN L2 +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C1 0 R7 C4 R2 VDD DRAIN OSC 13V VIPer + COMP SOURCE C5 C6 C11 R3 FC00402 Figure 11: Off Line Power Supply With Optocoupler Feedback F1 BR1 TR2 C1 TR1 AC IN D2 L2 +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C1 0 R7 C4 R2 VDD DRAIN OSC 13V VIPer + COMP SOURCE C5 C11 C6 R6 ISO1 R3 R4 C8 U2 R5 FC 00412 10/17 VIPer20B / VIPer20BSP OPERATION DESCRIPTION : CURRENT MODE TOPOLOGY: The current mode control method, like the one integrated in the VIPer20B uses two control loops - an inner current control loop and an outer loop for voltage control. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage VS proportional to this current. When VS reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. This results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in the case of short circuit. During a first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct. For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. STAND-BY MODE Stand-by operation in nearly open load condition automatically leads to a burst mode operation allowing voltage regulation on the secondary side. The transition from normal operation to burst mode operation happens for a power PSTBY given by : 1 2 PSTBY = LP ISTBY FSW 2 Where: LP is the primary inductance of the transformer. FSW is the normal switching frequency. ISTBY is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. This current can be computed as : (tb + td) VIN ISTBY = LP tb + td is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and represents roughly the minimum on time of the device. Note that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13V regulation level forcing the output voltage of the transconductance amplifier to low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power switch is maintained in the off state, resulting in missing cycles and zero duty cycle. As soon as VDD gets back to the regulation level and the VCOMPth threshold is reached, the device operates again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input mains lines. This mode of operation allows the VIPer20B to meet the new German ”Blue Angel” Norm with 1W total power consumption for the system when working in stand-by. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the output capacitors and of the low output current drawn in such conditions.The normal operation resumes automatically when the power get back to higher levels than PSTBY. HIGH VOLTAGE START-UP CURRENT SOURCE An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced 11/17 VIPer20B / VIPer20BSP consumption and also provided to the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on figure 12. In case of abnormal condition where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor discharges itself down to the low threshold voltage VDDoff of the UVLO logic, and the device get back to the inactive state where the internal circuits are in standby mode and the start up current source is activated. The converter enters a endless start up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPer20B tries to start. This ratio is fixed by design to 2 to 14, which gives a 13% start up duty cycle while the power dissipation at start up is approximately 1W, for a 230 Vrms input voltage. This low value of start-up duty cycle prevents the stress of the output rectifiers and of the transformer when in short circuit. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature and compensation network implemented on the COMP pin. The following formula can be used for defining the minimum capacitor needed: IDD tSS CVDD > VDDhyst where: IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. VDDhyst is the voltage hysteresis of the UVLO logic. Refer to the minimum specified value. Soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of figure 13 can be used. It mixes a high performance compensation Figure 12: Behaviour of the high voltage current source at start-up VDD 2 mA VDDo n VDDoff 15 mA 3 mA VDD 1 mA DRAIN 15 mA C VDD Ref. t UNDERVOLTAGE LOCK OUT LOGIC Auxiliary primary wind in g VIPer Start up dut y cycle ~ 10 % 12/17 SOUR CE FC00422 VIPer20B / VIPer20BSP network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by putting the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption doesn’t exceed 0.5mA. Figure 14 shows a typical application of this function, with a latched shut down. Once the ”Shutdown” signal has been activated, the device remains in the off state until the input voltage is removed. TRANSCONDUCTANCE ERROR AMPLIFIER The VIPer30B includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (VDD). Thus: ∂ ICOMP Gm = ∂ VDD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: ∂ VCOMP ∂ VCOMP 1 ZCOMP = = x ∂ ICOMP Gm ∂ VDD This last equation shows that the open loop gain AVOL can be related to Gm and Z COMP: AVOL = Gm x ZCOMP where Gm value for VIPer20B is 1.5 mA/V typically. Gm is well defined by specification, but ZCOMP Figure 13: Mixed Soft Start and Compensation and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define more accurately the transfer function F of the error amplifier, according to the following equation, very similar to the one above: F(S) = Gm x Z(S) The error amplifier frequency response is reported in figure 8 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330 KΩ. More complex impedance can be connected on the COMP pin to achieve different compensation laws. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated on figure 15. As shown in figure 15 an additional noise filtering capacitor of 2.2 nF is generally needed to avoid any high frequency interference. It can be also interesting to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. Figure 16 shows such a configuration. Note that R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. EXTERNAL CLOCK SYNCHRONIZATION: The OSC pin provides a synchronisation capability, when connected to an external frequency source. Figure 17 shows one possible Figure 14: Latched Shut Down D2 D3 VIPer VDD VIPer R1 DRAIN VDD OSC 13V Q2 R3 + 13V COMP SO URCE D1 + COMP SOURCE AUXILIARY WINDING R3 R2 R1 C4 R2 + C3 DRAIN - OSC C1 R4 Shutdown + C2 FC00432 Q1 D1 FC00442 13/17 VIPer20B / VIPer20BSP schematic to be adapted depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. where: PRIMARY PEAK CURRENT LIMITATION The primary IDPEAK current and, as resulting effect, the output power can be limited using the simple circuit shown in figure 18. The circuit based on Q1, R1 and R2 clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value: VCOMP − 0.5 IDPEAK = HID OVER-TEMPERATURE PROTECTION: Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140oC while the typical value is 160oC. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 34oC below the shutdown value (see figure 6). Figure 15: Typical Compensation Network Figure 16: Slope Compensation VCOMP = 0.6 x R1 + R2 R2 The suggested value for R1+R2 is in the range of 220KΩ. VIPer VDD R2 DRAIN R1 VIPer - OSC 13V VDD + DRAIN - OSC COMP SOURCE 13V + COMP C2 R1 SOURCE C2 C1 Q1 C1 C3 R3 F C00452 FC00462 Figure 17:External Clock Synchronization Figure 18:Current Limitation Circuit Example VIPer VDD OSC 13V VIPer VDD DRAIN + COMP SOURCE DRAIN OSC 13V + COMP SOURCE R1 10 kΩ Q1 R2 FC00 472 FC 00 482 14/17 VIPer20B / VIPer20BSP PENTAWATT HV (VERTICAL) MECHANICAL DATA DIM. mm TYP. MIN. 4.30 1.17 2.40 0.35 0.60 4.90 7.42 9.30 A C D E F G1 G2 H1 H2 H3 L L1 L2 L3 L5 L6 L7 M M1 R V4 Diam. MAX. 4.80 1.37 2.80 0.55 0.80 5.28 7.82 9.70 10.40 10.40 17.30 15.22 21.85 22.82 3.00 15.80 6.60 3.10 8.16 10.05 16.60 14.60 21.20 22.20 2.60 15.10 6.00 2.50 7.56 inch TYP. MIN. 0.169 0.046 0.094 0.014 0.024 0.193 0.292 0.366 0.396 0.653 0.575 0.835 0.874 0.102 0.594 0.236 0.098 0.298 0.50 90o MAX. 0.189 0.054 0.110 0.022 0.031 0.208 0.308 0.382 0.409 0.409 0.681 0.599 0.860 0.898 0.118 0.622 0.260 0.122 0.321 0.020 90 3.70 3.90 0.146 0.154 L E L1 M1 A M R C D Resin between leads L6 L7 V4 H2 H3 H1 G1 G2 F L2 L5 Diam L3 P023H3 15/17 VIPer20B / VIPer20BSP PowerSO-10 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 3.35 3.65 0.132 0.144 A1 0.00 0.10 0.000 0.004 B 0.40 0.60 0.016 0.024 C 0.35 0.55 0.013 0.022 D 9.40 9.60 0.370 0.378 D1 7.40 7.60 0.291 e 1.27 0.300 0.050 E 9.30 9.50 0.366 0.374 E1 7.20 7.40 0.283 0.291 E2 7.20 7.60 0.283 0.300 E3 6.10 6.35 0.240 0.250 E4 5.90 6.10 0.232 0.240 F 1.25 1.35 0.049 0.053 14.40 0.543 1.80 0.047 h 0.50 H 13.80 L 1.20 q 0.002 1.70 α 0.567 0.071 0.067 0o 8o B 0.10 A B 10 = E4 = = = E1 = E3 = E2 = E = = = H 6 = = 1 5 e 0.25 B SEATING PLANE DETAIL ”A” A C M Q h D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL ”A” α 0068039-C 16/17 VIPer20B / VIPer20BSP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 17/17