STMICROELECTRONICS VIPER53ESP-E

VIPer53EDIP - E
VIPer53ESP - E
OFF-line Primary Switch
Features
■
Switching frequency up to 300kHz
■
Current mode control with adjustable limitation
■
Soft start and shut-down control
■
Automatic burst mode in standby condition
(“Blue Angel“ compliant )
PowerSO-10
■
Undervoltage lockout with Hysteresis
■
Integrated start-up current source
■
Over-temperature protection
■
Overload and short-circuit control
■
Overvoltage protection
■
In compliance with the 2002/95/EC European
Directive
Description
The VIPer53E combines an enhanced current
mode PWM controller with a high voltage
MDMesh Power MOSFET in the same package.
Block diagram
DIP-8
Typical applications cover offline power supplies
with a secondary power capability ranging up to
30W in wide range input voltage, or 50W in single
European voltage range and DIP-8 package and
40W in wide range input voltage, or 65W in single
European voltage range and PowerSO-10
package, with the following benefits:
– Overload and short-circuit events
controlled by feedback monitoring and
delayed device reset;
– Efficient standby mode by enhanced pulse
skipping.
– Integrated start-up current source is
disabled during normal operation to reduce
the input power.
OSC
DRAIN
ON/OFF
OSCILLATOR
PWM
LATCH
OVERTEMP.
DETECTOR
R1
S
FF
Q
R2
R3 R4 R5
BLANKING TIME
SELECTION
PWM
COMPARATOR
UVLO
COMPARATOR
1V
HCOMP
0.5V
150/400ns
BLANKING
VDD
CURRENT
AMPLIFIER
8.4/
11.5V
STANDBY
COMPARATOR
8V
0.5V
Vcc
IC OMP
125k
4V
OVERLOAD
COMPARATOR
4.4V
OVERVOLTAGE
COMPARATOR
4.5V
18V
TOVL
January 2006
COMP
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SOURCE
1/31
www.st.com
31
Contents
VIPer53EDIP - E / VIPer53ESP - E
Contents
1
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Rectangular U-I Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Secondary Feedback Configuration Example . . . . . . . . . . . . . . . . . . . . 9
6
Current Mode Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8
High Voltage Start-up Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9
Short-Circuit and Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . 15
10
Regulation Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11
Special Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
12
Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
13
Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
14
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
DocRev1
VIPer53EDIP - E / VIPer53ESP - E
1
Electrical data
1.1
Maximum rating
Electrical data
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 1.
Absolute maximum rating
Symbol
VDS
ID
Parameter
Continuous Drain Current
Supply Voltage
VOSC
OSC Input Voltage Range
ITOVL
VESD
Unit
-0.3 ... 620
V
Internally limited
A
0 ... 19
V
0 ... V DD
V
-2 ... 2
mA
200
1.5
V
kV
Internally limited
°C
Continuous Drain Source Voltage (TJ= 25 ... 125°C) (1)
VDD
ICOMP
Value
COMP and TOVL Input Current Range (1)
Electrostatic Discharge:
Machine Model (R = 0Ω; C = 200pF)
Charged Device Model
TJ
Junction Operating Temperature
TC
Case Operating Temperature
-40 to 150
°C
Storage Temperature
-55 to 150
°C
TSTG
1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ
should be inserted in series with the TOVL pin.\
1.2
Thermal data
Table 2.
Symbol
Thermal data
Parameter
PowerSO-10 (1)
DIP-8 (2)
Unit
RthJC
Thermal Resistance Junction-case
Max
2
20
°C/W
RthJA
Thermal Resistance Ambient-case
Max
60
80
°C/W
1. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the DRAIN pin.
2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected
to the device tab.
DocRev1
3/31
Electrical characteristics
2
VIPer53EDIP - E / VIPer53ESP - E
Electrical characteristics
TJ = 25°C, VDD = 13V, unless otherwise specified
Table 3.
Symbol
BVDSS
IDSS
RDS(on)
Power section
Parameter
Test conditions
Drain-Source
Voltage
ID = 1mA; VCOMP = 0V
Off State Drain
Current
VDS = 500V; VCOMP = 0V; Tj = 125°C
Min.
Typ.
Max.
Unit
620
ID = 1A; VCOMP = 4.5V; VTOVL = 0V
Static Drain-Source
TJ = 25°C
On State Resistance
TJ = 100°C
V
0.9
150
µA
1
1.7
Ω
Ω
tfv
Fall Time
ID = 0.2A; VIN = 300V (1)
100
ns
trv
Rise Time
ID = 1A; VIN = 300V (1)
50
ns
Coss
Drain Capacitance
VDS = 25V
170
pF
CEon
Effective Output
Capacitance
200V < V DSon < 400V (2)
60
pF
1. On clamped inductive load
2. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain
to source voltage VDSon and the following formula:
V DSon 1.5
1
2
E ton = --- ⋅ C Eon ⋅ 300 ⋅ ⎛⎝ ----------------⎞⎠
2
300
Table 4.
Oscillator Section
Symbol
Parameter
FOSC1
Oscillator Frequency
Initial Accuracy
Test Conditions
RT = 8kΩ; CT = 2.2nF
Figure 15 on page 23
Min.
Typ.
Max.
Unit
95
100
105
kHz
93
100
107
kHz
RT = 8kΩ; CT = 2.2nF
4/31
Figure 17 on page 24
VDD = V DDon ... VDDovp;
TJ = 0 ... 100°C
FOSC2
Oscillator Frequency
Total Variation
VOSChi
Oscillator Peak
Voltage
9
V
VOSClo
Oscillator Valley
Voltage
4
V
DocRev1
VIPer53EDIP - E / VIPer53ESP - E
Table 5.
Symbol
Electrical characteristics
Supply Section
Parameter
Test Conditions
Min.
Typ.
Max. Unit
VDSstart
Drain Voltage Starting
Threshold
VDD = 5V; IDD = 0mA
34
IDDch1
Startup Charging Current
VDD = 0 ... 5V; VDS = 100V
Figure 9 on page 22
-12
mA
IDDch2
Startup Charging Current VDD = 10V; VDS = 100VFigure 9.
-2
mA
IDDchoff
Startup Charging Current VDD = 5V; V DS = 100VFigure 11.
in Thermal Shutdown
TJ > TSD - THYST
50
0
V
mA
IDD0
Operating Supply Current
Fsw = 0kHz; V COMP = 0V
Not Switching
8
IDD1
Operating Supply Current
Fsw=100kHz
Switching
9
11
mA
mA
VDDoff
VDD Undervoltage
Shutdown Threshold
Figure 9 on page 22
7.5
8.4
9.3
V
VDDon
VDD Startup Threshold
Figure 9.
10.2
11.5
12.8
V
VDDhyst
VDD Threshold
Hysteresis
Figure 9.
2.6
3.1
VDDovp
VDD Overvoltage
Shutdown Threshold
Figure 9.
17
18
19
V
Min.
Typ.
Max.
Unit
1.7
2
2.3
V/A
Table 6.
Symbol
HCOMP
V
Pwm Comparator Section
Parameter
∆VCOMP / ∆IDPEAK
VCOMPos VCOMP Offset
Test Conditions
VCOMP = 1 ... 4 V Figure 14.
dID/dt = 0
dID/dt = 0 Figure 14.
0.5
V
IDlim
Peak Drain Current
Limitation
ICOMP = 0mA; VTOVL = 0V
Figure 14.
dID/dt = 0
IDmax
Drain Current
Capability
VCOMP = VCOMPovl ; VTOVL = 0V
dID/dt = 0
td
Current Sense Delay
to Turn-Off
ID = 1A
VCOMPbl
VCOMP Blanking Time
Change Threshold
Figure 10 on page 22
tb1
Blanking Time
VCOMP < VCOMPBLFigure 10.
300
400
500
ns
tb2
Blanking Time
VCOMP > VCOMPBLFigure 10.
100
150
200
ns
Minimum On Time
VCOMP < VCOMPBL
450
600
750
ns
tONmin1
DocRev1
1.7
2
2.3
A
1.6
1.9
2.3
A
250
ns
1
V
5/31
Electrical characteristics
Table 6.
VIPer53EDIP - E / VIPer53ESP - E
Pwm Comparator Section
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
250
350
450
ns
tONmin2
Minimum On Time
VCOMP > VCOMPBL
VCOMPoff
VCOMP Shutdown
Threshold
Figure 13 on page 23
0.5
V
ICOMP=0mA (1)
4.5
V
0.6
mA
VCOMPhi
ICOMP
VCOMP High Level
COMP Pull Up Current VCOMP= 2.5V
1. In order to ensure a correct stability of the internal current source, a 10nF capacitor (minimum value 8nF)
should always be present on the COMP pin.
Table 7.
Overload Protection Section
Symbol
Parameter
VCOMPovl
VCOMP Overload
Threshold
VDIFFovl
VCOMPhi to VCOMPovl
Voltage Difference
Test Conditions
Min.
ITOVL = 0mA Figure 7 on page 20
Figure 7.
Max.
4.35
(1)
VDD = VDDoff ... VDDreg;
ITOVL= 0mA
Typ.
50
150
Unit
V
250
mV
(1)
VOVLth
VTOVL Overload
Threshold
Figure 7.
4
V
tOVL
Overload Delay
COVL = 100nF Figure 7.
8
ms
1. VCOMPovl is always lower than VCOMPhi
Table 8.
Over temperature Protection Section
Symbol
Test Conditions
TSD
Thermal Shutdown
Temperature
Figure 11 on page 22
THYST
Thermal Shutdown
Hysteresis
Figure 11 on page 22
Table 9.
6/31
Parameter
Min.
Typ.
Max.
140
160
°C
40
°C
Typical Output Power Capability
Type
European
(195 - 265Vac)
US / Wide range
(85 - 265Vac)
VIPer53EDIP-E
50W
30W
VIPer53ESP-E
65W
40W
DocRev1
Unit
VIPer53EDIP - E / VIPer53ESP - E
3
Pin connections and function
Pin connections and function
Figure 1.
Pin connection (top view)
COMP 1
8
TOVL
OSC 2
7
VDD
SOURCE 3
6
SOURCE 4
5
DRAIN
NC
NC
1
10
NC
2
9
NC
NC
3
8
NC
VDD
4
7
OSC
TOVL
5
6
COMP
DRAIN
DIP-8
Figure 2.
SOURCE
PowerSO-10
Current and voltage conventions
IDD
ID
VDD
DRAIN
IOSC
OSC
15V
VDS
VDD
TOVL
COMP
SOURCE
ITOVL
VOSC
ICOMP
VTOVL
VCOMP
Table 10.
Pin function
Pin Name
Pin Function
VDD
Power supply of the control circuits. Also provides the charging current of the external
capacitor during start-up.
The functions of this pin are managed by four threshold voltages:
- VDDon: Voltage value at which the device starts switching (Typically 11.5 V).
- VDDoff: Voltage value at which the device stops switching (Typically 8.4 V).
- VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V).
SOURCE
Power MOSFET source and circuit ground reference.
DRAIN
Power MOSFET drain. Also used by the internal high voltage current source during
the start-up phase, to charge the external VDD capacitor.
COMP
Allows the setting of the dynamic characteristic of the converter through an external
passive network. The useful voltage range extends from 0.5V to 4.5V. The Power
MOSFET is always off below 0.5V, and the overload protection is triggered if the
voltage exceeds 4.35V. This action is delayed by the timing capacitor connected to the
TOVL pin.
TOVL
Allows the connection of an external capacitor for delaying the overload protection,
which is triggered by a voltage on the COMP pin higher than 4.4V.
OSC
Allows the setting of the switching frequency through an external Rt-Ct network.
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7/31
Rectangular U-I Output characteristics
4
VIPer53EDIP - E / VIPer53ESP - E
Rectangular U-I Output characteristics
Figure 3.
Off Line Power Supply With Optocoupler Feedback
F1
C1
AC IN
D1
T1
C2
R1
R2
C3
T2
D2
L1
D4
D3
R4
R3
VDD
OSC
DRAIN
C8
C9
C10
CONTROL
R8
COMP
C4
TOVL
SOURCE
U2
C5
C12
10nF
R5
C7
R9
1k
C11
C6
R7
U3
R6
8/31
DocRev1
DC OUT
VIPer53EDIP - E / VIPer53ESP - E
5
Secondary Feedback Configuration Example
Secondary Feedback Configuration Example
The secondary feedback is implemented through an optocoupler driven by a programmable
zener diode (TL431 type) as shown in Figure 3 on page 8
The optocoupler is connected in parallel with the compensation network on the COMP pin
which delivers a constant biasing current of 0.6mA to the optotransistor. This current does
not depend on the compensation voltage, and so it does not depend on the output load
either. Consequently, the gain of the optocoupler ensures a constant biasing of the TL431
device (U3), which is responsible for secondary regulation. If the optocoupler gain is
sufficiently low, no additional components are required to a minimum current biasing of U3.
Additionally, the low biasing current protects the optocoupler from premature failure.
The constant current biasing can be used to simplify the secondary circuit: instead of a
TL431, a simple zener and resistance network in series with the optocoupler diode can
insure a good secondary regulation. Current flowing in this branch remains constant just as
it does by using a TL431, so typical load regulation of 1% can be achieved from zero to full
output current with this simple configuration.
Since the dynamic characteristics of the converter are set on the secondary side through
components associated to U3, the compensation network has only a role of gain
stabilization for the optocoupler, and its value can be freely chosen. R5 can be set to a fixed
value of 2.2kΩ, offering the possibility of using C7 as a soft start capacitor: When starting up
the converter, the VIPer53E device delivers a constant current of 0.6mA on the COMP pin,
creating a constant voltage of 1.3V in R5 and a rising slope across C7. This voltage shape,
together with the operating range of 0.5V to 4.5V provides a soft startup of the converter.
The rising speed of the output voltage can be set through the value of C7. The C4 and C6
values must be adjusted accordingly in order to ensure a correct startup.
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9/31
Current Mode Topology
6
VIPer53EDIP - E / VIPer53ESP - E
Current Mode Topology
The VIPer53E implements the conventional current mode control method for regulating the
output voltage. This kind of feedback includes two nested regulation loops:
The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET
output transistor is on, the inductor current (primary side of the transformer) is monitored
with a SenseFET technique and converted into a voltage. When VS reaches VCOMP, the
power switch is turned off. This structure is completely integrated as shown on the Block
Diagram of Figure on page 1, with the current amplifier, the PWM comparator, the blanking
time function and the PWM latch. The following formula gives the peak current in the Power
MOSFET according to the compensation voltage:
V COMP – V COMPos
I Dpeak = -------------------------------------------------H COMP
The outer loop defines the level at which the inner loop regulates peak current in the power
switch. For this purpose, VCOMP is driven by the feedback network (TL431 through an
optocoupler in secondary feedback configuration, see Figure 3 on page 8) and is sets
accordingly the peak drain current for each switching cycle.
As the inner loop regulates the peak primary current in the primary side of the transformer,
all input voltage changes are compensated for before impacting the output voltage. This
results in an improved line regulation, instantaneous correction to line changes, and better
stability for the voltage regulation loop.
Current mode topology also provides a good converter start-up control. The compensation
voltage can be controlled to increase slowly during the start-up phase, so the peak primary
current will follow this soft voltage slope to provide a smooth output voltage rise, without any
overshoot. The simpler voltage mode structure which only controls the duty cycle, leads
generally to high current at start-up with the risk of transformer saturation.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in the case of current spikes caused by primary side
transformer capacitance or secondary side rectifier reverse recovery time when working in
continuous mode.
10/31
DocRev1
VIPer53EDIP - E / VIPer53ESP - E
7
Standby Mode
Standby Mode
The device offers a special feature to address the low load condition. The corresponding
function described hereafter consists of reducing the switching frequency by going into burst
mode, with the following benefits:
– It reduces the switching losses, thus providing low consumption on the mains lines.
The device is compliant with “Blue Angel” and other similar standards, requiring less
than 0.5 W of input power when in standby.
– It allows the regulation of the output voltage, even if the load corresponds to a duty
cycle that the device is not able to generate because of the internal blanking time,
and associated minimum turn on.
For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM
latch and the Power MOSFET in the Off state as long as VCOMP remains below 0.5V (See
Block Diagram on page 2). If the output load requires a duty cycle below the one defined by
the minimum turn on of the device, the VCOMP net decreases its voltage until it reaches this
0.5V threshold (VCOMPoff). The Power MOSFET can be completely Off for some cycles, and
resumes normal operation as soon as VCOMP is higher than 0.5V. The output voltage is
regulated in burst mode. The corresponding ripple is not higher than the nominal one at full
load.
In addition, the minimum turn on time which defines the frontier between normal operation
and burst mode changes according to VCOMP value. Below 1.0V (VCOMPbl), the blanking
time increases to 400ns, whereas for higher voltages, it is 150ns Figure 10 on page 22 The
minimum turn on times resulting from these values are respectively 600 ns and 350 ns,
when taking into account internal propagation time. This brutal change induces an
hysteresis between normal operation and burst mode as shown on Figure 10 on page 22
When the output power decreases, the system reaches point 2 where VCOMP equals
VCOMPbl. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding
the effective turn-on time that should be needed at this output power level. Therefore the
regulation loop will quickly drive VCOMP to VCOMPoff (Point 3) in order to pass into burst
mode and to control the output voltage. The corresponding hysteresis can be seen on the
switching frequency which passes from FSWnom which is the normal switching frequency set
by the components connected to the OSC pin and to FSWstby. Note: This frequency is
actually an equivalent number of switching pulses per second, rather than a fixed switching
frequency since the device is working in burst mode.
As long as the power remains below PRST the output of the regulation loop remains stuck at
VCOMPsd and the converter works in burst mode. Its “density” increases (i.e. the number of
missing cycles decreases) as the power approaches P RST and finally resumes normal
operation at point 1. The hysteresis cannot be seen on the switching frequency, but it can be
seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power
level.
The power points value PRST and PSTBY are defined by the following formulas:
2
1
1
2
P R ST = --- • F SWnom • ( tb 1 + td ) • V IN • ------Lp
2
1
2
P STBY = --- • F SWnom • Ip ( V COMPbl ) • Lp
2
DocRev1
11/31
Standby Mode
VIPer53EDIP - E / VIPer53ESP - E
Where Ip(VCOMPbl2) is the peak Power MOSFET current corresponding to a compensation
voltage of VCOMPbl (1V). Note: The power point PSTBY where the converter is going into
burst mode does not depend on the input voltage.
The standby frequency FSWstby is given by:
P STBY
P SWstby = ----------------- • F SWnom
P RST
The ratio between the nominal and standby switching frequencies can be as high as 4,
depending on the Lp value and input voltage.
Figure 4.
.Standby Mode Implementation
ton
3
600ns
Minimum
turn on
1
2
350ns
VCOMP
VCOMPsd
VCOMPoff
VCOMPbl
PIN
1
PRST
3
2
PSTBY
FSW
FSWstby
12/31
FSWnom
DocRev1
VIPer53EDIP - E / VIPer53ESP - E
8
High Voltage Start-up Current Source
High Voltage Start-up Current Source
An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits in standby
mode with reduced consumption, and also supplies the external capacitor connected to the
VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the
UVLO logic, the device turns into active mode and starts switching. The start-up current
generator is switched off, and the converter should normally provide the needed current on
the VDD pin through the auxiliary winding of the transformer, as shown on Figure 3 on
page 8.
The external capacitor CVDD on the VDD pin must be sized according to the time needed by
the converter to start-up, when the device starts switching. This time tss depends on many
parameters, including transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin and possible secondary feedback
circuit. The following formula can be used for defining the minimum capacitor needed:
I D D1 ⋅ tss
C VD D > -----------------------V DDhyst
Figure 9 on page 22 shows a typical start-up event. V DD starts from 0V with a charging
current IDDch1 at about 9 mA. When about VDDoff is reached, the charging current is reduced
down to IDDch2 which is about 0.6mA. This lower current leads to a slope change on the VDD
rise. Device starts switching for VDD equal to VDDon, and the auxiliary winding delivers some
energy to VDD capacitor after the start-up time tss.
The charging current change at VDDoff allows a fast complete start-up time tSDU, and
maintains a low restart duty cycle. This is especially useful for short circuits and overloads
conditions, as described in the following section.
DocRev1
13/31
High Voltage Start-up Current Source
Figure 5.
VIPer53EDIP - E / VIPer53ESP - E
Start-up Waveforms
IDD
IDD1
t
IDDch2
IDDch1
VDD
tSS
VDDreg
VDDst
VDDsd
tSU
t
14/31
DocRev1
VIPer53EDIP - E / VIPer53ESP - E
9
Short-Circuit and Overload Protection
Short-Circuit and Overload Protection
A VCOMPovl threshold of about 4.4V has been implemented on the COMP pin. When VCOMP
goes above this level, the capacitor connected on the TOVL pin begins to charge. When
reaching typically VOVLth (4V), the internal MOSFET driver is disabled and the device stops
switching. This state is latched because of to the regulation loop which maintains the COMP
pin voltage above the V COMPovl threshold. Since the VDD pin does not receive any more
energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and the
device is reset, recharging the VDD capacitor for a new restart cycle. Note: If VCOMP drops
below the VCOMPovl threshold for any reason during the VDD drop, the device resumes
switching immediately.
The device enters an endless restart sequence if the overload or short circuit condition is
maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries
to restart, thus delivering its full power capability to the output. In order to keep the whole
converter in a safe state during this event, DRST must be kept as low as possible, without
compromising the real start-up of the converter. A typical value of about 10% is generally
sufficient. For this purpose, both VDD and TOVL capacitors can be used to satisfy the
following conditions:
C OVL > 12.5 ⋅ 10
–6
⋅ tss
C OVL ⋅ I D Dch2
4
1
C VDD > 8 ⋅ 10 ⋅ ⎛ -------------- – 1⎞ ⋅ -----------------------------------⎝D
⎠
V DDhyst
RST
Refer to the previous start-up section for the definition of tss, and CVDD must also be
checked against the limit given in this section. The maximum value of the two calculus will
be adopted.
All this behavior can be observed on Figure 2 on page 7. In Figure 7 on page 20 the value of
the drain current Id for VCOMP = VCOMPovl is shown. The corresponding parameter IDmax is
the drain current to take into account for design purposes. Since IDmax represents the
maximum value for which the overload protection is not triggered, it defines the power
capability of the power supply.
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Regulation Loop Stability
10
VIPer53EDIP - E / VIPer53ESP - E
Regulation Loop Stability
The complete converter open loop transfer function can be built from both power cell and
the feedback network transfer functions. A theoretical example can be seen in Figure 11 on
page 22 for a discontinuous mode flyback loaded by a simple resistor.
A typical schematic corresponding to this situation can be seen on Figure 3 on page 8. The
transfer function of the power cell is represented as G(s) in .Figure 11 on page 22 It exhibits
a pole which depends on the output load and on the output capacitor value. As the load of a
converter may change, two curves are shown for two different values of output resistance
value, RL1 and R L2. A zero at higher frequency values then appears, due to the output
capacitor ESR. Note: The overall transfer function does not depend on the input voltage
because of the current mode control. A typical regulation loop is shown on Figure 3 on
page 8 and has a fixed behavior represented by F(s) on Figure 11 on page 22. A double
zero due to the R 1-C1 network on the COMP pin and to the integrator built around the TL431
and R2-C2 is set at the same value as the maximum load RL2 pole.
The total transfer function is shown as F(s). G(s) at the bottom of Figure 11 on page 22. For
maximum load (plain line), the load pole begins exactly where the zeros of the COMP pin
and the TL431 stop, and this results in a first order decreasing slope until it reaches the zero
of the output capacitor ESR. The point where the complete transfer function has a unity gain
is known as the regulation bandwidth and has a double interest:
– The higher it is, the faster the reaction will be to an eventual load change, and the
smaller the output voltage change will be.
– The phase shift in the complete system at this point has to be less than 135° to
ensure good stability. Generally, a first-order slope gives 90° of phase shift, and a
second-order gives 180°.
In Figure 3 on page 8, the unity gain is reached in a first order slope, so the stability is
ensured.
The dynamic load regulation is improved by increasing the regulation bandwidth, but some
limitations have to be respected:
1.
As the transfer function above zero due the ESR capacitor is not reliable (the ESR itself
is not well specified, and other parasitic effects may take place), the bandwidth should
always be lower than the minimum of FC and ESR zero
2.
As the highest bandwidth is obtained with the highest output power (plain line with RL2
load in Figure 3, the above criteria will be checked for this condition and allows the
value of R4 if R1 is set to a fixed value (e.g., (2.2kΩ).
As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load
in Figure 3), the above criteria will be checked for this condition and allows to define the
value of R 4, if R1 is set fixed (2.2kΩ, for instance). The following formula can be derived:
R
4
P
G ⋅R
MAX
O
1
--------------------- ⋅ -------------------------------------------------------P
F
⋅R ⋅C
O UT2 BW2
L2 OUT
=
with:
P
and:
P
2
V
OUT
= ----------------O UT2
R L2
MAX
2
1
= --- ⋅ L ⋅ I
⋅F
2 P LIM SW
Go is the current transfer ratio of the optocoupler.
16/31
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VIPer53EDIP - E / VIPer53ESP - E
Regulation Loop Stability
The lowest load gives another condition for stability: The frequency FBW1 must not
encounter the third order slope generated by the load pole, the R1-C1 network on the
COMP pin and the R2-C2 network at the level of the TL431 on secondary side. This
condition can be met by adjusting both C1 and C2 values:
R
⋅C
P
L1 OUT
OU T1
C > ----------------------------------- ⋅ --------------------1
GO
PMAX
2
6.3 ⋅ --------- ⋅ R 1
R4
P OU T1
R L1 ⋅ C OUT
C > ----------------------------------------------- ⋅ --------------------2
G
P
O
MAX
6.3 ⋅ --------- ⋅ R ⋅ R
1
2
R
4
with:
P OUT1
2
V OUT
= ------------------R
L1
The above formula gives a minimum value for C1. It can be then increased to provide a
natural soft start function as this capacitor is charged by the current ICOMP at start-up.
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Special Recommendations
11
VIPer53EDIP - E / VIPer53ESP - E
Special Recommendations
10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to
ensure correct stability of the internal current source Figure 12 on page 22.
In order to improve the ruggedness of the device versus eventual drain overvoltages, a
resistance of 1kΩ should be inserted in series with the TOVL pin, as shown on Figure 12 on
page 22
Note:
18/31
This resistance does not impact the overload delay, as its value is negligible prior to the
internal pull-up resistance (about 125kΩ).
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VIPer53EDIP - E / VIPer53ESP - E
12
Software Implementation
Software Implementation
All the above considerations and some others are included included in ST design software
which provides all of the needed components around the VIPer device for specified output
configurations, and is available on www.st.com.
DocRev1
19/31
Operation pictures
13
VIPer53EDIP - E / VIPer53ESP - E
Operation pictures
Figure 6.
Rise and Fall time
ID
C<<C OSS
C
L
D
t
VDD
DRAIN
VDS
300V
OSC
CONTROL
90%
tfv
trv
COMP
t
10%
Figure 7.
Overloaded Event
VDD
Normal
operation
Abnormal
operation
VDDon
VDDoff
VCOMP
VDIFFovl
VTOVL
VOVLth
tOVL
VDS
Not
switching
Switching
20/31
DocRev1
TOVL
SOURCE
VIPer53EDIP - E / VIPer53ESP - E
Figure 8.
Operation pictures
Complete Converter Transfer Function
3.2 ⋅
P
M AX
--------------------P
OU T1
3.2 ⋅
P
MA X
--------------------P O UT2
1
-----------------------------------------π⋅R
⋅C
L1
OUT
1
-----------------------------------------π ⋅R
⋅C
L2
O UT
1
1
--------------------------------------------------2 ⋅ π ⋅ ESR ⋅ C
OUT
FS
1
-------------------------------------------------------------------2⋅π⋅R
⋅C
COM P
COM P
G
R
1
⋅ ------O R
4
FC
1
F S. GS
F BW2
1
FBW1
DocRev1
21/31
Operation pictures
Figure 9.
VIPer53EDIP - E / VIPer53ESP - E
Start-up VDD current
Figure 10. Blanking Time
tb
IDD
tb1
IDD0
VDDhyst
VDDoff
VDD
VDDon
IDDch2
tb2
VDS = 100 V
FSW = 0 kHz
VCOMP
IDDch1
VCOMPbl
Figure 11. Thermal Shutdown
VCOMPhi
Figure 12. Overvoltage Event
Tj
VDD
TSD
VDDovp
TSD-THYST
VDD
V DDon
VCOMP
Abnormal
operation
Automatic
startup
VDS
VCOMP
Not
switching
Switching
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VIPer53EDIP - E / VIPer53ESP - E
Operation pictures
Figure 13. Shutdown Action
Figure 14. Comp Pin Gain and Offset
VOSC
VOSChi
VOSClo
IDpeak
t
VCOMP
IDlim
IDmax
Slope = 1 / HCOMP
VCOMPoff
t
ID
VCOMP
VCOMPos
VCOMPovl VCOMPhi
t
Figure 15. Oscillator Schematic
Vcc
VDD
Rt
OSC
PWM
section
320 Ω
Ct
SOURCE
DocRev1
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Operation pictures
VIPer53EDIP - E / VIPer53ESP - E
The switching frequency settings shown on the graphic here below is valid within the
following boundaries:
Rt > 2kΩ
FSW = 300kHz
Figure 16. Oscillator Settings
Frequency (kHz)
300
2.2nF
1nF
4.7nF
100
10nF
22nF
10
1
10
100
RT (KΩ)
Figure 17. Typical Frequency Variation vs. Junction Temperature
Normalised Frequency
1.04
1.02
1
0.98
0.96
-20
0
20
40
60
80
Temperature (°C)
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DocRev1
100
120
VIPer53EDIP - E / VIPer53ESP - E
Operation pictures
Figure 18. Typical Current Limitation vs. Junction Temperature
Normalised IDlim
1.04
1.02
1
0.98
0.96
-20
0
20
40
60
80
100
120
Temperature (°C)
DocRev1
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Mechanical Data
14
VIPer53EDIP - E / VIPer53ESP - E
Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
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Table 11.
Mechanical Data
DIP8 Mechanical Data
Dimensions
Databook (mm)
Ref.
Nom.
Min
A
Max
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.26
E1
6.10
6.35
7.11
e
2.54
eA
7.62
eB
L
10.92
2.92
Package Weight
3.30
3.81
Gr. 470
Figure 19. Package Dimensions
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Mechanical Data
VIPer53EDIP - E / VIPer53ESP - E
Table 12.
PowerSO-10 Mechanical Data
Dimensions
Databook (mm)
Ref.
Nom.
A
3.35
Max
3.65
A1
0.00
0.10
B
0.40
0.60
c
0.35
0.55
D
9.40
9.60
D1
7.40
7.60
E
9.30
9.50
E1
7.20
7.40
E2
7.20
7.60
E3
6.10
6.35
E4
5.90
6.10
e
1.27
F
1.25
H
13.80
h
L
α
1.35
14.40
0.50
1.20
q
1.80
1.70
0°
8°
Figure 20. Package Dimensions
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Min
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VIPer53EDIP - E / VIPer53ESP - E
15
Order codes
Order codes
Table 13.
Order codes
Part Number
Package
Shipment
VIPer53ESPTR - E
PowerSO-10
Tape and reel
VIPer53ESP - E
PowerSO-10
Tube
VIPer53EDIP - E
DIP-8
Tube
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Revision history
16
VIPer53EDIP - E / VIPer53ESP - E
Revision history
Table 14.
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Document revision history
Date
Revision
12-Jan-2006
1
Changes
Initial release.
DocRev1
VIPer53EDIP - E / VIPer53ESP - E
Revision history
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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