VND5N07/VND5N07-1 VNP5N07FI/K5N07FM "OMNIFET": FULLY AUTOPROTECTED POWER MOSFET Table 1. General Features Figure 1. Package Type Vclamp RDS(on) Ilim VND5N07 VND5N07-1 VND5N07FI VND5N07FM 70 V 0.2 Ω 5A 3 3 2 1 ■ LINEAR CURRENT LIMITATION ■ THERMAL SHUT DOWN ■ SHORT CIRCUIT PROTECTION ■ INTEGRATED CLAMP ■ LOW CURRENT DRAWN FROM INPUT PIN ■ DIAGNOSTIC FEEDBACK THROUGH INPUT PIN ■ ESD PROTECTION ■ DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) ■ COMPATIBLE WITH STANDARD POWER MOSFET 1 DPAK TO-252 IPAK TO-251 3 1 ISOWATT220 2 SOT-82FM DESCRIPTION The VND5N07, VND5N07-1, VNP5N07FI and VNK5N07FM are monolithic devices made using STMicroelectronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. Fault feedback can be detected by monitoring the voltage at the input pin. Table 2. Order Codes Package Tube Tape and Reel DPAK VND5N07 VND5N0713TR IPAK VND5N07-1 – ISOWATT220 VND5N07FI – SOT-82FM VND5N07FM – REV. 2 June 2004 1/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Figure 2. Block Diagram Table 3. Absolute Maximum Ratings Value Symbol Parameter DPAK ISOWATT220 SOT-82FM Unit IPAK VDS Drain-Source Voltage (Vin = 0) Internally Clamped V Vin Input Voltage 18 V ID Drain Current Internally Limited A IR Reverse DC Output Current –7 A 2000 V Vesd Electrostatic Discharge (C = 100 pF, R =1.5 KΩ) Ptot Total Dissipation at Tc = 25 °C 60 24 9 W Tj Operating Junction Temperature Internally Limited °C Tc Case Operating Temperature Internally Limited °C -55 to 150 °C Tstg Storage Temperature Table 4. Thermal Data Symbol Parameter DPAK/IPAK ISOWATT220 SOT-82FM Unit Rthj-case Thermal Resistance Junction-case Max 3.75 5.2 14 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 100 62.5 100 °C/W 2/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM ELECTRICAL CHARACTERISTICS (Tcase = 25°C unless otherwise specified) Table 5. Off Symbol VCLAMP Parameter Drain-source Clamp Voltage Test Conditions ID = 200 mA; Vin = 0 Min. Typ. Max. Unit 60 70 80 V VCLTH Drain-source Threshold Voltage ID = 2 mA; Vin = 0 55 VINCL Input-Source Reverse Clamp Voltage Iin = –1 mA –1 IDSS Zero Input Voltage Drain Current (Vin = 0) VDS = 13 V; Vin = 0 VDS = 25 V; Vin = 0 IISS Supply Current from Input Pin VDS = 0 V; Vin = 10 V V –0.3 V 50 200 µA µA 250 500 µA Typ. Max. Unit 3 V 0.200 0.280 Ω Ω Max. Unit Table 6. On (1) Symbol Parameter Test Conditions VIN(th) Input Threshold Voltage VDS = Vin; ID + Iin = 1 mA RDS(on) Static Drain-source On Resistance Vin = 10 V; ID = 2.5 A Vin = 5 V; ID = 2.5 A Min. 0.8 Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% Table 7. Dynamic Symbol Parameter Test Conditions gfs (2) Forward Transconductance VDS = 13 V; ID = 2.5 A Coss Output Capacitance VDS = 13 V; f = 1 MHz; Vin = 0 Min. Typ. 3 4 S 200 300 pF Typ. Max. Unit Note: 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%. Table 8. Switching (3) Symbol td(on) tr td(off) tf td(on) tr td(off) tf (di/dt)on Qi Parameter Test Conditions Min. Turn-on Delay Time VDD = 15 V; Id = 2.5 A; 50 100 ns Rise Time Vgen = 10V; Rgen = 10 Ω 60 100 ns Turn-off Delay Time (see Figure 28) 150 300 ns 40 80 ns Fall Time Turn-on Delay Time VDD = 15 V; Id = 2.5 A; 150 250 ns Rise Time Vgen = 10V; Rgen = 1000 Ω 400 600 ns Turn-off Delay Time (see Figure 28) 3900 5000 ns 1100 1600 ns Fall Time Turn-on Current Slope VDD = 15 V; ID = 2.5 A Vin = 10 V; Rgen = 10 Ω 80 A/µS Total Input Charge VDD = 12 V; ID = 2.5 A; Vin = 10 V 18 nC Note: 3. Parameters guaranteed by design/characterization. 3/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM ELECTRICAL CHARACTERISTICS (cont’d) Table 9. Source Drain Diode Symbol Parameter Test Conditions Forward On Voltage ISD = 2.5 A; Vin = 0 trr(5) Reverse Recovery Time Qrr(5) Reverse Recovery Charge ISD = 2.5 A; di/dt = 100 A/µs VDD = 30 V; Tj = 25 °C (see test circuit, Figure 30) IRRM(5) Reverse Recovery Current VSD(4) Min. Typ. Max. Unit 1.6 V 150 ns 0.3 µC 5.7 A Note: 4. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 5. Parameters guaranteed by design/characterization. Table 10. Protection Symbol Parameter Test Conditions Min. Typ. Max. Unit 3.5 3.5 5 5 7 7 A A 15 40 20 60 µs µs Drain Current Limit Vin = 10 V; VDS = 13 V Vin = 5 V; VDS = 13 V tdlim(6) Step Response Current Limit Vin = 10 V Vin = 5 V Tjsh(6) Overtemperature Shutdown 150 °C Tjrs(6) Overtemperature Reset 135 °C Igf(6) Fault Sink Current Vin = 10 V; VDS = 13 V Vin = 5 V; VDS = 13 V Eas(6) Single Pulse Avalanche Energy starting Tj = 25 °C; VDD = 20 V Vin = 10 V; Rgen = 1 KΩ; L = 10 mH Ilim 50 20 0.2 mA mA J Note: 6. Parameters guaranteed by design/characterization. PROTECTION FEATURES During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry. The device integrates: – OVERVOLTAGE CLAMP PROTECTION: internally set at 70V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. – LINEAR CURRENT LIMITER CIRCUIT: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, and the ability to be driven from a TTL Logic circuit 4/15 junction temperature may reach the overtemperature threshold Tjsh. – OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 150°C. The device is automatically restarted when the chip temperature falls below 135°C. – STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model (with a small increase in RDS(on)). VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Figure 3. Thermal Impedance for DPAK/IPAK Figure 4. Thermal Impedance for ISOWATT220 Figure 5. Derating Curve Figure 6. Output Characteristics Figure 7. Transconductance Figure 8. Static Drain-source On Resistance vs Input Voltage 5/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Figure 9. Static Drain-Source On Resistance Figure 10. Static Drain-Source On Resistance Figure 11. Input Charge vs Input Voltage Figure 12. Capacitance Variations Figure 13. Normalized Input Threshold Voltage vs Temperature Figure 14. Normalized On Resistance vs Temperature 6/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Figure 15. Normalized On Resistance vs Temperature Figure 16. Turn-on Current Slope Figure 17. Turn-on Current Slope Figure 18. Turn-off Drain-Source Voltage Slope Figure 19. Turn-off Drain-Source Voltage Slope Figure 20. Switching Time Resistive Load 7/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Figure 21. Switching Time Resistive Load Figure 22. Switching Time Resistive Load Figure 23. Current Limit vs Junction Temperature Figure 24. Step Response Current Limit Figure 25. Source Drain Diode Forward Characteristics 8/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Figure 26. Unclamped Inductive Load Test Circuit Figure 27. Unclamped Inductive Waveforms Figure 28. Switching Times Test Circuits For Resistive Load Figure 29. Input Charge Test Circuit Figure 30. Test Circuit For Inductive Load Switching And Diode Recovery Times Figure 31. Waveforms 9/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM PACKAGE MECHANICAL Table 11. DPAK Mechanical Data Symbol millimeters Min Typ Max A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 B 0.64 0.90 B2 5.20 5.40 C 0.45 0.60 C2 0.48 0.60 D 6.00 6.20 D1 E 5.1 6.40 6.60 E1 4.7 e 2.28 G 4.40 4.60 H 9.35 10.10 L2 L4 0.8 0.60 R V2 1.00 0.2 0° Package Weight 8° Gr. 0.29 Figure 32. DPAK Package Dimensions P032P Note: Drawing is not to scale. 10/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Table 12. IPAK Mechanical Data millimeters Symbol Min Typ Max A 2.2 2.4 A1 0.9 1.1 A3 0.7 1.3 B 0.64 0.9 B2 5.2 5.4 B3 0.85 B5 0.3 B6 0.95 C 0.45 0.6 C2 0.48 0.6 D 6 6.2 E 6.4 6.6 G 4.4 4.6 H 15.9 16.3 L 9 9.4 L1 0.8 1.2 L2 0.8 1 Figure 33. IPAK Package Dimensions A1 C2 A3 A C H L B5 2 G = 1 = = E B2 = 3 B B6 = D = B3 L2 L1 Note: Drawing is not to scale. 11/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Table 13. ISOWATT220 Mechanical Data millimeters Symbol Min A Typ Max 4.4 4.6 B 2.5 2.7 D 2.5 2.75 E 0.4 0.7 F 0.75 1 F1 1.15 1.7 F2 1.15 1.7 G 4.95 5.2 G1 2.4 2.7 H 10 10.4 L2 16 L3 28.6 30.6 L4 9.8 10.6 L6 15.9 16.4 L7 9 9.3 3 3.2 B D A E Figure 34. ISOWATT220 Package Dimensions L3 L6 F2 H G G1 ¯ F F1 L7 1 2 3 L2 Note: Drawing is not to scale. 12/15 L4 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Table 14. SOT-82FM Mechanical Data millimeters Symbol Min Typ Max A 2.85 3.05 A1 1.47 1.67 b 0.40 0.60 b1 1.4 1.6 b2 1.3 1.5 c 0.45 0.6 D 10.5 10.9 e 2.2 2.8 E 7.45 7.75 L 15.5 15.9 L 1 1.95 2.35 Figure 35. SOT-82FM Package Dimensions Note: Drawing is not to scale. 13/15 VND5N07/VND5N07-1/VNP5N07FI/K5N07FM REVISION HISTORY Table 15. Revision History Date Revision June-1996 1 First Issue 18-June-2004 2 Stylesheet update. No content change. 14/15 Description of Changes VND5N07/VND5N07-1/VNP5N07FI/K5N07FM Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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