PROCESS CP709 Power Transistor PNP - Low Saturation Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 41.3 x 41.3 MILS Die Thickness 9.0 MILS Base Bonding Pad Area 9.5 x 9.2 MILS Emitter Bonding Pad Area 12.8 x 10.2 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au - 18,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 6,670 PRINCIPAL DEVICE TYPES CMPT7090L CXT7090L CZT7090L CMXT7090L 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (23- August 2006) PROCESS CP709 Typical Electrical Characteristics 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (23- August 2006)